System for controlling power plane of a printed circuit board by using a single voltage regulator to control switches during first and second power modes

[0002] 1. Field of the Invention

[0003] The present invention relates generally to power management, and in particular, relates to power plane control for a printed circuit board (PCB), such as a peripheral component interconnect (PCI) card useable for computer network applications.

[0004] 2. Background Information

[0005] The personal computer (PC) has become very popular in recent years as a tool for accessing the Internet. Desktop PCs and laptop PCs are examples of terminals that can be used to communicate with the Internet, where in some applications, one or more PCs in homes can share an existing telephone line when connecting to the Internet.

[0006] These PCs typically use PCI components, such as controllers and transceivers in the form of chips mounted on or coupled to one or more PCBs (sometimes referred to as a “card”), in order to perform various networking and peripheral device operations. Multi-layer PCBs have different portions of the needed interconnections on each layer. Some of these layers are dedicated to power supply distribution and some to ground (power supply return). The term “plane” is often used in reference to the various layers of a multi-layer PCB, such as those layers dedicated for power supply and ground.

[0007] Various standards specify the level of power that needs be provided to the power planes under different operating conditions. An example of these standards/specifications includes the Advanced Configuration and Power Interface (ACPI), revision 1.0b, published Feb. 8, 1999. The operating conditions that require different power levels include a full power mode, where full operating power is required, and a low power mode, where it is desirable to minimize power consumption.

[0008] To meet specification requirements for full power and low power modes, PCI board designers generally use a voltage regulator to control power to one power plane and a separate voltage regulator to control power to another power plane, if separate power planes are present. However, the use of multiple voltage regulators results in an increase in the number of total components per card. Such an increase in components disadvantageously uses up precious space on a card and results in increased costs.

[0009] A non-limiting and non-exhaustive embodiment of the present invention will be described in the following figure, wherein like reference numerals or labels refer to like parts unless otherwise specified.

[0010] FIG. 1 is a schematic diagram of a circuit according to an embodiment of the invention.

[0011] Embodiments of an apparatus and method for power plane control are described in detail herein. In the following description, some specific details are provided, such as the description of various capacitors in FIG. 1, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, materials, components, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0012] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0013] Referring to the schematic of FIG. 1, shown generally at 10 is a circuit according to an embodiment of the invention. The circuit 10 can be among the components mounted on a PCB, for example. In another embodiment, the circuit 10 may comprise part of circuitry on an integrated circuit chip.

[0014] The circuit 10 manages/controls the supply of power to two different power planes 12 and 14. The power planes 12 and 14 can be power planes for a PCI card useable for computer network applications in one embodiment. The power plane 12, in this embodiment, is referred to as “VDDCORE” and supplies power to portions of transceiver and controller components of a PCI card. The power plane 14, in this embodiment, is referred to as “VDDBUS” and supplies power to interfaces to a PCI bus. It is noted that a PCI implementation is described herein for the sake of example and simplicity of illustration. It is understood that embodiments of the invention can be applied to implementations other than PCI implementations, and therefore, the invention is not limited by the particular implementation.

[0015] In a full power mode, power from a main power supply VCC is provided to both power planes 12 and 14. In a low power mode, the power from the main power supply VCC is shut off, reduces, or isolated, so that power from an auxiliary power supply Vaux is provided to the power plane 12. In the low power mode, little or no power is provided to the power plane 14.

[0016] According to an embodiment of the invention, the main power supply VCC is 5 volts and the auxiliary power supply Vaux is 3.3 volts. It is to be appreciated, however, that the power supplies VCC and Vaux can take on any value(s) that are suitable for a particular application of the circuit 10, and therefore, the invention is not limited by the specific value(s) used. For simplicity of explanation and for illustrative purposes, these specific values for VCC and Vaux will be used throughout this description.

[0017] In an embodiment of the invention, the circuit 10 includes a voltage regulator 16. The voltage regulator 16 regulates the main power supply VCC and/or the auxiliary power supply Vaux, such that 3.3 volts, for example, are provided to the power planes 12 and 14, in a manner that will be described later below. An example of a suitable voltage regulator 16 that can be used by an embodiment of the invention is a Semtech 400 mA SmartLDO regulator.

[0018] The voltage regulator 16 has an input terminal Vin coupled to the main power supply VCC. In some types/models of voltage regulators, the voltage regulator 16 can have another input terminal coupled to the auxiliary power supply Vaux, but in other types/models of voltage regulators, an input terminal connected to the auxiliary power supply Vaux is not required (e.g., there can be a no connection “NC” at that input terminal). The voltage regulator 16 further includes an output terminal Vout and a drive terminal DR. In one embodiment, the drive terminal DR and the output terminal Vout, can be separate terminals, while in another embodiment of the voltage regulator 16, the drive terminal DR and the output terminal Vout can be the same terminal. The voltage regulator 16 can include one or more ground terminals GND.

[0019] In the embodiment of the circuit 10 shown in FIG. 1, the output terminal Vout of the voltage regulator 16 is coupled to the power plane 12. One or more capacitors 18-24 can be coupled between the output terminal Vout and ground. The capacitor 18 can be a bulk capacitor having a value of 4.7 microFarads, for example, to build up power, and the capacitors 20-24 can have a value of 0.1 microFarads, for example, to perform filtering. Similarly, a capacitor 26 having a value of 0.1 microFarads, for example, can be coupled between the auxiliary power supply Vaux and ground, and a capacitor 28 having a value of 0.1 microFarads, for example, can be coupled between the main power supply VCC and ground, to provide filtering. A bulk capacitor 30 having a value of 4.7 microFarads, for example, can be coupled between the main power supply VCC and ground, in order to store/build up power.

[0020] It is to be appreciated that the capacitors 18-24 and 26-30 and their specific connection(s) in the circuit 10 are described herein for illustrative purposes only, and so are not required to be connected exactly as shown in FIG. 1. Some embodiments of the invention may use other configurations/connections of capacitors, while other embodiments may not even utilize capacitors. Therefore, the invention is not limited by the presence, specific values, or connections of the capacitors 18-24 and 26-30.

[0021] The drive terminal DR of the voltage regulator 16 is coupled to gate terminals 32 and 34 of transistors 36 and 38, respectively, which act as switching devices. In one embodiment, the transistor 36 is a P-channel field effect transistor (FET), while the transistor 38 is an N-channel FET. P-channel junction field effect transistors (JFETs) or P-channel metal oxide silicon FETs (MOSFETs) can be used for the transistor 36. Similarly, N-channel JFETs or N-channel MOSFETs can be used for the transistor 38. Other types of FET devices may be used as well, including metal-insulator semiconductor FETs (MISFETs) and insulated gate FETs (IGFETs).

[0022] FETs are provided in an embodiment because they have advantageous features of requiring low drive at their gate terminals and/or having a small voltage drop/differential across their drain and source terminals when they turn on (e.g., the resistance r_DS(ON)is low). It is to be appreciated, however, that other types of devices that have these features may be used. Therefore, the invention is not limited by the specific type of transistor and/or switching device(s) used.

[0023] A drain terminal 40 of the transistor 36 is coupled to the auxiliary power supply Vaux, and a source terminal 42 is coupled to the power plane 12. A drain terminal 44 of the transistor 38 is coupled to the power plane 12, and a source terminal 46 is coupled to the power plane 14.

[0024] Diodes 48 and 50 may be optionally coupled, respectively, across the drain terminal 40 and the source terminal 42, and across the drain terminal 44 and the source terminal 46. The diodes 48 and 50 function as current direction controllers, but need not be included in some embodiments of the invention.

[0025] A low-resistance resistor 54 is coupled between the main power supply VCC and the gate terminals 32 and 34. The resistor 54 can have a value between 0 and 10 ohms, for example, and its illustrative connection shown in FIG. 1 provides an additional connection between the gate terminal 34 of the transistor 38 and the main power supply VCC.

[0026] Operation of the circuit 10 will now be described for the full power mode and for the low power mode. Beginning first with the full power mode, the power planes 12 and 14 are both required to be supplied with full operating voltage, which is 3.3 volts for discussion purposes herein. The main power supply VCC provides 5 volts to the input terminal Vin of the voltage regulator 16. The voltage regulator 16 changes this 5-volt input voltage to 3.3 volts and outputs this voltage at the output terminal Vout. The output terminal Vout is coupled to the power plane 12, thereby providing 3.3 volts to the power plane 12.

[0027] Meanwhile, the drive terminal DR of the voltage regulator 16 outputs 3.3 volts (or some other positive voltage in the range of 3.3 volts to 4.5 volts, for example) to the gate terminals 32 and 34 of the transistors 36 and 38, respectively. Because the transistor 36 is a P-channel FET, it is turned off (e.g., becomes an open circuit or open switch). The transistor 38, however, because it is an N-channel FET, is driven by the positive voltage at its gate terminal 34 and turns on (e.g., becomes a short circuit or closed switch). As a result, 3.3 volts is also supplied to the power plane 14. In effect, the turned-on transistor 38 connects the power planes 12 and 14 together, and both power planes 12 and 14 receive power from the regulated main power supply VCC during full power mode.

[0028] In some instances, because the drive terminal DR of the voltage regulator 16 is trying to drive two transistors, insufficient power or voltage (e.g., less than 3.0 volts) may be provided to the power plane 14. Therefore, the additional connection between the gate terminal 34 and the main power supply VCC (through the resistor 54) provides sufficient drive voltage to turn the transistor 38 completely on.

[0029] In low power mode, the main power supply VCC is typically turned off, reduced, or isolated. Therefore, no power is provided to the power plane 14, and the auxiliary power supply Vaux provides power to the power plane 12 as follows. First, a zero voltage at the input terminal Vin of the voltage regulator 16 (indicative of the turned-off main power supply VCC) results in a zero-volt output at the output terminal Vout and at the drive terminal DR. The zero volts at the drive terminal DR turns off (e.g., makes into an open circuit) the transistor 38, thereby isolating or cutting off the power plane 14 from a supply of power. Because the main power supply VCC is dropped in low power mode, there is also no current or voltage provided to the gate terminal 34 of the transistor 38 via the connection through the resistor 54.

[0030] Because the transistor 36 is a P-channel FET, the zero voltage at its gate terminal 32 (provided from the drive terminal DR of the voltage regulator 16) causes the transistor 36 to turn on (e.g., to become a short circuit). This provides an electrical connection between the auxiliary power supply Vaux and the power plane 12, thereby providing the power plane 12 with 3.0 to 3.3 volts.

[0031] Embodiments of the invention thus provide an apparatus and method for controlling/managing power supplied to power planes of a PCI card/components. This is done in one embodiment through the use of the single voltage regulator 16, plus a few other elements. Examples of load current supplied to the power planes 12 and 14 during full power mode is 365 mA, while 200 mA can be supplied to the power plane 12 during low power mode. These values are well within tolerance levels for commercially available voltage regulators 16, and also meet existing specifications. Furthermore, embodiments of the invention provide a robust but simple solution that can accommodate power management requirements for 1 Mbps and 10 Mbps Ethernet functionality, and for power management requirements for other implementations. The reduction in components used, as compared to existing dual-voltage regulator implementations, provides savings in terms of both costs and space.

[0032] The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

[0033] For example, while embodiments of the invention have been described herein as outputting a voltage at the drive terminal DR of the voltage regulator 16 that is positive when the main power supply VCC provided to the input terminal Vin is a positive voltage, it is possible to provide an embodiment where the voltage at the drive terminal is zero or negative when the voltage to the input terminal Vin is positive. In such a modification then, the transistor 38 can be a P-channel FET, and transistor 36 can be an N-channel FET. In other modifications, appropriate inverter(s) can be connected to the gate terminal(s) of the transistor 36 or the transistor 38 so that these two transistors can be both N-channel FETs or both P-channel FETs.

[0034] In another embodiment, the auxiliary power supply Vaux can be coupled to an input of the voltage regulator 16 (instead of being a no connection), such that at low power modes, positive voltage can be output from the output terminal Vout that is indicative of the positive input voltage from the auxiliary power supply Vaux, while zero or negative voltage can be output from the drive terminal DR to turn off the transistor 38 and to turn on the transistor 36. In yet another modification of this embodiment, the drive terminal DR can output a positive voltage at low power modes and still provide the appropriate turn-on/turn-off sequence for the transistors 36 and 38 if the appropriate conductivity type (e.g., N-channel or P-channel) transistors are used/connected, or if inverters are connected to their gates.

[0035] In other modifications, the main power supply VCC and the auxiliary power supply Vaux can come from a same source, instead of from two different sources. That is, the auxiliary power supply Vaux can simply be a reduced level of the main power supply VCC.

[0036] Furthermore, although a PCI implementation has been described herein for illustrative purposes, it is to be appreciated that some embodiments of the invention may be implemented with other systems/devices/cards, and therefore, the invention is not limited to PCI applications. For instance, an embodiment of the invention can be implemented for a Universal Serial Bus (USB) system. An embodiment of the invention also can be implemented for any type of system (not shown) where there may be a need to control/provide a limited current/power supply to a bus or power plane during a low power mode, and a current/power supply to a bus or power plane(s) during a full power mode. An example of such a system can have a Vsupply1 to provide a limited current supply that is always present, and a Vsupply2 that is present when the system is in a normal operating mode. A Vmain (such as a power plane or bus) is supplied only in the normal operating mode by Vsupply2 (or by both Vsupply1 and Vsupply2), such that full current is available to power all planes/busses. A Vcore (such as a power plane or bus) is maintained with its power supply (provided by Vsupply1) during a low power or sleep mode, such that limited current is provided to power only required planes/busses.

[0037] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.