Apparatus and Method for Reducing Power Consumption by Peripheral Devices After Downloading a Program Therefrom

1. Field of the Invention

The present invention relates to a microcomputer system, and more specifically to that capable of reducing power consumption.

2. Description of the Prior art

Referring to FIG. 6, prior practice of a microcomputer system is exemplified in the form of a block diagram.

As illustrated in the figure, designated at 1 is a microcomputer system such as a personal computer and controls, etc., which comprises a processor unit 5 (hereinafter, referred to as a microprocessing unit (MPU).) composed of a central processing unit (hereinafter, referred to as a CPU.) 2 and of a buffer 4 connected to the CPU2 through an internal bus 3, peripheral equipment composed of a ROM (read only memory) 7 as an external memory device connected to the buffer 4 through an external bus 6, of a RAM (random access memory) 8, and of a data input/output unit (hereinafter, referred to as an I/O unit.) such as a parallel port and a serial port, a block 12 connected to the MPU5, and a watch 13 connected to the external bus and including a counter, the MPU5 and the peripheral equipment 7 to 9 each comprising one-chip LSIS. The CPU2 drives the external bus 6 through the buffer 4 for reading a basic program stored in the ROM7, and writing and reading data and user programs into and out of the RAM8. Additionally, it inputs and outputs data into and from external equipment through the I/O unit 9.

The microcomputer system 1 must read out the programs and data stored in the ROM7 and the RAM8 for executing the programs through the CPU2. For this, an address of the ROM7 or the RAM8 in which such a program has been stored is outputted to the ROM7 or the RAM8 through the internal bus 3, buffer 4, and external bus 6. The ROM7 or RAM8 outputs the program or data stored therein at the foregoing address onto the external bus 6 which is in turn read into the CPU2 through the buffer 4 and the internal bus 3. Further, when the CPU2 executes any processing corresponding to the program or data and outputs data to the peripheral equipment 7 to 9, the data is outputted again through the internal bus 3, buffer 4, and external bus 6.

The prior microcomputer system constructed as described above must access the external bus 6 at all times to which the peripheral equipment 7 to 9 have been connected, consuming more power than required. Further, in order for it to operate as a system, it is needed to input/output data at all times so that it is impossible to turn off a power supply of the peripheral equipment 7 to 9 or reduce voltage as well as to restrict the consumed power of the entire system.

To solve the problem with the prior art, it is an object of the present invention to provide a microcomputer system capable of reducing power consumption.

To achieve the above object, a microcomputer system according to the present invention comprises a processor unit composed of a central processing unit and a buffer connected to said central processing unit through an internal bus, and peripheral equipment such as an external memory device and a data input/output unit, connected to said buffer through an external bus, said processor unit including an internal memory device connected to said central processing unit through the internal bus, said buffer including connection means for connection or disconnection with or from the external bus and consumed power reduction means controlled by said processor unit for reducing the consumed power of an input power supply of said peripheral equipment.

The above and other objects, features, and advantages of the invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating a microcomputer system as an embodiment of the present invention;

FIGS. 2 and 3 are circuit diagrams of power consumption reduction means, switching means, and a buffer, respectively;

FIGS. 4 and 5 are a view of status transition of the microcomputer system and a flow chart of the same in a power saving mode, respectively; and

FIG. 6 is a block diagram illustrating a prior microcomputer system.

Referring now to FIGS. 1 to 5, a microcomputer system of an embodiment of the present invention will be described. The same symbols shall be applied to the identical parts to those shown in FIG. 6, and the description thereof will be omitted.

As illustrated in FIG. 1, designated at 10 is an internal RAM as an internal memory device connected to a CPU2 through an internal bus 3 provided in a MPU5, and 11 is power consumption reduction means for controlling switching means 11a, 11b disposed between each peripheral device 7 to 9 and an input power supply, which means is controlled by the CPU2 through the internal bus 3, a buffer 4, and an external bus 6. The power consumption reduction means 11 and the switching means 11a, 11b are comprised respectively of an output port (flip-flop in the present case) and of transistors, as illustrated in FIG. 2. The buffer 4 includes disconnection means 4a for connection and disconnection with the external bus 6 and comprises a plurality of tri-state buffers as illustrated in FIG. 3.

In the following, operation of the embodiment will be described with reference to FIGS. 4 and 5 in which a status transition of the microcomputer system of the embodiment is illustrated and a flow chart of the same in a power saving mode is depicted. With the power supply turned on from a system interruption status A the operation changes to an ordinary mode B to start the microcomputer system 1 for ordinary processing. Herein, the microcomputer system advances to a power saving mode C by the program or instructions from an external device. In the power saving mode C, in step S1 it is judged whether or not the external bus 6 is at a status to be disconnected, as illustrated in FIG. 5. With such a status of the external bus 6 to be disconnected, in step S2 a program that is to be executed only in the MPU5 is read out from the ROM7 or the through the external bus 6, buffer 4, and internal bus 3, and stored in the internal RAM10. Then, in step S3 the power consumption reduction means 11 is operated by instructions from the CPU2 to switch-the switching means 11a, 11b toward the low power consumption. More specifically, the power supply of the ROM7 is turned off, and the power supplies of the RAM8 and the I/O 9 are reduced in their output voltages to their levels at which data in the RAM8 and the I/O 9 are not erased, for example from 5 V, an ordinary voltage, to 3 V, a low power consumption voltage. In step S4, the disconnection means 4a of the buffer 4 is controlled by the CPU2 to disconnect the MPU5 from the external bus 6. Further, in step 85 the program is executed only in the interior of the MPU5. Hereby, there is required no access to the external bus 6 which severely consumes power, and consumed power with the peripheral devices 7 to 9 is also reduced, so that power consumption of the entire system can be reduced. Additionally, in step S6 it is judged whether or not the program read into the internal RAM10 is completed, and is so, in step S7 the buffer 4 is connected to the external bus 6 and the peripheral devices 7 to 9 are returned to the original status of the operation, i.e., from the power saving mode C to the ordinary mode B shown in FIG. 4. Further, once the power supply is turned off in the power saving mode C, the operation changes to the system interruption status A, and if the power supply is again turned on, the system is started in the ordinary mode B.

Herein, although in the present embodiment the internal RAM10 was provided as the internal memory device, the present invention is not limited thereto. For example, provided the program and data to be executed in the power saving mode C are limited, there may be provided an internal ROM that has previously stored therein those program and data and hence may be permanently stationed those program and data in the MPU5.

According to the microcomputer system of the present invention, as described above, the internal memory device included in the processor device stores therein a program or data. Hereby, the microprocessor system is operable only with the processor device even if the external bus is disconnected through the disconnection means of the buffer. Therefore, power consumption due to the access to the external bus is eliminated by disconnection of the external bus through the buffer, and power consumption in input power supplies of the peripheral devices is reduced by the control of the power consumption reduction means through the processor device prior to disconnection of the external bus. Thus, the power consumption of the entire system can be reduced.