Device and method to cause a false data value to be correctly seen as the proper data value

[0002] The invention pertains to bidirectional data flow along a transmission line between a first semiconductor chip and a second semiconductor chip.

[0003] Problems can occur in high-speed bidirectional buses between two semiconductor chips when the transmission line electrical length exceeds the rise-time or fall-time of the signal. Setup times may not be met for the first bit received after a bus turnaround. The problem arises when the bus electrical design is such that the same electrical condition is used both for termination of the bus in its characteristic impedance and for driving one of the two logic levels. With buses of this design, when a bus turnaround occurs, the driving chip which is relinquishing the bus turns off its output driver and turns on its terminator, and the chip which is taking over the bus turns on its output driver.

[0004] When one chip drives the bus at the non-terminating electrical level (for example, a zero) and relinquishes the bus, at the end of its last bit time, the former driving chip will turn on its bus termination in preparation for receiving signals from the other chip. Since the same electrical condition is used both for termination of the bus in its characteristic impedance and for driving one of the logic levels, the chip that is relinquishing the bus actually drives an electrical signal transition (for example, from a zero to a one) down the bus during the transition period. This signal can be thought of as a transitional value. If the new bus master chip drives the opposite logic level (for example, a zero) during this transition time, the value driven by the new chip will not be seen at the relinquishing chip in time to be properly detected. This is because the relinquishing chip continues to see the transitional value that it is driving until that transitional value travels to the new bus driver and is reflected back to the relinquishing chip.

[0005] The length of the transmission time between the chips determines the length of time the relinquishing chip will receive the transition value and, therefore, the time during which it will be unable to detect the correct value from the new driving chip.

[0006] Prior solutions to this problem have been to shorten the distance between the two semiconductor chips or to slow down the clock to ensure the data arrives timely and accurately. For example, the clock could be slowed down to around 440 megahertz versus the more ideal operating frequency of 500 megahertz.

[0007] Another prior solution involves reducing the delay associated with the circuit logic through which the signal travels.

[0008] Another prior solution is to add an idle cycle as the first bus cycle after bus turnaround, thus ignoring bus activity during this cycle at the expense of decreased performance.

[0009] The present invention is a device and method for causing a false logical “one” to be correctly seen as a logical “zero” when a bidirectional signal travels between a first semiconductor chip and a second semiconductor chip, through a transmission line placed between the two semiconductor chips, by coupling an electrical network to the transmission line to cause an early electrical reflection.

[0010] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:

[0011] FIG. 1 is a schematic of two semiconductor chips connected by a transmission line according to an embodiment of the present invention;

[0012] FIGS. 2 and 3 show different embodiments of an electrical network connected to the transmission line;

[0013] FIG. 4 shows the glitch waveform and the modified glitch waveform at the input of the receiver of the first semiconductor chip for “0” to “0” situations; and

[0014] FIG. 5 shows the glitch waveform and the modified glitch waveform at the input of the receiver of the first semiconductor chip for a “0” to “1” situation.

[0015] FIG. 1 shows a schematic view of system 10 wherein the situation being described is shown. A transmission line glitch is launched from first semiconductor chip 11 as it changes from being bus master to receiver. This glitch is the transition voltage value from chip 11, and its reflection from chip 12, as will be discussed below. As bus master, chip 11 had been driving a low (i.e. zero) signal onto transmission line 130 which may be, for example, a (board trace) via transmission line portion 104 (which may be, for example, a chip package trace).

[0016] The change from master to receiver occurs when chip 11 turns off its pull-down resistor 103 by opening switch 102 and turns on its pull-up resistor 100 by closing switch 101. This serves to terminate the bus at chip 11's end. Switch 101 closing causes a rising edge (i.e. a logical one or a high signal) to travel down the transmission line from first chip 11 toward second chip 12.

[0017] Meanwhile, chip 12 (which has now become bus master) starts to pull down to zero through its pull-down resistor 123 by closing switch 122. Prior to switch 122 closing, current was already flowing through pull-up resistor 120 and out of the chip via trace 124. However, transmission line 124 (which may be a package trace on chip 12) was already at a low voltage from the logical zero that had been on the line before switch 102 opened. As a result, no change in voltage appears on transmission line 130 between chips 11 and 12 for this event.

[0018] When the rising edge from chip 11 (switch 101 closing) arrives at chip 12, there is a low at the input of receiver 125 caused by switch 122 closing. This low, in conjunction with the impedance discontinuity between board trace 130 and package trace 124, causes a reflection to be returned along the transmission line toward chip 11, forcing the bus to a low voltage. The glitch from chip 11 ends when the negative reflection from chip 12 arrives back at the input of receiver 105, causing a low level to exist over the length of the transmission path 124, 130 and 104 caused by the closing of switch 122.

[0019] The width of the glitch is set by the round-trip time of the interconnect 124, 130 and 104. If the round trip time is too long, the first bit sent by chip 12 will not be detected because (as will be discussed) the setup time is too short due to the effect of the glitch on chip 11's signal detector.

[0020] If the total interconnect length (chip, package and board trace lengths) of the bidirectional signal is short enough, the glitch will have ended and the signal will have reached its final intended value before chip 11 samples the bit. However, when the total interconnect length exceeds approximately Tr times V/2, where Tr is the rise or fall time of the signal and V is the velocity of propagation along the signal trace, the glitch width is too long and will interfere with the ability of chip 11 to correctly receive the first bit sent by chip 12.

[0021] This problem can be overcome by shortening the total interconnect length between the chips by a sufficient amount. However, shortening the interconnect length may be impractical due to the congested chip and board layouts.

[0022] The glitch can be made narrower if the reflection ending the glitch can be made to arrive at chip 11 earlier than it would normally arrive. This has the effect of shortening the width of the turnaround glitch so that setup time (as will be discussed) is sufficient for the first bit from chip 12 to be properly detected.

[0023] An important realization is that as the glitch propagates from chip 11 toward chip 12, the signal is already low at chip 12. By adding an impedance discontinuity, in the form of network 131, the glitch can be made to reflect back toward chip 11 “early”. This early reflection will arrive at chip 11 sooner than it would have had network 131 not been present, since the glitch would have to travel further before being reflected at switch 122. This early reflection reduces the glitch width, as determined at chip 11, thereby allowing a longer setup time so as to allow the first zero bit from chip 12 to be correctly recognized. Node 150 should be positioned at a location that minimizes reflections when chip 12 transitions to receive and that produces an earlier reflection sufficient to shorten the glitch when chip 11 transitions to receive.

[0024] FIG. 2 shows one embodiment of electrical network 131 in which 22 pF capacitor 250 is connected to ground and to terminal 150. This embodiment provides approximately 600 psec of additional setup time by shortening the glitch by 600 psec due to the early negative reflection from the capacitor.

[0025] A second embodiment of network 131, as shown in FIG. 3, uses a 326 psec long 50 ohm transmission line stub 301 that is connected to terminal 150 and that is grounded through 50 ohm resistor 302 and 10 pF capacitor 303. The 50 ohm 326 psec transmission line stub, 50 ohm resistor and 10 pF capacitor are optimal values for the present invention, although others may be used, depending on the impedance, edge rate and length of the transmission line. The reflection occurs as the glitch's rising edge encounters the impedance discontinuity caused by the connection of network 131. The energy transferred to the stub is absorbed by resistor 302, preventing an undesirable secondary reflection from the end of the stub from perturbing the signal on the interconnect traces 130, 104, and 124. A 10 pF capacitor 303 prevents the termination resistor from drawing DC current after the transient wavefront has passed. Compared to the single capacitor embodiment, this embodiment has the advantage that network 131 components may be located a distance from the transmission line where they may be placed more easily. Also, the reflections off of the stub are less severe than those from the capacitor of FIG. 2.

[0026] Electrical network 131 also causes reflections when chip 12 drives the transmission line. However, especially when using the embodiment of FIG. 3, these reflections alter the signal waveform less than when chip 11 drives the transmission line. This is in part because package trace 104 from chip 11 is a 33 ohm transmission line. The mismatch between the driving 33 ohm line and the 50 ohm board trace in parallel with the 50 ohm stub (FIG. 3) is less than when the 50 ohm board trace drives the 33 ohm package trace in parallel with the 50 ohm stub. Thus, the reflection is smaller when chip 12 drives than it is when chip 11 drives. Also, the reflection node is closer to the signal source, thus the reflection time is shorter, which creates a less significant effect on the signal.

[0027] Note that while impedance 130 is 50 ohms and impedance 124 is 33 ohms, these impedance's could be any relative magnitude and a reflection will occur where a discontinuity exists.

[0028] A problem with any early reflection solution designed to suppress the bus turnaround glitch caused when chip 11 sends a zero followed by chip 12 sending a zero is that the same physical effect occurs when chip 11 sends a zero followed by chip 12 sending a one. This causes the one to be incorrectly received as a zero, as illustrated in FIG. 5. One solution to this problem is to design the bus protocol so that chip 12 is never required to send a one as the first bit after a turnaround when it receives a zero as the previous bit.

[0029] Turning now to FIG. 4, there is shown a theoretical graph (using the embodiment of FIG. 3) showing volts on the vertical axis and nanoseconds on the horizontal axis. FIG. 4 shows the situation that occurs when there is a zero from chip 11 followed by a zero from chip 12. It should be understood that FIG. 4 (and FIG. 5) are sketches showing the relative slopes of the various signals at the receiver of chip 11 and are not graphs taken from actual circuits. Line 450 shows a clock timing pulse which is high (1.7 volts) at time=0 to 3.25 nanoseconds and then falls, portion 450-F until 4 nanoseconds, stays flat at 0.4 volts and starts rising at 5 nanoseconds, portion 450-R until 5.75 nanoseconds.

[0030] For illustrative purposes only, let us assume that the cutoff between a high “1” and a low “0” is 0.9 volts. Let us also assume that the setup window is 1,000 picaseconds (1 nanosecond) wide as shown between points 42 and 43. The setup window is the time just prior to a sample being taken where the signal being sampled must be stable.

[0031] Let us assume that the signal from chip 11 was zero (0.4 volts) at time=0. Line 401 represents that signal from the period 0 nanoseconds through 2 nanoseconds. Shortly after 2 nanoseconds, the control is switched from chip 11 to chip 12. In a perfect world, since there was a zero online from chip 11 followed by a zero on the same line from chip 12, line 401 would continue, as shown by line 402.

[0032] However, because of the glitch created by the rising pulse from chip 11, line 403 is shown rising from 0.4 volts up to 1.4 volts at roughly 3.5 nanoseconds. At that point, the reflected signal causes the waveform to begin to fall, as shown by line 404. As discussed above, the window for the setup time is between points 42 and 43 as the clock rises through 0.9 volts. Thus, clearly, at the same time, line 404 is both above and below 0.9 volts during the setup window time, violating the required setup time, which most likely will cause chip 11 to receive the value incorrectly as a one.

[0033] Using the electrical network of FIG. 2 or FIG. 3, the result will be a quicker falloff time of the glitch as shown by line 404′. Note that line 404′ is below 0.9 volts at all times during the window setup time. Accordingly, by using network 131 (FIG. 1) the circuit would register a zero (low) as it should even though a high glitch was on the line.

[0034] FIG. 5 shows a situation where the low from chip 11 is followed by a high from chip 12. In this situation, line 501 shows the reflected signal if there is no network present. In this situation, clearly a one would be detected, since line 501 is above setup window 42-43 at all times.

[0035] However, if electrical network 131 is being used, then the signal would behave as shown as line 501 prime and would dip through roughly 0.8 volts. Thus, during the setup window 42:43, the signal would appear unstable and, thus, would not read properly. However, the reason that this is not a problem in the circuit being discussed, is that there is in place a protocol which prevents a high from chip 12 from following a low from chip 11. Accordingly, the situation shown in FIG. 5 which could potentially be a problem, is not an issue when used with a protocol as discussed above.

[0036] While it is contemplated that both chips (circuits) are on the same board, this need not be the case. Also, the electrical network can be placed at other locations provided that the contained circuit elements are modified properly, in accordance with the teachings herein.

[0037] The illustrations herein are with respect to chip 11 transitioning from driving a zero to receiving a zero from chip 12. It should be understood that the same effect could occur on a transition from chip 12 driving a zero to chip 12 receiving a zero. Also, it should be understood that circuits with opposite biasing would behave the same way, such that a chip driving a one transitioning to receipt of a one could cause the same glitch (low instead of high). The concepts of this invention would cover these situations.