Termination structure for high speed, high pin density chips

[0002] 1. Field of the Invention

[0003] The present invention relates generally to high speed, high pin density chips, and more particularly, to a termination structure for a high speed, high pin density chips which reduces the effects of signal ringing, unwanted oscillations, overshoots and undershoots, while consuming little extra power.

[0004] 2. Description of the Related Art

[0005] In a high speed and high pin density package device (HSHD) which has on the order of several hundred pins, the parasitic parameters of the HSHD package device, such as the parasitic capacitance, inductance, mutual inductance and resistance become prominent and result in large cross talk and oscillation of the input signals. This cross talk and oscillation lower the performance of the HSHD device.

[0006] For example, consider the example in FIG. 1 of a high speed and high density package device (HSHD) 10 driving another HSHD 20 device through a PCB trace (T₁-T_N) 30. When the output signals 12 from the corresponding pins Pin₁-Pin_Nof the source HSHD 10 pass through the source high density package 40, the output signals 14 become somewhat irregular. Then the output signals 14 pass through the PCB trace (T₁-T_N) 30 through the destination high density package 50 to the input pins Pin₁-Pin_Nof the destination HSHD device 20. Due to the parasitic effects caused in the process of passing through the input pins' package R₁-R_N, the signals 16 exhibit oscillation, large glitches on the rising edge of the signals, and large overshoots and undershoots. The glitches, overshoots and undershoots greatly increase the setup process time of the input signal's valid logic level; in fact a large amplitude overshoot and/or undershoot may prevent the valid logic level from being set up during an entire clock cycle. Large overshoots may also damage the input CMOS logic.

[0007] The arrangement in FIG. 1 may also introduce signal ringing. Ringing results from signal reflection in the PCB trace (T₁-T_N) 30. There have been numerous attempts to reduce or eliminate signal ringing by address termination when the output signal of a device travels through a PCB trace to the input of another device. Source terminations (resistors) and end terminations (resistors and capacitors) have been used to attempt to solve the signal ringing problem. FIG. 1 is an example of a source termination structure. In FIG. 1, resistors R_E1, . . . , R_EN18 act as the source termination of the interface between HSHD 10 and HSHD 20.

[0008] FIG. 2 is an example of an end termination structure. In FIG. 2, resistors Rt₁. . . Rt_Nact as the end termination of the interface between HSHD 10 and HSHD 20. FIGS. 3a-3cillustrate several end termination structures. FIG. 3aillustrates the structure in FIG. 2, while FIG. 3billustrates a dual resistor (Rt_Mand Rt_N) configuration (similar to the configuration used in U.S. Pat. No. 5,519,353 to Rainal). FIG. 3cillustrates an alternative resistor Rt_Nand capacitor C_Nconfiguration. In FIGS. 1 and 2, the packages 40 and 50 are shown as being connected with a vertical line, in order to illustrate that the packages 40 and 50 are related to each other by mutual inductance.

[0009] As set forth above, the termination structures in FIGS. 3a-3care used to solve signal ringing in PCB traces, such as PCB trace (T_l-T_N) 30. However, other problems which result from the configuration of FIG. 1, include unwanted oscillations, glitches, undershoots and overshoots. These problems may be caused by the package 50 of the HSHD input device 20 itself. The termination structures in FIGS. 3a-3creduce, to some degree, the signal oscillations, glitches, undershoots and overshoots. However, the structures shown in FIG. 3band 3cconsume extra power, and the values of the resistor Rt_Nand capacitor C_Nin the structure of FIG. 3care difficult to choose when large parasitic effects exist in the package 50 of the HSHD input device 20.

[0010] For example, in FIG. 3c, if a signal of a certain frequency propagates from left (input) of the PCB trace Tn to right (output), a multiplying factor relative to the signal frequency, namely (1+jωRC)/(1+jω)(Ro+R)C), where Ro is the impedance of the PCB trace Tn, R is the resistance of Rtn, C is the capacitance of Cn and ω is the frequency of the signal may be added to the output signal. This results in the introduction of a pole and a zero evident in a Pole-Zero Plot, which may cause the output signal to oscillate. Another problem introduced by the arrangement in FIG. 3cis that the multiplying factor is usually smaller than 1, which reduces the valid input logic voltage level. This condition is worsened if R≦Ro. FIG. 3aand FIG. 3balso introduce this valid logic voltage level problem.

[0011] The signal oscillations, glitches, undershoots and overshoots problems caused by the package 50 of the HSHD input device 20 in FIG. 1 are illustrated in FIGS. 4a-4d. FIGS. 4a-4dillustrate the input signals 16 at Pin_Mwith the circuitry illustrated in FIG. 1. In particular, FIG. 4aillustrates the fastest operation condition of the HSHD input device 10, where the input signals 16 are propagated at the fastest speed and the largest oscillation or overshoot and undershoot may occur. This is termed the “worst case fast” condition. As illustrated between time 16 and 18 in FIG. 4a, large oscillations are apparent. FIG. 4cillustrates the leading edge of the waveform, including the large oscillations, of FIG. 4ain more detail.

[0012] FIG. 4billustrates a counterpart waveform for the waveform illustrated in FIG. 4a. In particular, FIG. 4billustrates the slowest operation condition or “worst case slow” condition of the HSHD input device 10, where the input signal 16sare propagated at the slowest speed, and the smallest oscillation, overshoot, or undershoot may occur. As illustrated between time 20 and 22 in FIG. 4b, large oscillations are apparent. FIG. 4dillustrates the leading edge of the waveform, including the large oscillations, in FIG. 4bin more detail.

[0013] The present invention provides a novel termination structure, which reduces the problems described above with conventional PCB traces between HSHD devices and their packages.

[0014] In particular, in one embodiment of the present invention, a resistor is inserted in series between a PCB trace and an input pin of the destination high density package. The series resistor, acting as a type of end termination, positively alters the waveforms of the signals input to the destination high speed density package. In particular, glitches and ringing after the input pin package or at the output of the destination high density package (at the gate for a CMOS transistor) are reduced. Overshoots and undershoots are also reduced. As a result, the input signals are usable and the interface between HSHD devices operates correctly. Further, the setup procedure of the valid logic level of the input signal can be accomplished much more quickly and is much more stable.

[0015] An additional advantage of the present invention is that the inserted series resistor consumes very little extra power (except for a little thermal energy). The inserted series resistor may increase the rise/fall times of the input signals very slightly, but this increase is much smaller than the increase caused by the conventional glitches, overshoots and undershoots. Therefore, if a signal is one of the input signals to which an inserted series resistor is added, the value selected for the inserted resistor for the input signal may depend on both overshoot and undershoot tolerances of the device and on the rise/fall time requirement of the signals.

[0016] FIG. 1 illustrates the conventional high speed, high density (HSHD) package device with a conventional source termination structure.

[0017] FIG. 2 illustrates the conventional HSHD device with a conventional end termination structure.

[0018] FIGS. 3a-3cillustrate alternative conventional end termination structures.

[0019] FIGS. 4a-4dare waveforms illustrating the “worst case fast” and “worst case slow” conditions in the conventional HSHD device with a conventional end termination structure.

[0020] FIG. 5 illustrates a device of the present invention, in one exemplary embodiment.

[0021] FIGS. 6a-6dare waveforms illustrating the “worst case fast” and “worst case slow” conditions in the device of FIG. 5.

[0022] As described above, the present invention is directed to a novel termination structure, which reduces the ringing, glitches, overshoots, and undershoots in an arrangement of HSHD devices and their packages, connected by PCB traces.

[0023] In one embodiment of the present invention, the novel termination structure includes a resistor inserted in series between the PCB trace and the input pin of the destination high density package. The series resistor, acting as a type of end termination, positively alters the waveforms of the output signals of the destination high density package. In particular, glitches and ringing after the input pin package or at the input transistor of the chip (at the gate for a CMOS transistor) are reduced. Overshoots and undershoots are also reduced. As a result, the input signals are usable and the interface between HSHD devices operates correctly. Further, the setup procedure of the valid logic level of the input signal can be accomplished much more quickly and is much more stable.

[0024] An additional advantage of the present invention is that the inserted series resistors consume very little extra power (except for a little thermal energy). Further, the value selected for the inserted resistor for an input signal may depend on both overshoot and undershoot tolerances of the device and on the rise time requirement of the signals. As discussed above with respect to FIG. 1, the output signals 12 of HSHD 10 pass through HSHD 10's output package 40 of S₁, . . . , S_N, source termination resistors Re₁, . . . , Re_N, and PCB traces 30 of T₁, . . . , T_N(PCB traces are modeled by a transmission line) to the input nodes of HSHD 20, identified In₁, . . . , In_N. From In_mto Pin_m(m=1, . . . , N) of HSHD 20, the signals must pass through the packages 50 of HSHD 20 which are shown as r₁, . . . , r_Nin FIG. 1. Large glitches, overshoots and undershoots occur because of the presence of the package's parasitic circuit network including parasitic capacitance, inductance, mutual inductance and resistance.

[0025] As illustrated in FIG. 5, if properly valued resistors 60 (Rr₁, . . . , Rr_N) are inserted in series between transmission line T_mand package 50 r_m(m=1, . . . , N), the glitches at Pin_m(m=1, . . . , N) of HSHD 20, and overshoots and undershoots are reduced. The transit curves of the input signals at Pin_malso become much smoother.

[0026] Choosing the resistance value of resistors 60 depends on the package parasitic characteristics, the signal frequency, and the rise/fall time requirements of the signal, which can be readily determined through transistor-level simulation, such as a SPICE simulation, which is known to one of ordinary skill in the art.

[0027] FIG. 5 illustrates the circuitry with resistors 60 (Rr₁, . . . , Rr_N) inserted in series between transmission line T_mpackage 50 r_m, while FIG. 1 illustrates the circuitry without inserted series resistors. Waveforms representing the input signals 16 of FIG. 5 are shown in FIGS. 6a-6d. FIGS. 4a-4dillustrate the input signals 16 at Pin_Min the circuitry illustrated in FIG. 1. FIGS. 6a-6dillustrate the input signals 16 at Pin_Mwith the circuitry illustrated in FIG. 5. In particular, FIG. 6aillustrates the fastest operation condition of the HSHD input device 10, where the input signals 16 are propagated at the fastest speed and the largest oscillation or overshoot and undershoot may occur. As illustrated between time 16 and 18 in FIG. 6a, the oscillations are much smaller than the oscillations illustrated in during the same time period in FIG. 4a. FIG. 6cillustrates the leading edge of the waveform of FIG. 6a. Comparing FIG. 6cto FIG. 4c, the oscillations in FIG. 6care much less apparent.

[0028] FIG. 6billustrates the slowest operation condition or “worst case slow” condition of the device of FIG. 5, where the input signal 16sare propagated at the slowest speed, and the smallest oscillation, overshoot, or undershoot may occur. As illustrated between time 20 and 22 in FIG. 6b, the oscillations are much smaller than the oscillations illustrated in during the same time period in FIG. 4b. FIG. 6dillustrates the leading edge of the waveform of FIG. 6b. Comparing FIG. 6dto FIG. 4d, the oscillations in FIG. 6dare much less apparent.

[0029] The arrangement in FIG. 5 has another application. By properly designing the output buffers of the HSHD 10 and 20, and properly choosing the values of R_s1, . . . , R_SN, and Rr₁. . . , Rr_N, the unidirectional HSHD 10-to-HSHD 20 interface can become a bi-directional interface, namely, signals can not only flow from HSHD 10 to HSHD 20, but signals can also flow from HSHD 20 to HSHD 10. In this embodiment, resistors Rr₁, . . . , Rr_Ncan also act as a source termination, and resistors R_s1, . . . , R_sNcan act in a manner similar to Rr₁, . . . Rr_Nin FIG. 2. As an example, in a Utopia interface, which is an interface standard between an Asynchronous Transfer Mode (ATM) device and a Physical layer (PHY) device, the signals flow bidirectionally. If the ATM device and the PHY device have similar timing requirements, they can also have similar I/O buffers with similar driving ability. As a result, the same value resistors of Rsl˜Rsn, and Rr1˜Rrn may be used in each device. Further, the valves of Rs1˜Rs and Rr1˜Rrn may be substantially equal to the impedance of the PCB trace, or larger or smaller than the impedance of the PCB trace, depending on the application.

[0030] As described above, the present invention lowers the signal ringing caused by signal reflection in a PCB trace. The present invention also reduces glitches, oscillations, overshoots, and undershoots. As a result, the input signals are usable and the interface between HSHD devices operates correctly. Further, the setup procedure of the valid logic level of the input signal can be accomplished much more quickly and is much more stable.

[0031] An additional advantage of the present invention is that the inserted series resistor consumes very little extra power (except for a little thermal energy).

[0032] Although the present invention has been described in connection with the above embodiments, the present invention is not limited to these embodiments. In particular, although the present invention has been described above in conjunction with one or more series resistors, other implementations, such as or any other implementations known to one of ordinary skill in the art could also be utilized. For example, the resistor 60 may be placed in the package 50 of input device 20 in FIG. 5. Thus, the density of the PCB board can be increased because the resistor 60 is part of the input device 20. Further, the package bonding materials need not be gold or another expensive metal; the material may be another cheaper or high resistance metals.

[0033] Further, although the present invention has been described above in conjunction with FIG. 5 as showing a resistor for each input signal, resistors could be applied to only a subset of input signals as required. Further, as described above in connection with an input signal, the parameters for determining the value of any given series resistor may depend on the type of input signal to which it is connected, these additional parameters being known to one of ordinary skill in the art.

[0034] Further, although the present invention has been described above in conjunction with HSHD devices, other devices, such as any low speed MOS VLSI chip or any other devices known to one of ordinary skill in the art could also be utilized. Further, although the present invention has been described above in conjunction with PCB traces, other connections, such as metal wire, cables, connectors, bridges, and vias (a hole path between the front side and back side of two-sided PCB board) or any other connections known to one of ordinary skill in the art could also be utilized.

[0035] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.