Method of compensating for interference in a signal generated by discrete multitone modulation, and circuit configuration for carrying out the method.

[0002] The invention lies in the telecommunications field. More specifically, the invention relates to a method for the compensation of interference in a signal generated by discrete multitone modulation, whereby the signal thus generated has a multiplicity of defined carrier frequencies, and each carrier frequency has a signal vector. The invention further pertains to a circuit configuration for carrying out the compensation method.

[0003] Discrete multitone modulation (DMT)—or multicarrier modulation—is a modulation method which is suitable in particular for the transmission of data via linearly distorting channels. By comparison with so-called single-carrier methods such as amplitude modulation, for example, which has only one carrier frequency, a multiplicity of carrier frequencies are used in discrete multitone modulation. Each individual carrier frequency is modulated in its amplitude and phase according to quadrature amplitude modulation (QAM). A multiplicity of QAM-modulating signals are thus obtained. A specific number of bits can thereby be transmitted per carrier frequency. Discrete multitone modulation is used for example for digital audio broadcasting (DAB) with the designation OFDM (Orthogonal Frequency Division Multiplex) and for the transmission of data via telephone lines with the designation ADSL (Asymmetric Digital Subscriber Line).

[0004] In the case of ADSL, data are transmitted from an exchange to a subscriber, connected via an analog connection in the telephone network, with the aid of a DMT-modulated signal. In that context, ETSI and ANSI standards stipulate that each carrier frequency has a bandwidth of approximately 4 kHz and transports at most up to 15 bit/s/Hz. The actual number of bits/s/Hz may be different for each carrier frequency, as a result of which the data rate and the transmission spectrum can be adapted to the transmission channel.

[0005] A DMT transmission system has a coder which combines the bits of a serial digital data signal to be transmitted into blocks. A complex number is assigned in each case to a specific number of bits in a block. A complex number represents a carrier frequency f_i=i/T where i=1, 2, . . . , N/2 of discrete multitone modulation. All the carrier frequencies f_iare distributed equidistantantly. T is the time duration of a block. By means of inverse Fourier transformation, the carrier frequencies represented by signal vectors are transformed into the time mode, where they directly represent N samples of a DMT signal to be transmitted. In order to be able to employ inverse fast Fourier transformation (IFFT), a power of two is chosen for N.

[0006] After the inverse fast Fourier transformation, a cyclic prefix is implemented, the last M (M<N) of the samples once again being attached to the beginning of a block. As a result, a periodic signal is simulated to a receiver when the transient process generated by a transmission channel has settled after M samples in accordance with a time T·M/N. The outlay on equalization in the receiver can be greatly reduced by the cyclic prefix, since after the demodulation in the receiver, it is only necessary to effect multiplication by the inverse transfer function of the transmission channel in order to eliminate the linear distortions of the transmission channel. This requires one complex or four real multiplications for each carrier frequency.

[0007] In the case of ADSL, the transmission channel is a two-wire line (copper pair). The two-wire line requires a long time for the transient process in relation to the length of a block. On the other hand, the additional transmission capacity required by the cyclic prefix should be as small as possible.

[0008] Given a block length of N=512, a cyclic prefix of M=32 is stipulated in the case of ADSL. However, the transient process of the two-wire line has still not settled after M=32 values. As a result, interference occurs in the receiver, and cannot be eliminated by a frequency domain equalizer.

[0009] Such interference can be reduced in the receiver with the aid of particular signal processing measures.

[0010] To that end, a time domain equalizer (TDEQ) is connected upstream of a demodulator. The time domain equalizer is designed as a digital transversal filter having adjustable coefficients. The task of the time domain equalizer is to shorten the transient process of the transmission channel. Accordingly, the number of impulse response values of the digital transversal filter must as far as possible be less than the M samples of the cyclic prefix. The design of such time domain equalizers is described by Al-Dhahir and Cioffi in “Optimum Finite-Length Equalization for Multicarrier Transceivers,” IEEE Trans. On Comm., Vol. 44, No. 1, January 1996. What is disadvantageous, however, is the high additional outlay on circuitry for the time domain equalizer, caused by the high number of coefficients (between 20 and 40 coefficients), exhibited by the digital transversal filter used as time domain equalizer. A further disadvantage of such time domain equalizers is the high computation complexity, which amounts to approximately 50 to 100 million multiplications per second given a filter length of 20 to 40 coefficients and necessitates a correspondingly high outlay on circuitry. In addition, each coefficient has to be adjusted for adaptation of the digital transversal filter.

[0011] It is accordingly an object of the invention to provide a method for the compensation of interference in a signal generated by discrete multitone modulation and a circuit configuration for carrying out the method, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which require a smaller outlay on circuitry than time domain equalizers and can be implemented as a simple and fast algorithm and as a simple circuit, respectively.

[0012] With the foregoing and other objects in view there is provided, in accordance with the invention, a method of compensating for interference in a signal generated by discrete multitone modulation, wherein the signal generated by discrete multitone modulation has a multiplicity of carrier frequencies each having a signal vector. The method comprises the following method steps:

[0013] generating an error signal vector from a reference signal vector, which is a signal vector of the multiplicity of signal vectors in the signal generated by discrete multitone modulation;

[0014] assigning to each of the signal vectors of the multiplicity of signal vectors, except for the reference signal vector, a set of adjustable coefficients and multiplying the error signal vector with the adjustable coefficients; and

[0015] subsequently adding the error signal vector to each remaining signal vector of the multiplicity of signal vectors for the purpose of compensating for interference.

[0016] In other words, an error signal vector is generated from a reference signal vector, which is a signal vector from the multiplicity of signal vectors. The error signal vector is added to each of the remaining signal vectors of the multiplicity of signal vectors for the purpose of compensating for interference. Each of the signal vectors of the multiplicity of signal vectors, except for the reference signal vector, is assigned a set of adjustable coefficients by which the error signal vector is multiplied prior to the addition. In an advantageous manner, the error signal is calculated in one simple step of the method and added to the remaining carrier frequencies in a further simple step. On account of the interdependence of interference of each individual carrier frequency, it suffices to calculate the error signal from a carrier frequency. In contrast to time domain equalization, the method can be designed as an algorithm in a very simple manner.

[0017] In accordance with an added feature of the invention, the adjustable coefficients are adapted in accordance with transmission conditions of the carrier frequency having the signal vector assigned to the adjustable coefficients. In an advantageous manner, this adaptation of the coefficients results in better suppression of interference as may be contained in the signal vector.

[0018] In accordance with an additional feature of the invention, the adjustable coefficients are adjusted using an iterative algorithm for the purpose of minimizing errors.

[0019] In accordance with another feature of the invention, the adjustable coefficients are adjusted with a mean square error algorithm.

[0020] In accordance with a further feature of the invention, the reference signal vector is mapped in a value-discrete reference signal vector and the value-discrete reference signal vector is subtracted from the reference signal vector for generating the error signal vector.

[0021] With the above and other objects in view there is provided, in accordance with the invention, a circuit configuration for compensating for interference in a signal generated by discrete multitone modulation, the signal generated by discrete multitone modulation having a multiplicity of carrier frequencies in the frequency domain, and each carrier frequency having a signal vector, comprising:

[0022] a first decision circuit receiving a reference signal vector, the first decision circuit mapping the reference signal vector into a value-discrete reference signal vector;

[0023] a subtractor circuit connected to the first decision circuit for forming an error signal vector by subtracting the reference signal vector and the value-discrete reference signal vector from one another;

[0024] a multiplicity of adders receiving the error signal vector and adding the error signal vector to each of the remaining signal vectors, except for the reference signal vector; and

[0025] multiplier circuits connected upstream of each of the adders in a signal flow direction, the multiplier circuits multiplying the error signal vector by adjustable coefficients.

[0026] In other words, a reference signal vector is fed to a first decision circuit, which maps the reference signal vector into a value-discrete reference signal vector. A subtractor circuit for forming an error signal vector subtracts the reference signal vector and the value-discrete reference signal vector from one another. The error signal vector is fed to a multiplicity of adders, which add the error signal vector to each of the remaining signal vectors, except for the reference signal vector. Multiplier circuits which multiply the first error signal vector by adjustable coefficients are connected upstream of each of the multiplicity of adders.

[0027] In accordance with again an added feature of the invention, the adjustable coefficients are adjustable by a manipulated variable. In a preferred embodiment, the manipulated variable is a power of two. Choosing a power of two for the manipulated variable allows the adjustment of the adjustable coefficients to be carried out by means of a simple shift register.

[0028] With the above and other objects in view there is also provided, in accordance with an alternative embodiment of the invention, a method of compensating for interference in a signal generated by discrete multitone modulation, wherein the signal generated by discrete multitone modulation has a multiplicity of carrier frequencies each having a signal vector, which comprises the following method steps:

[0029] defining a signal vector of a multiplicity of signal vectors in a signal generated by discrete multitone modulation as a reference signal vector, and generating an error signal vector from the reference signal vector;

[0030] calculating interference with the remaining signal vectors of the multiplicity of signal vectors in approximation from the error signal vector; and

[0031] subtracting the calculated interference from the respective signal vector of the multiplicity of signal vectors for interference compensation.

[0032] In this alternative embodiment, the interference in the remaining signal vectors of the multiplicity of signal vectors is calculated as an approximation from the error signal vector, and the calculated interference is subtracted from the respective signal vector of the multiplicity of signal vectors for the purpose of compensating for interference. It is advantageous that adaptive adjustment of coefficients is not necessary in this case. As a result, convergence problems during the adaptation cannot occur either.

[0033] Other features which are considered as characteristic for the invention are set forth in the appended claims.

[0034] Although the invention is illustrated and described herein as embodied in a method for the compensation of interference in a signal generated by discrete multitone modulation, and circuit configuration for carrying out the method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

[0035] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

[0036] FIG. 1 is a schematic diagram of a first exemplary embodiment of the circuit configuration according to the invention for the compensation of interference in a signal generated by discrete multitone modulation;

[0037] FIG. 2 is a circuit schematic of an exemplary embodiment of the circuit configuration for forming the weighting coefficients of the error signal;

[0038] FIG. 3 is a plot diagram with the signal-to-noise ratio at the input of the decision circuit; and

[0039] FIG. 4 is a schematic diagram of a second exemplary embodiment of the circuit configuration for the compensation of interference in a signal generated by discrete multitone modulation.

[0040] Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is seen an exemplary embodiment of the circuit configuration for the compensation of interference in a signal generated by discrete multitone modulation. A serial-parallel converter 1 receives digital samples of a signal IN generated by discrete multitone modulation. The serial-parallel converter 1 forms blocks from the digital samples fed in, one block having a multiplicity of N parallel signals which are fed to a demodulator 2. In this case, N should be a power of two.

[0041] The demodulator 2 is a fast Fourier transformer which converts the multiplicity of N parallel signals fed in in the time domain into a multiplicity of n carrier frequencies f0-fn in the frequency domain. Each carrier frequency is modulated by quadrature amplitude modulation (QAM) in the context of the discrete multitone modulation. Each carrier frequency has a signal vector 20a, 20bto 2na, 2nb.

[0042] By way of example, in the case of ADSL (Asymmetric Digital Subscriber Line), of 256 carrier frequencies each having a frequency spacing of 4.3125 kHz, the carrier frequencies 7 to 250 corresponding to a frequency spectrum of 30.1875 kHz to 1078.125 kHz are utilized for the signal transmission.

[0043] Each signal vector has two elements, which constitute a real part and an imaginary part of a complex number. The absolute value and the phase of the complex number correspond to the carrier frequency (frequency channel, channel) with QAM-modulated signal.

[0044] In accordance with the multiplicity of signal vectors or carrier frequencies, provision is made of n frequency domain equalizers 30, . . . , 3n(FDEQ) for the equalization of the signal vectors 20a, 20bto 2na, 2nb. A frequency domain equalizer is used for the channel equalization of a signal vector. For this purpose, each frequency domain equalizer can be adapted to the transmission characteristics of the transmission channel that are specific to a carrier frequency.

[0045] An equalized signal vector a₀, b₀and a_n, b_nis respectively present at the output of each frequency domain equalizer 30, . . . , 3n.

[0046] A decision circuit 40 and 4nis respectively connected downstream of each frequency domain equalizer 30, . . . , 3n. A decision circuit decides which signal state in the signal state space of the carrier frequencies modulated by QAM is assigned to a signal vector fed in. A signal state corresponds to a value-discrete signal vector having a value-discrete amplitude and a value-discrete phase. What is decisive for correct assignment of a signal vector to a value-discrete signal vector is a signal vector that is interfered with as little as possible by the transmission.

[0047] A decoder circuit 50, . . . , 5nis respectively connected downstream of each decision circuit 40, . . . , 4n. A decoder circuit decodes, from a value-discrete signal vector fed in, the binary signals OUT0 to OUTn contained in the signal vector.

[0048] An arbitrary signal vector a₀, b₀is used as reference signal vector. The reference signal vector is converted into a value-discrete reference signal vector a₀′, b₀′ by the first decision circuit 40. The reference signal vector is used to correct all of the remaining signal vectors. This is possible on account of the interdependence of the individual signal vectors.

[0049] An error signal vector is generated from the reference signal vector and is used to correct all the other signal vectors. For this purpose, the real part a₀and the value-discrete real part a₀′ of the reference signal vector are fed to a first subtractor circuit 6 and subtracted from one another. A real part Δa₀of a complex number which represents the error signal contained in the error signal vector Δa₀, Δb₀is present at the output of the first subtractor circuit 6. The imaginary part b₀and the value-discrete imaginary part b₀′ of the reference signal vector are fed, in a corresponding manner to the real parts, to a second subtractor circuit 7. An imaginary part Δb₀of the complex number which represents the error signal contained in the error signal vector Δa₀, Δb₀is present at the output of the second subtractor circuit 7.

[0050] The formula for forming the elements of the error signal vector from the elements of the reference signal vector reads as follows:

[0051] Δa₀=a₀−a′₀and Δb₀=b₀−b′₀

[0052] The error signal vector Δa₀, Δb₀is adapted to the signal vector to be corrected and is added, for the purpose of correction, to the signal vector corresponding to a channel to be corrected.

[0053] This method is described below using the example of an arbitrary channel corresponding to a signal vector a_n, b_n. In terms of the method, every channel is corrected except for the channel having the reference signal vector.

[0054] The real part Δa₀of the error signal vector is fed to a first multiplier circuit 8 and, in parallel, to a second multiplier circuit 11. The first multiplier circuit 8 multiplies the real part Δa₀of the error signal vector by a first coefficient C_aaⁿ. The second multiplier circuit 11 multiplies the real part Δa₀of the error signal vector by a second coefficient C_abⁿ.

[0055] The imaginary part Δb₀of the error signal vector is fed to a third multiplier circuit 9 and, in parallel, to a fourth multiplier circuit 10. The third multiplier circuit 9 multiplies the imaginary part Δb₀of the error signal vector by a third coefficient C_baⁿ. The fourth multiplier circuit 10 multiplies the imaginary part Δb₀of the error signal vector by a fourth coefficient C_bbⁿ.

[0056] The output signal of the first multiplier circuit 8 and of the third multiplier circuit 9 are fed to a first adder circuit 12. A real part a_n, of the signal vector, which is present at the output of a frequency domain equalizer 3n, is likewise fed to the first adder circuit 12. The first adder circuit adds the three signals fed in to form an error-corrected real part a_n*of the signal vector.

[0057] The output signal of the second multiplier circuit and of the fourth multiplier circuit are fed to a second adder circuit 13. An imaginary part b_nof the signal vector, which is present at the output of the second frequency domain equalizer 3n, is furthermore fed to the second adder circuit 13. An error-corrected imaginary part b_n*of the signal vector is present at the output of the second adder circuit 13, which adds the three signals fed in.

[0058] The method described above can be expressed by the following formulae:

[0059] a_n*=a_n+C_aaⁿ·Δa₀+C_baⁿΔb₀

[0060] b_n*=b_n+C_abⁿ·Δa₀+C_bbⁿ·Δb₀

[0061] The error-corrected real part a_n*and the error-corrected imaginary part b_n*of the signal vector are fed to a second decision circuit 4n, which converts the error-corrected real part a_n*and the error-corrected imaginary part b_n*into a value-discrete real part a_n*′ and into a value-discrete imaginary part b_n*′ respectively, of a value-discrete signal vector a_n*′, b_n*′.

[0062] The value-discrete signal vector a_n*′, b_n*′ is fed to a second decoder circuit 5n. The second decoder circuit 5ndecodes signals from the signal vector fed in.

[0063] In this method, for each signal vector except for the reference signal vector, the error signal vector is weighted in accordance with the channel to be corrected and added to the signal vector representing the channel.

[0064] The weighting coefficients C_aaⁿ, C_baⁿ, C_abⁿand C_bbⁿfor the weighting of the error signal vector can be progressively adjusted using an iterative algorithm for the purpose of minimizing errors, such as the mean square error algorithm (MSE algorithm) for example (in this case k designates a discrete point in time):

[0065] C_aaⁿ(k)=C_aaⁿ(k−1)−g ·Δa₀(k)·Δa_n(k)

[0066] C_bbⁿ(k)=C_bbⁿ)(k−1)−g·Δb₀(k)·Δb _n(k)

[0067] C_abⁿ(k)=C_abⁿ(k−1)−g·Δa₀(k)·Δb_n(k)  (1)

[0068] C_baⁿ(k)=C_baⁿ(k−1)−g·Δb₀(k)·Δa_n(k)

[0069] Both the error signal vector Δa₀, Δb₀of the reference signal vector and an error signal vector Δa_n, Δb_nof the n^thchannel to be corrected are required in order to calculate the weighting coefficients C_aaⁿ, C_ban, C_abⁿ, and C_bbⁿin accordance with the formulae (1). In this case, the error signal vector Δa_n, Δb_nof the n^thchannel to be corrected is formed in a corresponding manner to the error signal vector of the reference channel.

[0070] If the intention is to eliminate interference from a signal vector only in the lower frequency domain, a simplified algorithm with symmetrical weighting coefficients C_aaⁿ, C_baⁿ, C_abⁿand C_bbⁿis sufficient. This may be the case for example when using a time domain equalizer connected upstream of the demodulator 2 and the serial-parallel converter 1. The requirements made of the time domain equalizer are then less stringent than the requirements made of a time domain equalizer without interference compensation. The weighting coefficients C_aaⁿ, C_baⁿ, C_abⁿand C_bbⁿare calculated as follows in this case:

[0071] C_bbⁿ(k)=C_aaⁿ(k−1)

[0072] C_bbⁿ(k)=−C_aaⁿ(k−1)  (2a)

[0073] In an advantageous manner, the storage space required for storing the weighting coefficients is reduced as a result of the symmetry of the weighting coefficients.

[0074] In this case the algorithm for adjustment reads as follows:

[0075] C_aaⁿ(k)=C_aaⁿ(k−1)−g·(Δa₀(k)·Δa_n(k)+Δb₀(k)·Δb_n(k)

[0076] C_abⁿ(k)=C_abⁿ(k−1)−g·(Δa₀(k)·Δb_n(k)+Δb₀(k)·a_n(k))  (2)

[0077] The circuit configurations represented in FIG. 2 calculate the weighting coefficients C_aaⁿ, C_baⁿ, C_abⁿand C_bbⁿaccording to the MSE algorithm in accordance with the formulae (1).

[0078] Each of the circuit configurations has a first multiplier 100, which multiplies the real part Δa₀or respectively the imaginary part Δb₀of the error signal vector of the reference channel by the real part Δa_nor respectively the imaginary part Δb_nof the error signal vector formed on the channel to be corrected.

[0079] A second multiplier 101, connected downstream of the first multiplier 100 in the signal flow direction, multiplies the result of the first multiplier 100 by a manipulated variable g, which is formed in a circuit block 102.

[0080] The manipulated variable g is chosen as a power of two 2^−μin order to simplify the multiplication. This means that a simple shift register can be used for the second multiplier 101.

[0081] A further simplification can be achieved by merely using the sign for the real part Δa_iand the imaginary part Δb_iof an error signal vector (this also applies to the simplified algorithm according to the formulae (2b)). The first multiplication 100 is thus reduced to a single-bit operation.

[0082] The output signal of the second multiplier 101 is fed to the inverting input of a comparator 103, whose output is fed back to the non-inverting input via a delay element 104.

[0083] FIG. 3 shows the signal-to-noise ratio (SNR) for various methods for the compensation of interference at the input of each decision circuit 40, . . . , 4n. Without a time domain equalizer and interference suppression, an SNR of −40 to −20 dB over a frequency range up to approximately 1.1 MHz is achieved. With the invention's method for the compensation of interference (=interference suppressor), an SNR of −70 to approximately −45 dB is achieved, which corresponds to an improvement by on average 25 to 30 dB. An SNR of −70 to approximately −50 dB is achieved with a time domain equalizer which has 32 coefficients and is connected upstream of the demodulator 2.

[0084] FIG. 4 shows a second exemplary embodiment of the circuit configuration for the compensation of interference in a signal generated by discrete multitone modulation. In this case, all elements which are identical to the elements of the first exemplary embodiment are also provided with the same reference symbols.

[0085] Only the differences between the first and second exemplary embodiments are described below.

[0086] The error signal vector Δa₀, Δb₀of the reference signal vector is fed to an apparatus 200, which adapts the error signal vector to the channels to be corrected.

[0087] To that end, firstly parameters for the error frequency response are calculated from the error signal vector and are then used to correct the other channels.

[0088] If the circuit configuration is considered as a 2^ndorder system, it is possible to calculate the frequency response of the interference or of the error per channel downstream of the frequency response equalizers using the following equation: ${\mathrm{Error}}_u=\left(c_1+c_2·z_n\right)·\frac{{\mathrm{FEQ}}_n}{{\mathrm{FEQ\_mod}}_n}$

[0089] n channel index

[0090] Error_nError of the n^thchannel

[0091] z_nz_n=e^jn·^Ta with T_aas sampling time (for example 2.208 MHz in the case of ADSL)

[0092] FEQ_ncoefficients of the frequency domain equalizer of the n^thchannel

[0093] FEQ_mod_ncoefficients of a modified frequency domain equalizer of the n^thchannel, FEQ_nbeing transformed into the frequency domain by means of inverse Fourier transformation-and, at the same time, that part of the impulse response which lies within the cyclic prefix being “clipped”.

[0094] The parameters c₁and c₂can be calculated from the reference channel—for example the 0^thchannel—using the above equation: ${\mathrm{Error}}_0=\left(c_1+c_2·z_0\right)·\frac{{\mathrm{FEQ}}_0}{{\mathrm{FEQ\_mod}}_0}$

[0095] Since this equation is complex, two equations—a real equation and an imaginary equation—are produced for the calculation of the two unknown parameters c₁and c₂. As a result, the error frequency response can be analytically calculated for each further channel and used to correct the respective channel. It is advantageous that this method does not necessitate adaptation of coefficients during a transmission. The parameters c1 and c2 and thus the error frequency responses of the further channels only have to be calculated once from the reference channel. As a result, on account of the adaptation time saved, convergence problems cannot occur either.

[0096] After the calculation of the parameters c₁and c₂and of the error frequency response of each channel, the error signal vector is modified in the apparatus 200 either with 1/ FEQ₋mod, if correction is effected upstream of the frequency domain equalizers, or with FEQ/FEQ₋mod, if correction is effected downstream of the frequency domain equalizers.

[0097] The error signal vector that has been adapted in this way is subsequently added, for the purpose of interference compensation, to the n^thchannel by means of the adder circuits 201 and 202.