CDMA receiver with antenna array adaptively controlled with combined errors of despread multipath components

[0002] 1. Field of the Invention

[0003] The present invention relates generally to spread spectrum communication systems and more specifically to a code division multiple access (CDMA) communication receiver having an array of antennas whose directivity pattern is adaptively controlled.

[0004] 2. Description of the Related Art

[0005] For CDMA communication receivers, it is known to use an adaptive array of antennas for receiving user signals. Each of the received user signals is separated into multipath components, which are supplied respectively to adaptive processing units so that each unit receives a set of multipath components of same arrival time. In each processing unit, the input signals are respectively multiplied with weight coefficients and summed together to produce a weighted sum signal. This signal is despread with a chip sequence and demodulated. The demodulated signals from the processing units are combined in an adder and a threshold decision is performed on the output of the adder to produce a symbol output. Each processing unit detects a decision error of the symbol output and produces the weight coefficient by detecting correlations between the set of multipath components and the decision error.

[0006] However, since the adaptive processing units are provided in number corresponding to the number of multipath components, and each unit performs weighting and summing operations and updating the weight coefficients, implementation of the prior art system suffers from hardware complexity. Additionally, difficulty is encountered for the prior art antenna array to create a distinct directivity pattern when the signals received by the antennas contain numerous multipath components, particularly when they contain weak components, due to decreased reliability of the decision errors.

[0007] It is therefore an object of the present invention to provide a code division multiple access communication receiver having an adaptive array of antennas which can be implemented with reduced hardware and which is capable of adaptively controlling the antenna pattern even when the received signal contains numerous multipath components.

[0008] According to a first aspect of the present invention, there is provided a code division multiple access communication receiver comprising a plurality of antennas spaced a correlation distance apart from each other, and multiply-and-add circuitry for respectively weighting signals from the antennas with weight coefficients and summing the weighted signals to produce a weighted sum signal. Separation circuitry separates the weighted sum signal into multipath components which respectively correspond to propagation paths of a signal transmitted from a user station. A plurality of despreaders are provided for respectively despreading the separated multipath components with a chip sequence assigned to the user station to produce a plurality of despread signals at symbol intervals. Error detection circuitry detects a plurality of errors between a symbol output and the despread signals and combines the errors to produce a combined error signal. Weight control circuitry produces the weight coefficients from the signals detected by the antennas and updates the weight coefficients according to the combined error signal.

[0009] Preferably, the receiver includes a plurality of demodulators for estimating channel responses of the propagation paths from the despread signals and multiplying the despread signals by the estimated channel responses to produce a plurality of demodulated signals. The demodulated signals are summed and threshold decision is made on the sum of the demodulated signals to produce a decision output. The error detection circuitry is arranged to multiply the decision output by the estimated channel responses to produce a plurality of multiplied decision outputs, and detect a plurality of differences between the multiplied decision outputs and the despread signals to produce the errors.

[0010] According to a second aspect, the present invention provides a code division multiple access communication receiver comprising a plurality of antennas spaced a correlation distance apart from each other, and a plurality of despreaders for respectively despreading signals detected by the antennas with a chip sequence assigned to a user station to produce a plurality of despread signals at chip intervals. Multiply-and-add circuitry is connected to the despreaders for respectively weighting the despread signals by weight coefficients, separating each of the weighted despread signals into a plurality of multipath components which respectively correspond to propagation paths of a signal transmitted from the user station and summing the seperated multipath components to produce a plurality of weighted sum signals each representative of the sum of the multipath components of same arrival time. Error detection circuitry detects a plurality of errors between a symbol output and the weighted sum signals, and combining the errors to produce a combined error signal, and weight control circuitry produces the weight coefficients from the despread signals and updates the weight coefficients according to the combined error signal.

[0011] Preferably, a plurality of demodulators are provided for estimating channel responses of the propagation paths from the weighted sum signals and respectively multiplying the weighted sum signals by the estimated channel responses to produce a plurality of demodulated signals. The demodulated signals are summed and a threshold decision is made on the sum of the demodulated signals to produce a decision output. The error detection circuitry is arranged to multiply the decision output by the estimated channel responses to produce a plurality of multiplied decision outputs, and detect a plurality of differences between the multiplied decision outputs and the despread signals to produce the errors.

[0012] The present invention will be described in further detail with reference to the accompanying drawings, in which:

[0013] FIG. 1 is a block diagram of an adaptive array CDMA receiver according to a first embodiment of the present invention;

[0014] FIG. 2 is a block diagram of an adaptive array CDMA receiver according to a second embodiment of the present invention; and

[0015] FIG. 3 is a block diagram of the multiply-and-add circuit of the second embodiment.

[0016] Referring now to FIG. 1, there is shown an adaptive array CDMA receiver of a cell-site station for receiving spread spectrum signals from a particular user. The CDMA receiver includes an array of antennas 1₁to 1_Nspaced such a distance apart that their output signals are correlated with each other. Such a distance is called “correlation distance”. Although not shown in FIG. 1, the outputs of the antennas are converted from radio frequency to an intermediate or baseband frequency. The signals from antennas 1₁through 1_Nare supplied to a multiply-and-add circuit 2 where they are respectively multiplied in complex multipliers 21₁to 21_Nby weight coefficients W₁-W_Nsupplied from a weight control circuit 4 and summed by an adder 22. As a result, the weighted sum signal appears as if it were received by an antenna having a directivity pattern uniquely determined for a signal which has been transmitted from that particular user and propagated over different multipath fading channels, and successively arrived at the antennas as multipath components of the transmitted signal.

[0017] To detect individual multipath components contained in the weighted sum signal, the output of the adder 22 is supplied to a separation circuit 5 where the multipath components S₁to S_Mare separated from each other and distributed to despreaders 6₁to 6_M. A chip sequence c_k, which is uniquely assigned to that particular user “k”, is supplied to the despreaders 6₁to 6_Mfor despreading the multipath component signals to produce convolutionally integrated output signals at symbol intervals.

[0018] The outputs of the despreaders 6₁to 6_Mare respectively coupled to demodulators 7₁to 7_Mof identical construction. Each demodulator comprises a channel response estimator 71 for estimating the phase and amplitude of the carrier of the corresponding multipath component as a channel impulse response by using a periodically transmitted known training sequence. The estimated channel response is an indication of the fading characteristic of the propagation path of the multipath component. A complex conjugate circuit 72 is provided for producing a complex conjugate of the estimated channel response, which is used by a complex multiplier 73 to multiply the output signal of the corresponding despreader, so that the output of the multiplier 73 is synchronized to the phase of the transmitted carrier. The output of the multiplier 73 of each demodulator 7_m(where i=1, 2, . . . , M) represents the demodulated signal of an m-th multipath fading channel and the output of the channel response estimator 71 represents the impulse response of the m-th multipath fading channel.

[0019] The demodulated signals of the “m” fading channels are maximum-ratio combined in an adder 8 and a threshold decision circuit 9 makes a hard-decision on the sum signal to produce a decision output as a replica of the symbol transmitted from the particular user.

[0020] An error detection circuit 10 is provided, which includes a plurality of multipliers 11₁to 11_Mwhere the decision symbol is multiplied by the channel responses respectively estimated by the demodulators 7₁to 7_M. For the respective multipath fading channels, subtractors 12₁to 12_Mare connected to the multipliers 11₁to 11_Mand the despreaders 6₁to 6_Mto calculate errors between the outputs of the corresponding multipliers 11 and the outputs of the corresponding despreaders 6, each representing the decision error of the m-th fading channel. These decision errors are respectively multiplied (spread) in complex multipliers 13₁to 13_Mwith the user's chip sequence, so that the decision errors have the same length as the chip sequence. The outputs of multipliers 13₁to 13_Mare stored in respective locations of a latch 14 as they occur and retrieved simultaneously when all the locations are filled with necessary data, so that the outputs of all multipliers 13 are time-coincident with each other at the outputs of the latch 14. The outputs of the latch 14 are summed in an adder 15 to produce an output representing a combined decision error of the decision circuit 9.

[0021] The decision error from the adder 15 is applied to the weight control circuit 4 where it is used to update the weight coefficients W₁to W_Nat chip intervals according to the MMSE (minimum mean square error) algorithm that minimizes the decision error by solving the following equation:

[0022] W(i+1)=W(i)+μ·r(i−D)e*(i)  (1)

[0023] Specifically, a complex conjugate of the decision error e*(i) is scaled by a stepsize μ and the output signals of the antennas 1₁to 1_Nare delayed in a delay unit 3 by delay time D, producing a vector of delayed signals r(i−D), and correlations W(i) are taken between the elements of the vector and the scaled decision error μ·e*(i), where D represents the total time taken to derive a decision error from a set of antenna signals and “i” represents a chip interval. Since the decision error is obtained at symbol intervals, the correlation values are integrated over the symbol time interval, producing a vector of weight coefficients W(i+1), which are applied respectively to the complex multipliers 21 as updated coefficients W₁to W_N. The stepsize μ is determined so that the speed of convergence, the precision of convergence and the stability of the receiver are appropriately compromised. Optimum values of weight coefficients W₁to W_Nare obtained in this way.

[0024] For a full understanding of the present invention, the operation of the CDMA receiver of this invention is mathematically analyzed as follows.

[0025] For a particular user “k”, the output signal y(i) of the multiply-and-add circuit 2 during a chip interval “i” is given by:

[0026] y_k(i)=r(i)^TW_k*(i)  (2)

[0027] where r(i)^Tis a transpose of the vector r(i) of the received signals.

[0028] Each of the despreaders 6₂to 6_Mis implemented with a tapped-delay line filter (or transversal filter) which produces an output signal z_k,m(j) for a transmitted symbol “j” by solving the following equation at symbol intervals: $\begin{array}{cc}{z}_{k,m}\left(j\right)=\frac{1}{L}\sum _{l=0}^{L-1}{y}_k\left(l+D_m\right)c_k\left(l\right)& \left(3\right)\end{array}$

[0029] where L is the length of the chip sequence c_k, and m=1, 2, . . . , M, and D_mis the delay time of multipath component signal S_mtransmitted on the m-th propagation path with respect to the arrival time of the signal S₁of the first propagation path. Equation (3) indicates that each despreader determines the correlation between the output signal y_k(i) and the chip sequence c_kand performs convolution integral of the correlation value over a symbol interval and divides the integral by the symbol interval represented by the integer L.

[0030] If the transmitted signal is a BPSK (bi-phase shift keying) signal and the channel response estimated for the symbol “j” on the multipath fading channel “m” by each demodulator 7_m(m=1, 2 . . . , M) is expressed as ξ_k,m(j), then the output of the multiplier 73 of each demodulator 7_mproduces an output signal z_k,m(j)ξ*_k,m(j). As a result, phase variation that occurs on each of the multipath fading channels (propagation paths) is compensated for by the multiplier 73 of each demodulator 7.

[0031] Decision circuit 9 performs a hard decision on the sum of the phase variation compensated signals and produces a decision output {circumflex over (d)}_k(j) as follows: $\begin{array}{cc}{\hat{d}}_k\left(j\right)=\mathrm{Sgn}\left[\sum _{m=1}^M{z}_{k,m}\left(j\right){\hat{\xi }}_{k,m}^{*}\left(j\right)\right]& \left(4\right)\end{array}$

[0032] where Sgn (x) is a signum function which is 1 if x>0, 0 for x=0, −1 for x<0. The hard decision symbol output is multiplied in the multipliers 11₁to 11_Mby the estimated channel responses ξ_k,1(j) to ξ_k,M(j), respectively, to produce output signals {circumflex over (d)}_k(j)ξ*_k,m(j) from which the output signals z_k,m(j) of the despreaders 6₁to 6_Mare subtracted in the subtractors 12₁to 12_M. The outputs of the subtractors 12 are multiplied with the chip sequence c_k(i) in the complex multipliers 13 so that their output signals are given by:

[0033] E_k,m(i)={{circumflex over (d)}_k(j)ξ*_k,m(j)−z_k,m(j)}c_k(i)  (4)

[0034] The purpose of the multiplication by the multipliers 11 of the error detector is to cancel the effects of the phase variation compensation by the multipliers 73 of the demodulators. Therefore, the phase variation components of the decision symbol are removed from the output signals E_k,m(i) of the complex multipliers 13₁to 13_M.

[0035] Alternatively, if the estimated value |ξ_k,m(j) of each multipath fading channel is known in advance, the following equation can be used instead of Equation (4): $\begin{array}{cc}{E}_{k,m}\left(i\right)=\left\{{\hat{d}}_k\left(j\right)\left|{\hat{\xi }}_{k.m}^{*}\left(j\right)\right|\frac{{\hat{\xi }}_{k,m}^{*}\left(j\right)}{\left|{\hat{\xi }}_{k,m}^{*}\left(j\right)\right|}-z_{k,m}\left(j\right)\right\}{c}_k\left(i\right)& \left(5\right)\end{array}$

[0036] With the outputs of the multipliers 13 being time-aligned by the latch 14, the error detector 10 produces the following decision error: $\begin{array}{cc}{e}_k\left(i\right)=\sum _{m=1}^M{E}_{k,m}\left\{i-\left(D_M-D_m\right)\right\}& \left(6\right)\end{array}$

[0037] where DM represents the delay time of the signal S_Mof the M-th propagation path. As a result, the weight coefficients of the multiply-and-add circuit 2 are optimized uniquely to the multipath signal components of the user “k”, so that the antenna gain of the array is strengthened in the arriving direction of the desired signal and weakened in the arriving directions of undesired signals. If the decision output is known in advance, a known symbol value can be used instead of the decision output d_k(j).

[0038] It is seen that the present invention requires, for each user, only one multiply-and-add circuit and one weight control circuit. This contributes to significant hardware reduction. Additionally, since the combined decision error of the weight control circuit is derived from errors of the individual multipath components, the antenna array can be controlled with precision and high convergence speed even though numerous multipath components are contained in received signals.

[0039] FIG. 2 is a block diagram of a modified embodiment of the present invention, in which parts corresponding in significance to those of FIG. 1 are marked with the same reference numerals as those used in FIG. 1. In FIG. 2, despreaders 60₁to 60_Nare connected to the antennas 1₁to 1_N, respectively. Each despreader is implemented with a tapped-delay line filter for calculating correlation between the signal from the corresponding antenna and the user's chip sequence c_kat chip intervals, rather than at symbol intervals, so that correlations between multipath components of the signal is detected by the corresponding antenna and the chip sequence is determined by each despreader. These multipath components are delivered from each despreader in sequence to a corresponding input terminal of a multiply-and-add circuit 20. Delay circuit 3 is connected to the outputs of the despreaders 60₁to 60_M. Weight control circuit 4 produces weight coefficients W1 to W_Nfrom the delayed outputs of the despreaders 60 and updates the coefficients according to the output of the error detection circuit 10A.

[0040] As shown in FIG. 3, the multiply-and-add circuit 20 includes multipliers 23₁to 23_Nconnected to the outputs of despreaders 60₁to 60_N, respectively, for multiplying their outputs with weight coefficients W₁to W_N. The outputs of multipliers 23₁to 23_Nare sequentially delivered to separation circuits 24₁through 24_N, respectively, where the multipath components of each of the weighted signals are separated and distributed to adders 25₁to 25_Mso that the adder 25₁receives a set of earliest signals S₁₁, S₂₁, . . . , S_N1from the first outputs of the distribution circuits, the adder 25₂receives a set of second signals S₁₂, S₂₂, . . . , S_N2from the second outputs, and the adder 25_Mreceives a set of last signals S_1M, S_2M, . . . , S_NMfrom the M-th outputs of the distribution circuits.

[0041] Adders 25₁to 25_Mcombine their input signals to produce sum signals which are respectively supplied to demodulators 70₁to 70_M.

[0042] The error detection circuit is indicated by numeral 10A. This circuit differs from the error detection circuit 10 of the previous embodiment by excluding the multipliers 13₁to 13_Mand having the subtractors 12₁to 12_Msubtract the outputs of the multiply-and-add circuit 20 from the outputs of multipliers 11₁to 11_M, respectively, and utilizing the outputs of subtractors 12₁to 12_Mas inputs of the latch 14.

[0043] Since the decision error of the error detection circuit 10A is detected without using the chip sequence, the adaptation of the array is performed at symbol intervals, which is advantageous for hardware reduction in comparison with the previous embodiment.