US 6,609,977 B1Grant
External interfaces for a 3D graphics system
Issue Date:2003-08-26
•57 Claims
•53 Drawing Sheets
Abstract
An advantageous set of external interfaces for home video game platform provide modularity and expandability while maintaining and preserving the proprietary nature of the platform. A disk drive interface provides flexible communications with an internal disk drive. Various serial bus interfaces provide expandability and interconnectability with a variety of internal and external devices including, for example, flash memory, broadband adapters, modems, and various other devices. A 4-port game controller interface provides serial interconnectability with handheld game controllers and various other input/output device. Power supply, digital and analog audio/video connections, and parallel memory expansion connections are also provided.
Metadata
Assignee
- Nintendo Co., Ltd.
Inventors
- Dan Shimizu
- Genyo Takeda
- Ko Shiota
- Munehito Oira
- Kazuo Koshima
- Satoshi Nishiumi
Application Information
Application Number:US 09/723,335
Filing Date:2000-11-28
Priority Date:2000-08-23
Art Unit:7
Classifications
IPC:
A63F 1302G06F 1340
Field of Search:
273148 B341 20345156345700345701463 1463 36463 39463 37463 38710 8710 12710 62710 72710 73710 74
Patent Drawings (53 sheets)
Description
RELATED APPLICATIONS
[0002] This application claims priority under 35 U.S.C. 119 to provisional application Ser. No. 60/226,884, filed Aug. 23, 2000.
[0003] This application is related to the following applications identified below, each of which is incorporated herein by reference:
[0004] U.S. patent application Ser. No. 09/722,664 filed Nov. 28, 2000 of Shimizu et al., entitled “Controller Interface for A Graphics System” which claims priority from provisional application Ser. No. 60/226,885 filed Aug. 23, 2000; and
[0005] Design application Ser. No. 29/128,262 filed Jul. 31, 2000 of Ashida entitled “Video Game Machine.”
FIELD OF THE INVENTION
[0006] The present invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Still more particularly, this invention relates to external system interfaces used to connect a graphics system to audio, video, mass media storage device, other storage device, communications, printing and other electronic devices.
BACKGROUND AND SUMMARY OF THE INVENTION
[0007] Many of us have seen films containing remarkably realistic dinosaurs, aliens, animated toys and other fanciful creatures. Such animations are made possible by computer graphics. Using such techniques, a computer graphics artist can specify how each object should look and how it should change in appearance over time, and a computer then models the objects and displays them on a display such as your television or a computer screen. The computer takes care of performing the many tasks required to make sure that each part of the displayed image is colored and shaped just right based on the position and orientation of each object in a scene, the direction in which light seems to strike each object, the surface texture of each object, and other factors.
[0008] Because computer graphics generation is complex, computer-generated three-dimensional graphics just a few years ago were mostly limited to expensive specialized flight simulators, high-end graphics workstations and supercomputers. The public saw some of the images generated by these computer systems in movies and expensive television advertisements, but most of us couldn't actually interact with the computers doing the graphics generation. All this has changed with the availability of relatively inexpensive 3D graphics platforms such as, for example, the Nintendo 64® and various 3D graphics cards now available for personal computers. It is now possible to interact with exciting 3D animations and simulations on relatively inexpensive computer graphics systems in your home or office.
[0009] A problem graphics system designers confronted in the past was how to efficiently couple system components together. A moderm 3D graphics system is relatively complex, and requires a number of different connections between different aspects of the system. For example, it is often necessary to interface with a mass storage device such as an optical disk. In addition, in an interactive real time system such as a gaming platform, some means must be provided to interface with user-manipulable controls such as hand-held controllers or the like. Sound is typically required, so that interfaces with various sound-producing and sound-supporting components are required. It is also necessary to provide some interfacing means for interfacing the system with a display device of an appropriate configuration. Additionally, it is often desirable to interface the system with a number of other components such as, for example, read only memory, flash memory, various memory cards, modems or other network connections, and debugging facilities for game or other application development. Various solutions to this problem were offered.
[0010] One approach would be to use standardized interfaces. Computer equipment manufacturers have developed a number of standardized interfaces in the past to connect with mass storage devices, modems, and other peripheral devices. Using standardized interfaces tends to simplify design efforts and achieve component compatibility and interoperability. The typical personal computer has a number of standardized interfaces so it can be modular and compatible with hardware and peripherals designed by a number of different manufacturers. Designing a new personal computer does not require redesign of all of these interfaces.
[0011] While the standardized interface approach has certain advantages in the arena of general purpose computing, it may not be suitable for home video game platforms. Because a home video game system must be manufactured at low cost and yet achieve maximum performance, it is desirable to optimize each and every aspect of the system—including the system interfaces. The interfaces can be looked at as the highways over which information flows throughout the system. This information traffic should flow as rapidly and efficiently as possible. Using standard interfaces may be easier from a design standpoint, but a standardized interface may not provide the high performance that a customized interface might offer. “One size fits all” makes things easier, but doesn't always result in the best possible fit.
[0012] Another issue relates to hardware interoperability. Standardized interfaces provide the advantage that no one owns them, and everyone can design components that are compatible with them. For example, when you buy a personal computer having a standardized serial interface, parallel interface and expansion device interface, you know that you can go out and purchase any of a variety of different devices all of which will be compatible with those standardized interfaces. You can plug in any of a dozen different types of printers to either the serial or the parallel interface of your personal computer, and they will all work. Similarly, any of dozens of different modems or other network cards can be plugged into the PCMCIA card slot of a personal computer or laptop, and all of these different cards will work.
[0013] Open standards have the advantage that they achieve hardware interoperability between systems and a wide range of different accessories. This approach is helpful when the system manufacturer is selling a general purpose device that can be used for virtually any application, but makes less sense in the home video game arena where a given video game manufacturer is responsible for making or licensing all of the various special-purpose accessories for its brand of home video game platform.
[0014] For example, video game manufacturers in the past have expended substantial time, effort and resources to develop definitive new home video game platforms. They want to sell as many of these as possible, and therefore price them very competitively. Like the razor manufacturer who recoups his investment by selling razor blades as opposed to the razor itself, video game platform manufacturers rely on controlling access to the installed user base of home video game systems to achieve profits through licensing. If the home video game platform used open standards, then competing manufacturing could bypass the company that invested all the time, effort and resources to develop the platform to begin with, and could instead market directly to consumers. Accordingly, under this business model, it is important for the platform manufacturer to be able to control access to the platform.
[0015] One technique used successfully in the past to control access to home video game platforms was to incorporate security systems that control access to the platform. A security system can enable the platform to accept or reject things plugged into it. As one example, it is possible to include an integrated circuit chip authentication type device in home video game cartridges. Before the home video game platform interoperates with the cartridge or other accessory, it may first authenticate the cartridge or other accessory by use of the security chip. While this approach can be highly successful, it requires each accessory to include authentication type information and/or devices. This increases cost. In addition, no security system is impenetrable. Given enough time, effort and resources, any security system can be “cracked” to unlock access to the platform. Thus, further improvements are desirable.
[0016] The present invention provides an approach to solving these problems. It provides a variety of proprietary system interfaces that have been optimized to maximize system performance. Because these optimized system interfaces are non-standard and unusual, they provide uniqueness that can be used as a basis for excluding unlicensed and unauthorized people from manufacturing components that are compatible with the interfaces. This allows a home video game platform developer to protect its substantial investment in the development of the platform.
[0017] One aspect of the present invention provides a proprietary disk interface for mass storage devices such as optical disks. The disk interface can be used to interface with an optical disk drive using direct memory access with interrupt. The disk interface acts as a transport for command packets sent between a disk drive and a graphics and audio coprocessor. The interface need not interpret the packets. The disk interface provides a number of signal lines including a parallel data bus and various additional signaling lines to provide high speed data transfer and efficiently coordinate operations between the disk drive and the rest of the system.
[0018] Another aspect provided by this invention is a serial interface for interfacing an audio and graphics coprocessor with a variety of different types of accessory devices including but not limited to hand-held game controllers. The serial interface provides a single bit serial interface using a state-based interface protocol. The interface supports four separate serial interfaces to four hand-held controllers or associated devices. Each interface can be accessed in parallel. In a controller mode, the last state of the controller is stored in a double-buffered register to support simple main processor reads for determining state. The example embodiment automatically polls controller state using hardware circuitry with configurable polling periods. A bulk mode supports changeable data size. A pair of light gun signals can be used to control separate horizontal/vertical counters to support flash and shutter light guns. An LCD shutter can be supported through automatic polling and a serial control command. The system interface includes automatic control of presence detect to save effort on the part of the main processor.
[0019] In accordance with another aspect of this invention, an external accessory device interface(s) is provided for interfacing with a variety of different types of external devices such as, for example, read only memory, flash memory, memory cards, modems, debugging systems or a variety of other devices. The external interface provided in accordance with this invention can be used, for example, to interface with a single chip boot ROM and associated real time clock, as well as to on-board flash memory, an external modem, an external memory card, debugger hardware, or other external devices including but not limited to a voice recognition device. A preferred external interface provides four separate external interface channels. A channel 0 supports both expansion and on-board devices. The entire ROM is memory mapped onto the external interface, and ROM reads can be controlled entirely by hardware for boot support. Separate external interface chip selects can be used to control many different devices (e.g., ROM/RTC, flash memory, expansion modem, expansion backup memory card, debug, etc.). Maskable external interrupts can also be provided—one for each external expansion port. Maskable interrupts may provide transfer complete signaling for each channel. A pair of maskable interrupts can be provided for hot-plug status to detect insertion and removal of external devices. Direct memory access can be used to support general transfers on each channel.
[0020] In accordance with yet another aspect provided by this invention, an audio interface provides support for audio functions within a graphics system. The audio/video interface can provide support for an external digital-to-analog converter providing, for example, composite video and 16-bit stereo sound running at a desired sampling rate (e.g., fixed 48 kHz). The interface may also provide an interface for a digital audio and video output and/or input. The collection of audio interfaces may also include a mass storage device streaming audio input interface via, for example, a 16-bit serial bit interface running at a predetermined sampling rate (e.g., 32 kHz or 48 kHz). The sample rate conversion of mass storage device streaming audio can be provided “on the fly.” The collection of audio interfaces may also include an audio mixer interface for mixing two audio streams into a final output stream. The audio mixer interface can provide audio volume control, for example, for mixing the mass storage device streaming audio output with audio generated using an internal digital signal processor.
[0021] In accordance with yet another aspect of this invention, a video interface provides efficient interfacing between a graphics processor and an external video encoder. The video interface does much of the work required so as to reduce the amount of work the external encoder needs to perform. The video interface also provides a number of interesting additional features such as panning, windowing, light gun support, and color format conversion.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] These and other features and advantages provided by the invention will be better and more completely understood by referring to the following detailed description of presently preferred embodiments in conjunction with the drawings, of which:
[0023] FIG. 1 is an overall view of an example interactive computer graphics system;
[0024] FIG. 2 is a block diagram of the FIG. 1 example computer graphics system;
[0025] FIG. 3 is a block diagram of the example graphics and audio processor shown in FIG. 2;
[0026] FIG. 4 is a block diagram of the example 3D graphics processor shown in FIG. 3;
[0027] FIG. 5 is an example logical flow diagram of the FIG. 4 graphics and audio processor;
[0028] FIG. 6 is a block diagram of an example input/output subsystem;
[0029] FIGS. 7A and 7B show an example disk interface;
[0030] FIG. 7C shows an example disk interface register interface;
[0031] FIGS. 8A and 8B show an example serial interface;
[0032] FIG. 8C shows example serial interface registers;
[0033] FIG. 8D is an even more detailed overall view of an example serial interface showing the details of serial interface communication circuitry and registers;
[0034] FIGS. 9A-9D show example external interfaces;
[0035] FIG. 9E shows example external interface registers;
[0036] FIGS. 10A and 10B show example audio interfaces;
[0037] FIG. 10C shows example audio interface registers;
[0038] FIGS. 11A-11H show various timing diagrams and elements of an example video controller;
[0039] FIG. 12 is a block diagram of an example overall more detailed embodiment of an example video game system;
[0040] FIGS. 12A-12G show a detailed example connection diagram;
[0041] FIGS. 13A and 13B show an example serial connection;
[0042] FIG. 14 shows example controller port connections;
[0043] FIGS. 15A-15C show example external interface connections;
[0044] FIG. 16 shows an example modem connection;
[0045] FIGS. 17A and 17B show example external digital video/audio connections;
[0046] FIG. 18 shows an example analog audio/video connection;
[0047] FIGS. 19A and 19B show an example SDRAM expansion connection;
[0048] FIGS. 20A and 20B show an example disk drive connection;
[0049] FIG. 21 shows an example power supply connection;
[0050] FIGS. 22-28B22 through 27, 28A and 28B show external views of an example video game system showing example external connector configurations; and
[0051] FIGS. 29A and 29B example alternative compatible implementations.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE INVENTION
[0052] FIG. 1 shows an example interactive 3D computer graphics system 50. System 50 can be used to play interactive 3D video games with interesting stereo sound. It can also be used for a variety of other applications.
[0053] In this example, system 50 is capable of processing, interactively in real time, a digital representation or model of a three-dimensional world. System 50 can display some or all of the world from any arbitrary viewpoint. For example, system 50 can interactively change the viewpoint in response to real time inputs from handheld controllers 52a,52bor other input devices. This allows the game player to see the world through the eyes of someone within or outside of the world. System 50 can be used for applications that do not require real time 3D interactive display (e.g., 2D display generation and/or non-interactive display), but the capability of displaying quality 3D images very quickly can be used to create very realistic and exciting game play or other graphical interactions.
[0054] To play a video game or other application using system 50, the user first connects a main unit 54 to his or her color television set 56 or other display device by connecting a cable 58 between the two. Main unit 54 produces both video signals and audio signals for controlling color television set 56. The video signals are what control the images displayed on the television screen 59, and the audio signals are played back as sound through television stereo loudspeakers 61L, 61R.
[0055] The user also needs to connect main unit 54 to a power source. This power source may be a conventional AC adapter (not shown) that plugs into a standard home electrical wall socket and converts the house current into a lower DC voltage signal suitable for powering the main unit 54. Batteries could be used in other implementations.
[0056] The user may use hand controllers 52a,52bto control main unit 54. Controls 60 (60a,60b) can be used, for example, to specify the direction (up or down, left or right, closer or further away) that a character displayed on television 56 should move within a 3D world. Controls 60 also provide input for other applications (e.g., menu selection, pointer/cursor control, etc.). Controllers 52 can take a variety of forms. In this example, controllers 52 shown each include controls 60 such as joysticks, push buttons and/or directional switches. Controllers 52 may be connected to main unit 54 by cables or wirelessly via electromagnetic (e.g., radio or infrared) waves.
[0057] To play an application such as a game, the user selects an appropriate storage medium 62 storing the video game or other application he or she wants to play, and inserts that storage medium into a slot 64 in main unit 54. Storage medium 62 may, for example, be a specially encoded and/or encrypted optical and/or magnetic disk. The user may operate a power switch 66 to turn on main unit 54 and cause the main unit to begin running the video game or other application based on the software stored in the storage medium 62. The user may operate controllers 52 to provide inputs to main unit 54. For example, operating a control 60 may cause the game or other application to start. Moving other controls 60 can cause animated characters to move in different directions or change the user's point of view in a 3D world. Depending upon the particular software stored within the storage medium 62, the various controls 60 on the controller 52 can perform different functions at different times.
Example Electronics of Overall System
[0058] FIG. 2 shows a block diagram of example components of system 50. The primary components include:
[0059] a main processor (CPU) 110,
[0060] a main memory 112, and
[0061] a graphics and audio processor 114.
[0062] In this example, main processor 110 (e.g., an enhanced IBM Power PC 750) receives inputs from handheld controllers 52 (and/or other input devices) via graphics and audio processor 114. Main processor 110 interactively responds to user inputs, and executes a video game or other program supplied for example, by external storage media 62 via a mass storage access device 106 such as an optical disk drive. As one example, in the context of video game play, main processor 110 can perform collision detection and animation processing in addition to a variety of interactive and control functions.
[0063] In this example, main processor 110 generates 3D graphics and audio commands and sends them to graphics and audio processor 114. The graphics and audio processor 114 processes these commands to generate interesting visual images on display 59 and interesting stereo sound on stereo loudspeakers 61R, 61L or other suitable sound-generating devices.
[0064] Example system 50 includes a video encoder 120 that receives image signals from graphics and audio processor 114 and converts the image signals into analog and/or digital video signals suitable for display on a standard display device such as a computer monitor or home color television set 56. System 100 also includes an audio codec (compressor/decompressor) 122 that compresses and decompresses digitized audio signals and may also convert between digital and analog audio signaling formats as needed. Audio codec 122 can receive audio inputs via a buffer 124 and provide them to graphics and audio processor 114 for processing (e.g., mixing with other audio signals the processor generates and/or receives via a streaming audio output of mass storage access device 106). Graphics and audio processor 114 in this example can store audio related information in an audio memory 126 that is available for audio tasks. Graphics and audio processor 114 provides the resulting audio output signals to audio codec 122 for decompression and conversion to analog signals (e.g., via buffer amplifiers 128L, 128R) so they can be reproduced by loudspeakers 61L, 61R.
[0065] Graphics and audio processor 114 has the ability to communicate with various additional devices that may be present within system 100. For example, a parallel digital bus 130 may be used to communicate with mass storage access device 106 and/or other components. A serial peripheral bus 132 may communicate with a variety of peripheral or other devices including, for example:
[0066] a programmable read-only memory (PROM) and/or real time clock (RTC) 134,
[0067] a modem 136 or other networking interface (which may in turn connect system 100 to a telecommunications network 138 such as the Internet or other digital network from/to which program instructions and/or data can be downloaded or uploaded), and
[0068] a flash memory 140.
[0069] A further external serial bus 142 may be used to communicate with additional expansion memory 144 (e.g., a memory card) or other devices. Connectors may be used to connect various devices to busses 130, 132, 142.
Example Graphics and Audio Processor
[0070] FIG. 3 is a block diagram of an example graphics and audio processor 114. Graphics and audio processor 114 in one example may be a single-chip ASIC (application specific integrated circuit). In this example, graphics and audio processor 114 includes:
[0071] a processor interface 150,
[0072] a memory interface/controller 152,
[0073] a 3D graphics processor 154,
[0074] an audio digital signal processor (DSP) 156,
[0075] an audio memory interface 158,
[0076] an audio interface and mixer 1300,
[0077] a peripheral controller 162, and
[0078] a display controller 164.
[0079] 3D graphics processor 154 performs graphics processing tasks. Audio digital signal processor 156 performs audio processing tasks. Display controller 164 accesses image information from main memory 112 and provides it to video encoder 120 for display on display device 56. Audio interface and mixer 1300 interfaces with audio code 122, and can also mix audio from different sources (e.g., streaming audio from mass access storage device 106, the output of audio DSP 156, and external audio input received via audio codec 122). Processor interface 150 provides a data and control interface between main processor 110 and graphics and audio processor 114.
[0080] Memory interface 152 provides a data and control interface between graphics and audio processor 114 and memory 112. In this example, main processor 110 accesses main memory 112 via processor interface 150 and memory interface 152 that are part of graphics and audio processor 114. Peripheral controller 162 provides a data and control interface between graphics and audio processor 114 and the various peripherals mentioned above. Audio memory interface 158 provides an interface with audio memory 126.
Example Graphics Pipeline
[0081] FIG. 4 shows a more detailed view of an example 3D graphics processor 154. 3D graphics processor 154 includes, among other things, a command processor 200 and a 3D graphics pipeline 180. Main processor 110 communicates streams of data (e.g., graphics command streams and display lists) to command processor 200. Microprocessor 110 has a two-level cache 115 to minimize memory latency, and also has a write-gathering buffer 111 for uncached data streams targeted for the graphics and audio processor 114. The write-gathering buffer 111 collects partial cache lines into full cache lines and sends the data out to the graphics and audio processor 114 one cache line at a time for maximum bus usage.
[0082] Command processor 200 receives display commands from main processor 110 and parses them—obtaining any additional data necessary to process them from shared memory 112. The command processor 200 provides a stream of vertex commands to graphics pipeline 180 for 2D and/or 3D processing and rendering. Graphics pipeline 180 generates images based on these commands. The resulting image information may be transferred to main memory 112 for access by display controller/video interface unit 164—which displays the frame buffer output of pipeline 180 on display 56.
[0083] FIG. 5 is a logical flow diagram of graphics processor 154. Main processor 110 may store graphics command streams 210, display lists 212 and vertex arrays 214 in main memory 112, and pass pointers to command processor 200 via bus interface 150. The main processor 110 stores graphics commands in one or more graphics first-in-first-out (FIFO) buffers 210 it allocates in main memory 110. The command processor 200 fetches:
[0084] command streams from main memory 112 via an on-chip FIFO memory buffer 216 that receives and buffers the graphics commands for synchronization/flow control and load balancing,
[0085] display lists 212 from main memory 112 via an on-chip call FIFO memory buffer 218, and
[0086] vertex attributes from the command stream and/or from vertex arrays 214 in main memory 112 via a vertex cache 220.
[0087] Command processor 200 performs command processing operations 200athat convert attribute types to floating point format, and pass the resulting complete vertex polygon data to graphics pipeline 180 for rendering/rasterization. A programmable memory arbitration circuitry 130 (see FIG. 4) arbitrates access to shared main memory 112 between graphics pipeline 180, command processor 200 and display controller/video interface unit 164.
[0088] FIG. 4 shows that graphics pipeline 180 may include:
[0089] a transform unit 300,
[0090] a setup/rasterizer 400,
[0091] a texture unit 500,
[0092] a texture environment unit 600, and
[0093] a pixel engine 700.
[0094] Transform unit 300 performs a variety of 2D and 3D transform and other operations 300a(see FIG. 5). Transform unit 300 may include one or more matrix memories 300bfor storing matrices used in transformation processing 300a.Transform unit 300 transforms incoming geometry per vertex from object space to screen space; and transforms incoming texture coordinates and computes projective texture coordinates (300c). Transform unit 300 may also perform polygon clipping/culling 300d.Lighting processing 300ealso performed by transform unit 300bprovides per vertex lighting computations for up to eight independent lights in one example embodiment. Transform unit 300 can also perform texture coordinate generation (300c) for embossed type bump mapping effects, as well as polygon clipping/culling operations (300d).
[0095] Setup/rasterizer 400 includes a setup unit which receives vertex data from transform unit 300 and sends triangle setup information to one or more rasterizer units (400b) performing edge rasterization, texture coordinate rasterization and color rasterization.
[0096] Texture unit 500 (which may include an on-chip texture memory (TMEM) 502) performs various tasks related to texturing including for example:
[0097] retrieving textures 504 from main memory 112,
[0098] texture processing (500a) including, for example, multi-texture handling, post-cache texture decompression, texture filtering, embossing, shadows and lighting through the use of projective textures, and BLIT with alpha transparency and depth,
[0099] bump map processing for computing texture coordinate displacements for bump mapping, pseudo texture and texture tiling effects (500b), and
[0100] indirect texture processing (500c).
[0101] Texture unit 500 outputs filtered texture values to the texture environment unit 600 for texture environment processing (600a). Texture environment unit 600 blends polygon and texture color/alpha/depth, and can also perform texture fog processing (600b) to achieve inverse range based fog effects. Texture environment unit 600 can provide multiple stages to perform a variety of other interesting environment-related functions based for example on color/alpha modulation, embossing, detail texturing, texture swapping, clamping, and depth blending.
[0102] Pixel engine 700 performs depth (z) compare (700a) and pixel blending (700b). In this example, pixel engine 700 stores data into an embedded (on-chip) frame buffer memory 702. Graphics pipeline 180 may include one or more embedded DRAM memories 702 to store frame buffer and/or texture information locally. Z compares 700a′ can also be performed at an earlier stage in the graphics pipeline 180 depending on the rendering mode currently in effect (e.g., z compares can be performed earlier if alpha blending is not required). The pixel engine 700 includes a copy operation 700cthat periodically writes on-chip frame buffer 702 to memory portion 113 of main memory 112 for access by display/video interface unit 164. This copy operation 700ccan also be used to copy embedded frame buffer 702 contents to textures in the main memory 112 for dynamic texture synthesis effects. Anti-aliasing and other filtering can be performed during the copy-out operation. The frame buffer output of graphics pipeline 180 (which is ultimately stored in main memory 112) is read each frame by display/video interface unit 164. Display controller/video interface 164 provides digital RGB pixel values for display on display 56.
Example Input/Output Subsystem
[0103] FIG. 6 shows an example input/output subsystem. In this example, the input/output subsystem includes a serial interface 1000, an external interface 1100, a disk interface 1200 and an audio interface 1300. Serial interface 1000 is used to communicate with controllers 52 or other devices that can be coupled to one of four serial ports of system 50. External interface 1100 is used to communicate with a variety of devices such as PROM RTC 134, modem 136, flash memory 140, memory card 144, etc. via various SPI buses 132, 142. Disk interface 1200 is used to communicate with mass storage access device 106 via a parallel bus 130. Audio interface 1300 is used to stream the audio output data from an audio buffer in main memory 112 to audio codec 122.
[0104] In the example embodiment, the external interface 1100 and disk interface 1200 have direct access to memory controller 152 via a bus 900. Details of the operation of memory controller 152 may be found in application Ser. No. 09/726,220 filed Nov. 28, 2000 entitled “Graphics Processing System with Enhanced Memory Controller” and application Ser. No. 09/722,665 filed Nov. 28, 2000 entitled “Method and Apparatus for Accessing Shared Resources.” The contents of each of these applications are incorporated herein by reference. In addition, each one of interfaces 1000, 1100, 1200 and 1300 as well as audio digital signal processor 156 share a common bus 902 used to communicate between these components and a bus interface 904. The bus interface 904, in turn, can be used to arbitrate access to graphics unit 180 including embedded DRAM 702. In the example embodiment, there is also a connection 906 between DSP 156 and audio interface 1300.
[0105] Briefly, disk interface 1200 provides an interface to mass storage access device 106 providing a direct memory access capability with interrupt. Serial interface 1000 provides a serial interface to hand controllers 52 or other serial devices using automatic controller polling and bulk data mode including a light gun interface. The external interface 1100 provides multiple serial peripheral interface (SPI) buses as well as a memory mapped area for boot PROM 134. Audio interface 1300 provides an output to audio codec 122 as well as an input for streaming audio from mass storage access device 106. These various interfaces 1000, 1100, 1200, 1300 provide a shared memory port for direct memory access, with round robin arbitration for access to main memory.
Example Disk Interface
[0106] FIG. 7A shows the external interface of disk interface 1200. In the example embodiment, bus 130 to/from disk interface 1200 is connected directed to mass storage access device 106 (which in the example embodiment may comprise an optical disk drive). In the example embodiment, bus 130 is a parallel bus having a single device on it, with disk interface 1200 being the only master and the mass storage access device 106 being the only target device. Disk interface 1200 communicates with main processor 110 via a SPU interface 1202 and an interrupt line 1204, and communicates with memory controller 152 via memory controller interface 900.
[0107] FIG. 7B shows a more detailed block diagram of an example disk interface 1200. In this example, disk interface 1200 includes a CPU interface block 1206, a memory controller interface block 1208, and various buffers including a buffer 1210, a buffer 1212, a DMA FIFO 1214, a direct memory access controller 1216, and an interrupt register 1218. In addition, disk interface 1200 includes a disk interface buffer 1220 for communicating with mass storage access device 106 via bus 130.
[0108] In the example embodiment, disk interface 1200 works primarily on a command packet and direct memory access basis. The disk interface 1200 operates as a transport for command packets sent to mass storage access device 106, and does not actually interpret the packets themselves. Operating on a packet basis allows the development of packet commands and the mechanism for mass storage access device 106 to be completed separately from the development of the actual physical interface provided by disk interface 1200.
[0109] Disk interface 1200 distinguishes between packets that comprise direct memory access commands and packets that comprise immediate commands. Direct memory access commands in the example embodiment begin with a command packet and then cause data to be sent to/from main memory 112 using direct memory access under control of direct memory access controller 1216. Immediate commands in the example embodiment begin with a command packet and result in data being transferred to/from the disk interface immediate data buffer 1212. Disk interface 1200 in the example embodiment includes the following features:
[0110] support for direct memory access mode commands,
[0111] support for immediate mode access register command,
[0112] direct memory access to/from main memory 112 on 32 byte boundaries/32 byte length,
[0113] break signal to interrupt current command,
[0114] maskable interrupt on transaction complete,
[0115] maskable interrupt on error received from mass storage access device 106,
[0116] 25 megabyte per second parallel interface to mask storage access device 106,
[0117] both read and write commands (including BMA supported),
[0118] bulk data transfer for debug.
[0119] As shown in FIGS. 7A and 7B, parallel bus 130 from disk interface 1200 to mass storage access device 106 includes the following signals:
[0120] a bi-directional, 8-bit wide parallel path DIDD,
[0121] a signal DIDIR from disk interface 1200 to mass storage access device 106,
[0122] a DIHSTRBb signal from disk interface 1200 to mass storage access device 106,
[0123] a DIDSTRBb signal from mass storage access device 106 to disk interface 1200,
[0124] a DIERR signal from mass storage access device 106 to disk interface 1200,
[0125] a DIBRK bi-directional signal between disk interface 1200 and mass storage access device 106,
[0126] a DIRSTb signal from disk interface 1200 to mass storage access device 106,
[0127] a DICOVER signal from mass storage access device 106 to disk interface 1200.
[0128] The following describes the various signals:
| Name | Dir | Type | Description |
|---|---|---|---|
| DIDD[7:0] | I/O | LVCMOS | DI Data: DI Data bus. Depending upon the DIDR |
| (Direction) signal, the data bus is driven by main processor | |||
| 110 or mass storage access device. When main processor | |||
| 110 is writing data the signals are outputs and the data | |||
| should be latched by the mass storage access device 106 on | |||
| the rising edge of the DIHSTRBn signal. When main | |||
| processor 110 is reading data from the mass storage access | |||
| device 106, the DIDD[7:0] signals are inputs and the data | |||
| should be latched on the rising edge of the DIDSTRBn | |||
| signal. | |||
| During reset, this bus can be used for latching in the | |||
| configuration. It is implemented as 8 bit transparent latches | |||
| controlled by sync reset and they sample the reset state of | |||
| the DIDD bus and hold the state on the rising edge of the | |||
| sync resetb. Currently, bit 0 is used for ROM scramble | |||
| disable, bits 1-7 are reserved. | |||
| DIDIR | O | LVCMOS | DI Direction: This signal controls the current direction of |
| the DIDD[7:0] data bus. |
[0129] FIG. 7C shows example registers within disk interface 1200 that are accessible by main processor 110. The FIG. 7C registers are each 32-bits wide and fall on 32-bit address boundaries. Main processor 110 can access these registers through 32-bit or 16-bit reads and writes. In the example embodiment, the base address of these disk interface registers is 0x0C006000.
[0130] The following sets forth definitions of example disk interface registers shown in FIG. 7C:
[0131] DISR: DI Status Register
[0132] Mnemonic: DISR
[0133] Offset: 0x00
[0134] Size 32 bits
| DISR |
[0135] DICVR: DI Cover Register
[0136] Mnemonic: DICVR
[0137] Offset: 0x04
[0138] Size 32 bits
| DICVR |
[0139] DICMDBUF0: DI Command Buffer 0
[0140] Mnemonic: DICMDBUF0
[0141] Offset: 0x08
[0142] Size 32 bits
| DICMDBUF0 |
[0143] DICMDBUF1: DI Command Buffer 1
[0144] Mnemonic: DICMDBUF 1
[0145] Offset: 0x0C
[0146] Size 32 bits
| DICMDBUF1 |
[0147] DICMDBUF2: DI Command Buffer 2
[0148] Mnemonic: DICMDBUF2
[0149] Offset: 0x10
[0150] Size 32 bits
| DICMDBUF1 |
[0151] DI DMA Memory Address Register
[0152] Mnemonic: DIMAR
[0153] Offset: 0x14
[0154] Size 32 bits
| DIMAR |
[0155] DILENGTH: DI DMA Transfer Length Register
[0156] Mnemonic: DILENGTH
[0157] Offset: 0x18
[0158] Size 32 bits
| DILENGTH |
[0159] DICR: DI Control Register
[0160] Mnemonic: DICR
[0161] Offset: 0x1C
[0162] Size 32 bits
| DICR |
[0163] DIIMMBUF DI Immediate Data Buffer
[0164] Mnemonic: DIIMMBUF
[0165] Offset: 0x20
[0166] Size 32 bits
| DIIMMBUF |
[0167] DICFG: DI Configuration Register
[0168] Mnemonic: DICFG
[0169] Offset: 0x24
[0170] Size 32 bits
| DICFG |
Example Serial Interface
[0171] FIGS. 8A and 8B show an example serial interface 1000. In this particular example, serial interface 1000 is a single bit serial interface that runs at 250 kHz. This single bit serial interface is similar to the “joybus” control interface used in the prior art Nintendo 64® product manufactured by Nintendo, but there are some differences. Example serial interface 1000 provides the following features in the example embodiment:
[0172] four separate 250 kHz serial interfaces for four controllers 52,
[0173] each interface can be accessed in parallel,
[0174] in controller mode, the last state of the controller 52 is in a double-buffered processor input/output register so that main processor 110 can simply read the register to determine the controller state,
[0175] the controller state is automatically polled by hardware with configurable polling periods,
[0176] bulk mode (changeable data size),
[0177] two light gun signals are used to control two separate horizontal/vertical counters to support both flash and shutter light guns,
[0178] an LCD shutter is supported through automatic polling and serial control commands, and
[0179] the serial interface 1000 can automatically detect the presence of hand controllers 52.
[0180] FIG. 8A shows the external interface of serial interface 1000. In this example, there are four separate controller ports 1002 on system 50. Each port 1002 has a pair of input and output pins (shown by the “x” mark blocks in FIG. 8A). The input pin connects directly to an external game controller 52 in the example embodiment. The output pin in the example embodiment connects to an external open-drain driver (not shown) which in turn connects directly to the external game controller 52. In the example embodiment, two of the ports 1002 have horizontal/vertical latch signals that can be used to latch horizontal/vertical counters within the video interface 164. These signals combined with the functionality of serial interface 1000 provide support for flash and shutter type light guns. The vertical latch and control registers used for this functionality are located in the video interface 164 in the example embodiment. FIG. 8A shows each of the four serial ports 1002 including an SIDI (bidirectional) line and an SIDO (unidirectional) controller output-to-serial interface 1000 line. The following shows example descriptions of these two signals:
| Name | Dir | Type | Description |
|---|---|---|---|
| SIDI[3:0] | I | LVCMOS | Serial Interface Data Input: SIDI[3:0] are input signals, each |
| bit is a separate half-duplex, 250 kbit/s input serial channel. | |||
| The serial protocol is an asynchronous interface and is self | |||
| timed, using a pulse width modulated signaling scheme. | |||
| SID0[3:0] | O | LVCMOS | Serial Interface Data Output: SIDO[3:0] are output signals, |
| each bit is a separate half-duplex, 250 kbit/s output serial | |||
| channel. The serial protocol is an asynchronous interface and | |||
| is self timed, using a pulse width modulated signaling scheme. | |||
[0181] FIG. 8B is a more detailed block diagram of serial interface 1000. As shown in this Figure, serial interface 1000 includes a main processor interface 1010, a serial interface communication circuitry and registers 1012, a small (128 byte) communication RAM 1014, and an input/output buffer arrangement 1016 for each of the four serial ports 1002.
[0182] FIG. 8C shows an example set of registers (register map) used to control serial interface 1000 in the example embodiment. The base address for these serial interface registers in the example embodiment is 0x0C006400. The following describes each of these various example registers in the example embodiment:
[0183] SIC0OUTBUF SI Channel 0 Output Buffer
[0184] Mnemonic: SIC-OUTBUF
[0185] Offset: 0x00
[0186] Size 32 bits
| SIC0OUTBUF |
[0187] This register is double buffered, so main processor writes to the SIC0OUTBUF will not interfere with the serial interface output transfer. Internally, a second buffer is used to hold the output data to be transferred across the serial interface. To check if SIC0OUTBUF has been transferred to the second buffer, main processor 110 polls the SISR[WRST0] register. When SICOOUTBUF is transferred, SISR[WRST0] is cleared.
[0188] SIC0INBUF SI Channel 0 Input Buffer High
[0189] Mnemonic: SIC0INBUFH
[0190] Offset: 0x04
[0191] Size 32 bits
| SIC0INBUFH |
[0192] SIC0INBUFH and SIC0INBUFL are double buffered to prevent inconsistent data reads due to main processor 110 conflicting with incoming serial interface data. To insure data read from SIC0INBUFH and SIC0INFUBL are consistent, a locking mechanism prevents the double buffer from copying new data to these registers. Once SIC0INBUFH is read, both SIC0INBUFH and SIC0INBUFL are ‘locked’ until SIC0INBUFL is read. While the buffers are ‘locked’, new data is not copied into the buffers. When SIC0INBUFL is read, the buffers become unlocked again.
[0193] SIC0INBUF SI Channel 0 Input Buffer Low
[0194] Mnemonic: SIC0INBUFL
[0195] Offset: 0x08
[0196] Size 32 bits
| SIC0INBUFL |
[0197] SIC1OUTBUF SI Channel 1 Output Buffer
[0198] Mnemonic: SIC 1 OUTBUF
[0199] Offset: 0x0C
[0200] Size 32 bits
| SIC1OUTBUF |
[0201] SIC1INBUF SI Channel 1 Input Buffer High
[0202] Mnemonic: SIC1INBUFH
[0203] Offset: 0x10
[0204] Size 32 bits
| SIC1INBUFH |
[0205] SIC1INBUF SI Channel 1 Input Buffer Low
[0206] Mnemonic: SIC1INBUFL
[0207] Offset: 0x14
[0208] Size 32 bits
| SIC1INBUFL |
[0209] SIC2OUTBUF SI Channel 2 Output Buffer
[0210] Mnemonic: SIC2OBUF
[0211] Offset: 0x18
[0212] Size 32 bits
| SIC2OUTBUF |
[0213] SIC2INBUF SI Channel 2 Input Buffer High
[0214] Mnemonic: SIC2INBUFH
[0215] Offset: 0x1C
[0216] Size 32 bits
| SIC2INBUFH |
[0217] SIC2INBUF SI Channel 2 Input Buffer Low
[0218] Mnemonic: SIC2INBUFL
[0219] Offset: 0x20
[0220] Size 32 bits
| SIC2INBUFL |
[0221] SIC30UTBUF SI Channel 3 Output Buffer
[0222] Mnemonic: SIC3OBUF
[0223] Offset: 0x24
[0224] Size 32 bits
| SIC3OUTBUF |
[0225] SIC3INBUF SI Channel 3 Input Buffer High
[0226] Mnemonic: SIC3INBUFH
[0227] Offset: 0x28
[0228] Size 32 bits
| SIC3INBUFH |
[0229] SIC3INBUF SI Channel 3 Input Buffer Low
[0230] Mnemonic: SIC3INBUFL
[0231] Offset: 0x2C
[0232] Size 32 bits
| SIC4INBUFL |
[0233] SIPOLL SI Poll Register
[0234] Mnemonic: SIPOLL
[0235] Offset: 0x30
[0236] Size 32 bits
| SIPOLL |
[0237] SICOMCSR SI Communication Control Status Register
[0238] Mnemonic: SICOMCSR
[0239] Offset: 0x34
[0240] Size 32 bits
| SICOMCSR |
[0241] When programming the SICOMCSR after a SICOM transfers has already started (e.g., SICOMCSR[TSTART] is set), the example software reads the current value first, then and/or in the proper data and then write the new data back. The software should not modify any of the transfer parameters (OUTLNGTH, INLNGTH, CHANNEL) until the current transfer is complete. This is done to prevent a SICOM transfer already in progress from being disturbed. When writing the data back, the software should not set the TSTART bit again unless the current transfer is complete and another transfer is required.
[0242] SISI SI Status Register
[0243] Mnemonic: SISR
[0244] Offset: 0x38
[0245] Size 32 bits
| SISR |
[0246] SIEXILK SI EXI Clock Lock
[0247] Mnemonic: SIEXILK
[0248] Offset: Ox3C
[0249] Size 32 bits
| SIEXILK |
[0250] FIG. 8D is an even more detailed overall view of serial interface 1000 showing the details of serial interface communication circuitry and registers 1012. Controllers 52aand 52b(and 52cand 52d,if present) are connected to game console 54 via connector ports 1002. Modem 1404 modulates and demodulates data transferred between the controllers and the console. In the example system, communication between the console and the controllers uses duty-cycle (pulse-width) modulation and the data is communicated over one line. The communication is half-duplex. The byte transfer order is “big-endian” in which within a given multi-byte numeric representation, the most significant byte has the lowest address (i.e., the data is transferred “big-end” first). Controller input/output buffer 1016 is used for normal data transfers involving controllers 52a-52d.As shown in FIG. 8D, input/output buffer 1016 is arranged as a double buffer. Communication RAM 1014 is provided for use in variable-size data transfers to and from controllers 52a-52d.In the example system, the maximum data size of these variable-size data transfers is 32 words. Of course, the present invention is not limited in this respect. Channel selector circuit 1408 controls selectors 1412a-1412dto selectively connect modem 1404 to either communication RAM 1014 or input/output buffer 1016. An HV counter latch circuit 1406 latches the screen position of a flash signal when a trigger input is received from a light gun unit. In the example system shown in FIG. 8, triggers inputs to the HV counter latch circuit 1406 are provided for connectors 1 and 2 only. It will be apparent that trigger inputs may be provided for the other connectors if desired. HV counter latch circuit 1406 may also be used with light pens connected to connectors 1 and/or 2.
[0251] Additional details of the serial interface may be found in application Ser. No. 09/722,664 filed Nov. 28, 2000 of Shimuzu et al. entitled “Controller Interface for a Graphics System”, the contents of which are incorporated herein.
Example External Interfaces
[0252] FIG. 9A is a block diagram of an example external interface logic 1100. In the example embodiment, external interface block 1100 supports three separate external interface channels 1102. In the example embodiment, external interface channel 1102(0) has a somewhat different configuration than channels 1102(1), 1102(2). This enables external interface channel 1102(0) to support both expansion and on-board devices and peripherals. Each of channels 1102 provides support for 8-bit word EXI operation. In the example embodiment, the entire ROM 134 is memory mapped on the external interface channel 1102(0), and ROM reads are controlled entirely by hardware for boot support.
[0253] The external interface 1100 in the example embodiment was chosen based on current support by several manufacturers (e.g., Macronix) for the EXI interface on Macronix's CMOS serial flash EEPROM parts. The implemented EXI protocol is based on and compatible with MXIC's MX25L4004 EXI interface. The preferred embodiment example external interface 1100 includes five separate chip select signals to control five different devices (e.g., ROM/RTC 134, flash memory 140, expansion modem 136, expansion backup memory card 144, etc.). Different implementations could provide different numbers of chip selects. The example embodiment external interface 1100 includes three maskable external interrupts (one for each expansion port/channel 1102) that are used to signal EXI transfer complete for each channel. An additional pair of maskable interrupts provided by channels 1102(0) and 1102(1) is used to provide hot-plug status for peripheral insertion and removal. Each of channels 1102 support general DMA (direct memory access) transfers in the example embodiment.
[0254] Referring to FIG. 9B, the portion 1100(0) of external interface 1100 supporting external interface channel 1102(0) includes a CPU interface 1104, a memory controller interface 1106, a direct memory access controller 1108 and associated FIFO buffer 1110, a ROM control 1112, an external interface data buffer/register 1114, a bus transceiver 1116, and an interrupt register 1118.
[0255] Block diagrams for the example external channel one interface 1100(1) and example external channel two interface 1100(2) are shown in FIGS. 9C and 9D, respectively. As can be appreciated from comparing FIGS. 9B, 9C and 9D, the channel one and channel two structures 1100(1), 1100(2) are quite similar to one another and each differ from the FIG. 9B structure in omitting the ROM control 1112(0).
[0256] The following table sets forth the various signal descriptions for the signals provided to/from example external interface ports 1102:
| Name | Dir | Type | Description |
|---|---|---|---|
| EXI0DO0 | O | LVCMOS | EXI Data Out 0 Channel 0: EXI0DO0 is an output |
| signal. EXI0DO0 transmits the serial data out to the slave | |||
| device, the MSB is sent first. The slave should latch data | |||
| on the rising edge of the EXI0CLK0. | |||
| EXI0DI0 | I | LVCMOS | EXI Data In 0 Channel 0: EXI0DI0 is an input signal. |
| EXI0DI0 receives the serial data from the slave device, the | |||
| MSB is received first. The data is latched on the rising | |||
| edge of the EXI0CLK0. | |||
| EXI0CLK0 | O | LVCMOS | EXI Clock 0 Channel 0: EXI0CLK0 is an output signal. |
| EXI0CLK0 synchronizes the transfer of the EXI0DO0 and | |||
| EXI0DI0 signals. Data is sent on a byte basis and 1 byte | |||
| can be sent in 8 clock cycles. The clock frequency is s/w | |||
| programmable, see EXI0CPR[CLK]. | |||
| EXI0DO1 | O | LVCMOS | EXI Data Out 1 Channel 0: EXI0DO1 is an output |
| signal. EXI0DO1 transmits the serial data out to the slave | |||
| device, the MSB is sent first. The slave should latch data | |||
| on the rising edge of the EXI0CLK1. | |||
| EXI0DI1 | I | LVCMOS | EXI Data In 1 Channel 0: EXI0DI1 is an input signal. |
| EXI0DI1 receives the serial data from the slave device, the | |||
| MSB is received first. The data is latched on the falling | |||
| edge of the EXI0CLK1. | |||
| EXI0CLK1 | I | LVCMOS | EXI Clock 1 Channel 0: EXI0CLK1 is an output signal. |
| EXI0CLK1 synchronizes the transfer of the EXI0DO1 and | |||
| EXI0DI1 signals. Data is sent on a byte basis and 1 byte | |||
| can be sent in 8 clock cycles. The clock frequency is s/w | |||
| programmable, see EXI0CPR[CLK]. | |||
| EXI0CS[2:0]B | I | LVCMOS | EXI Chip Select Channel 0 [2:0]B: EXI0CS[2:0]B are |
| output signals, active low. The EXI0CS[2:0]B signals | |||
| determine which EXI device on channel 0 is currently | |||
| selected. | |||
| EXI0TNTB | I | LVCMOS | EXI Interrupt Channel 1: EXI0INTB is an input signal, |
| active low, edge triggered. When asserted, this signal will | |||
| generate a main processor interrupt. The interrupt should | |||
| be cleared by accessing the interrupting device through the | |||
| EXI interface | |||
| EXI0EXTiN | I | LVCMOS | EXI External In Channel 0: EXI0EXTiN is an input |
| signals, when asserted high, it indicates that a device has | |||
| been plugged into the EXI bus | |||
| EXI1DO | O | LVCMOS | EXI Data Out Channel 1: EXI1DO is an output signal |
| EXI1DO transmits the serial data out to the slave device, | |||
| the MSB is sent first. The slave should latch data on the | |||
| rising edge of the EXI1CLK. | |||
| EXI1DI | I | LVCMOS | EXI Data In Channel 1: EXI1DI is an input signal. |
| EXI1DI receives the serial data from the slave device, the | |||
| MSB is received first. The data is latched on the falling | |||
| edge of the EXI1CLK. | |||
| EXI1CLK | I | LVCMOS | EXI Clock Channel 1: EXI1CLK is an output signal. |
| EXI1CLK synchronizes the transfer of the EXI1DO and | |||
| EXI1DI signals. Data is sent on a byte basis and 1 byte | |||
| can be sent in 8 clock cycles. The clock frequency is s/w | |||
| programmable, see EXI1CPR[CLK]. | |||
| EXI1CS0B | I | LVCMOS | EXI Chip Select Channel 1 0B: EXI1CS0B is an output |
| signal, active low. The EXI1CS0B signals determine | |||
| which EXI device on channel 1 is currently selected. | |||
| EXI1INTB | I | LVCMOS | EXI Interrupt Channel 1: EXI1INTB is an input signal, |
| active low, edge triggered. When asserted, this signal will | |||
| generate a CPU interrupt. The interrupt should be cleared | |||
| by accessing the interrupting device through the EXI | |||
| interface. | |||
| EXI1EXTIN | I | LVCMOS | EXI External In Channel 1: EXI1EXTIN is an input |
| signals, when asserted high, it indicates that device has | |||
| been plugged into the EXI bus. | |||
| EXI2DO | O | LVCMOS | EXI Data Out Channel 2: EXI2DO is an output signal. |
| EXI2DO transmits the serial data out to the slave device, | |||
| the MSB is sent first. The slave should latch data on the | |||
| rising edge of the EXI2CLK. | |||
| EXI2DI | I | LVCMOS | EXI Data In Channel 2: EXI2DO is an input signal. |
| EXI2DI receives the serial data from the salve device, the | |||
| MSB is received first. The data is latched on the falling | |||
| edge of the EXI2CLK. | |||
| EXI2CLK | I | LVCMOS | EXI Clock Channel 2: EXI2CLK is an output signal. |
| EXI2CLK synchronizes the transfer of the EXI2DO and | |||
| EXI2DI signals. Data is sent on a byte basis and 1 byte | |||
| can be sent in 8 clock cycles. The clock frequency is s/w | |||
| programmable, see EXI2CPR[CLK]. | |||
| EXI2INTB | I | LVCMOS | EXI Interrupt Channel 2: EXI2INTB is an input signal, |
| active low, edge triggered. When asserted, this signal will | |||
| generate a CPU interrupt. The interrupt should be cleared | |||
| by accessing the interrupting device through the EXI | |||
| interface. | |||
| EXI2CS0B | O | LVCMOS | EXI Chip Select Channel 2 OB: EXI2CS0B are output |
| signals, active low. The EXI2CS0B signals determine | |||
| which EXI device on channel 2 is currently selected. | |||
[0257] Serial Peripheral Interface
[0258] In one embodiment, main processor 110 can set the clock rates of these EXI channels to 32 MHz, 16 Mhz, 8 MHz, 4 MHz, 2 MHz and 1 MHz and these clocks rates may be set independently for the different channels. Chip select registers are used to identify the device to which the EXI bus is connected. For the example EXI0, CS0 (Chip Select 0) is set for a connection to an internal real time clock, CS1 is set for a connection to an internal IPL_ROM, and CS2 is set for an external device (modem, voice recognition system and the like). For the example EXI1, CS0 is set for a connection to an internal flash ROM and CS1 is set for an external device (modem, voice recognition system, and the like). Other configurations are possible.
[0259] Small size data as command is transferred between CPU registers immediately and large size data is transferred between main memory by direct memory access (DMA).
[0260] FIG. 9E shows example external interface registers. In the example embodiment, the base address for these registers is 0x0C006800. The following show example register definitions:
[0261] EXI Channel Parameter Register for channel 0
[0262] Mnemonic: EXI0CSR
[0263] Offset: 0x00
[0264] Size 32 bits
| EXIOCPR |
[0265] EXI0MAR: EXI0 DMA Memory Address Register
[0266] Mnemonic: EXI0MAR
[0267] Offset: 0x04
[0268] Size 32 bits
| EXI0MAR |
[0269] Mnemonic: EXI0LENGTH
[0270] Offset: 0x08
[0271] Size 32 bits
| EXI0LENGTH |
[0272] EXI0CR: EXI Control Register for channel 0
[0273] Mnemonic: EXI0CR
[0274] Offset: 0x0C
[0275] Size 32 bits
| EXI0CR |
[0276] EXI0DATA: EXI Data Register for channel 0
[0277] Mnemonic: EXI0DATA
[0278] Offset: 0x10
[0279] Size 32 bits
| EXI0DATA |
[0280] EXI1CPR: EXI Channel Parameter Register for channel 1
[0281] Mnemonic: EXI1CPR
[0282] Offset: 0x14
[0283] Size 32 bits
| EXI1CPR |
[0284] EXI1MAR: EXI1 DMA Memory Address Register
[0285] Mnemonic: EXI1MAR
[0286] Offset: 0x18
[0287] Size 32 bits
| EXI1MAR |
[0288] EXI1LENGTH: EXI1 DMA Transfer Length Register
[0289] Mnemonic: EXI1LENGTH
[0290] Offset: 0x1C
[0291] Size 32 bits
| EXI1LENGTH |
[0292] EXI1CR: EXI Control Register for channel 1
[0293] Mnemonic: EXI1CR
[0294] Offset: 0x20
[0295] Size 32 bits
| EXI1CR |
[0296] EXI1DATA: EXI Data Register for channel 1
[0297] Mnemonic: EXI1DATA
[0298] Offset: 0x24
[0299] Size 32 bits
| EXI1DATA |
[0300] EXI2CPR: EXI Channel Parameter Register for channel 2
[0301] Mnemonic: EXI2CPR
[0302] Offset: 0x28
[0303] Size 32 bits
| EXI2CPR |
[0304] EXI2MAR: EXI2 DMA Memory Address Register
[0305] Mnemonic: EXI2MAR
[0306] Offset: 0x2C
[0307] Size 32 bits
| EXI2MAR |
[0308] EXI2LENGTH: EXI2 DMA Transfer Length Register
[0309] Mnemonic: EXI2LENGTH
[0310] Offset: 0x30
[0311] Size 32 bits
| EXI2LENGTH |
[0312] EXI2CR: EXI Control Register for channel 2
[0313] Mnemonic: EXI2CR
[0314] Offset: 0x34
[0315] Size 32 bits
| EXI2CR |
[0316] EXI2DATA: EXI Data Register for channel 2
[0317] Mnemonic: EXI2DATA
[0318] Offset: 0x38
[0319] Size 32 bits
| EXI2DATA |
Example Audio Interfaces
[0320] FIG. 10A shows an example collection of audio interfaces for system 50. In the example embodiment, audio interfaces 1300 include a disk serial interface 1302, a digital-to-analog converter interface 1304, and an audio interface 1306. Digital-to-analog converter (DAC) serial interface 1304 receives an output from mixer 160 and converts that output to a form suitable for processing by audio codec 122 for reproduction on speakers 61. The disk serial interface 1302 receives the streaming audio input from mass storage access device 106 and provides it to a source block 1308. The audio interface 1306 is capable of reading digital audio from buffers stored in main memory and providing left and right digital audio streams to mixer 160.
[0321] The example embodiment audio interfaces 1300 provide support for external 16-bit stereo digital-to-analog converter interfaces running at a fixed 48 kHz sampling rate. The disk serial interface 1302 provides an optical disk streaming audio input interface providing 16-bit serial interface running at 32 kHz or 48 kHz sampling rate. This allows audio mixer 160 to mix the streaming audio input at programmable audio volume control. Disk serial interface 1302 provides sample rate conversion “on the fly” to, for example, change from a 32 kHz sampling rate provided by the mass storage access device 106 to a 48 kHz sampling rate.
[0322] FIG. 10B shows the external interface of the digital-to-analog converter serial interface 1304. This interface streams the audio output data from an audio input buffer to the final audio mixer 160 in DAC interface. The interface treats the AI buffer as a simple FIFO and expects that buffer to always have the next sample ready. Data is requested at the DAC sample rate (e.g., 48 kHz).
[0323] The following are example signal definitions for the various signals shown in FIG. 10B:
| Name | Dir | Type | Description |
|---|---|---|---|
| AID | O | LVCMOS | Audio Interface Data Out: AIDO is an output signal. |
| AIDO drives the serial bit stream of the Left/Right Audio | |||
| data driven out to the stereo audio DAC, synchronized by | |||
| the rising edge of the bit clock AOCLKO and AILRO | |||
| signal which determines if the current word is a left | |||
| sample or a right sample. | |||
| AILR | O | LVCMOS | Audio Interface Left Right Out: AILRO is an output |
| signal. AILRO is a frame signal for the serial bit stream | |||
| and determines the left/right channel of the current word | |||
| An edge of AILRO also acts as a sample conversion | |||
| signal to the DAC. AILRO toggles at the sample rate | |||
| frequency (48 kHz). | |||
| AICLK | O | LVCMOS | Audio Interface Clock Out: AICLKO is an output |
| signal. AICLKO is the bit clock for the AIDO serial bit | |||
| stream. | |||
| AISD | I | LVCMOS | Audio Interface Streaming Data: AISD is an input |
| signal AISD is the serial bit stream of the Left Right audio | |||
| data driven in from the Disk drive, synchronized by the | |||
| rising edge of the bit clock. | |||
| AISLR | O | LVCMOS | Audio Interface Streaming Left Right: AISLR is an |
| output signal. AISLR is a frame signal for the serial bit | |||
| stream and determines the left/right channel of the current | |||
| word. AISLR toggles at the sample rate frequency (32 | |||
| kHz/48 kHz). This signal also controls the flow of the | |||
| audio data. After this current stereo sample is received, if | |||
| AISLR does not toggle, the Disk assumes that the stream | |||
| is stopped/paused and sends 0’ as data. The Disk does not | |||
| begin sending data until it has received a high-low-high | |||
| sequence. | |||
| AISCLK | O | LCMOS | Audio Interface Streaming Clock: AISCLK is an |
| output signal. AISCLK is the bit clock for the AISD | |||
| serial bit stream. The AISCLK is a free running clock. | |||
[0324] FIG. 10C shows example audio interface registers having a base address of 0x0C006C00. The following show example register descriptions:
[0325] AICR: Audio Interface Control Register
[0326] Mnemonic: AICR
[0327] Offset: 0x00
[0328] Size 32 bits
| AICR |
[0329] AIVR: Audio Interface Volume Register
[0330] Mnemonic: AIVR
[0331] Offset: 0x04
[0332] Size 32 bits
| AIVR |
[0333] AISCNT: Audio Interface Sample Counter
[0334] Mnemonic: AISCNT
[0335] Offset: 0x08
[0336] Size 32 bits
| AISCNT |
[0337] AIIT: Audio Interface Interrupt Timing
[0338] Mnemonic: AIIT
[0339] Offset: 0x0C
[0340] Size 32 bits
| AIIT |
Example Video Interface
[0341] Video interface 164 in the example embodiment reads color information stored in main memory 112 and sends it to display 56. In more detail, the example video interface 164 has the following functions:
[0342] interfaces with an external video encoder (e.g., using a 10-pin—eight data pins plus one clock plus one phase—interface at 27 MHz,
[0343] generates NTSC, PAL or M-PAL timing,
[0344] requests pixels from the external frame buffer for display,
[0345] allows panning and windowing of a display region,
[0346] provides a video interrupt counter (resettable on field or frame basis),
[0347] interrupts the main processor 110 using four programmable timing registers,
[0348] captures raster position using a pair of light gun latches,
[0349] performs 4:4:4 RGB to 4:2:2 YCrCb conversion,
[0350] applies gamma correction to the RGB signal, and
[0351] interfaces to a 3D Liquid Crystal Display device.
[0352] Main processor 110 can write instructions to video interface 164 via a register interface. Video interface 164 can access main memory external frame buffer 113 via the graphics memory request arbitration 130. Additionally, video interface 164 provides an output to an external video encoder comprising three sets of signals:
[0353] video clock,
[0354] video clock phase, and
[0355] video data.
[0356] In the example embodiment, the video clock may be a single line having a 27 MHz rate. The video phase may provide a signal indicating YCb (low) or YCr (high) set on a single line. The video data bus may be eight bits wide, and contain YcrCb data during active display and video timing signals during blanking. An example timing diagram for this bus is shown in FIG. 11A.
[0357] Because the example embodiment clamps Y to 0x10 during active display, Y is set to 0x00 during the vertical blanking interval. During that time, CbCr are used for outputting video timing signals that may be encoded as follows:
| U/V Data | Flag | Description |
|---|---|---|
[0358] Because the timing signals are output in the Cb and Cr data only in the example embodiment, they should be expanded back to 13.5 MHz inside of the video encoder. As a result, horizontal sync and burst may be shifted by one pixel. An example timing diagram is shown in FIG. 11B.
[0359] In the example embodiment, vertical blanking can end on an even pixel (HBE is even), or it can end on an odd pixel (HBE is odd). In cases where HBE is even, the first chroma sample will be Cb followed by Cr, etc. In cases where HBE is odd, the first chroma sample will be Cr followed by Cb, etc. The diagram of FIG. 11C illustrates this.
[0360] The video interface 164 also includes a gun trigger interface consisting of two pins. Each pin detects the instance of a screen flash when a light gun trigger is pulled. Latch circuitry is used to mark the value of a screen timer when a screen flash is registered.
[0361] In the example embodiment, in order to simplify the external video encoder, the video interface 164 generates most of the video timing required by the encoder. Video interface 164 supports the timing of NTSC, PAL and M-PAL. In the example embodiment, video interface 164 displays the top field only in a non-interlace mode. Video interface 164 includes a timing generator responsible for generating video timing, control signals and interrupts. Basically this timing generator consists of two counters: a vertical line counter and a horizontal pixel counter. Once enabled, these counters run continuously at a pixel clock rate of, e.g., 27 MHz. A programmable decoder decodes the outputs of these counters. The decoder operates in four modes: NTSC, PAL, M-PAL, and debug mode. The debug mode is used for testing and simulation.
[0362] Video interface 164 generates addresses required to access pixel data from external frame buffer 113. It supports various addressing features including programmable picture size, windowing and pixel resolution pan and scan.
[0363] Video interface 164 also supports horizontal scaling such that a smaller frame buffer can be stretched horizontally to the desired display size. This is achieved by using a 6-tap sampling filter. Each filter tap has eight phases and a zero tap is added to have a total of forty-nine taps in the example embodiment. An output pixel is sampled to a 1/256 sub-pixel grid and is rounded to the nearest 1/8 sub-pixel in the example embodiment. This results in scan line being sampled up to eight times before it is down sampled to a target frequency. See example FIG. 11D.
[0364] The Y, Cr and Cb components are buffered in three separate shift registers in the example embodiment. Each register is responsible for replicating the first and last pixels for filtering at the boundaries. To ease implementation, Cb and Cr pixels are averaged to 4:4:4 before filtering. This prevents chroma words from reading ahead of luma words. It also allows luma and chroma to share the same control logic.
[0365] An internal stepper controls new sample position. The stepper is incremented by a step size every output pixel. The lowest eight bits of the stepper in the example embodiment are rounded to three bits for determining the phase of the filter. Only one bit to the left of the binary pointer is kept. If that bit is toggled, a new pixel is shifted into the pixel registers. The step size in the example embodiment for the stepper is determined by:
[0366] step size=floor (256×destination size/source size)/256.
[0367] FIG. 11E shows example shifters, and FIG. 11F shows an example filter data path. In the example embodiment, the video clock rate is twice the pixel rate (27 vs. 13.5), so the data path is time shared between the three components. The example data path shown in FIG. 11F consists of six multipliers, an adder and a set of lookup tables.
[0368] The step size and the filter coefficients are set up through the video interface 164 register interface in the example embodiment. The filter can be programmed to have different cut off frequencies, passband ripple and stopband attenuation. As the filter is symmetrical, only half of it is programmed. To conserve hardware in the filter, the filter coefficients are enveloped so that the center sixteen coefficients are in the range [0,2.0]. The outer 32 coefficients are in the range [−0.125, 0.125]. Eight times up-sampling is equivalent to a 0.5 Hz lowpass filter at an 8 Hz sampling rate. A conventional SINC filtering function can be used for windowing in the example embodiment.
[0369] Video interface 164 can support a 3D liquid crystal display by merging two frame buffer images (left and right) into a single stream of video. The output interleaves between the left and right pictures every two pixels. FIG. 11G shows an example timing diagram.
[0370] The example embodiment video interface 164 provides a gun trigger control supporting three sampling modes: 1-field (gun trigger is sampled for one field), 2-field (gun trigger is sampled for two fields), and continuous. In the 1/2-field mode, the detection mechanism includes the event sequence shown in FIG. 11H. In continuous mode, the trigger is sampled continuously until it is disabled.
[0371] In the example embodiment, the first gun trigger in a field latches the value of the display counters and gun triggers occurring in the remainder of the field are ignored.
[0372] The following tables describe various control registers within example video interface 164. The fourth column in each table shows the power-up reset values.
[0373] Display Configuration Register (R/W)
[0374] This register set ups and enables VI. Generally, VI should be reset before enabling it. This resets the states into some known values.
| ENB | 0 | This bit enables the video timing generation and data request. | 0 |
| RST | 1 | This bit clears all data request and puts VI into its idle state. | 0 |
| NIN | 2 | To select interlace or non-interlace mode. NIN = 0: interlace, NIN = 1: | 0 |
| non-interlace. In non-interlace mode, the top field is drawn at field rate | |||
| while the bottom field is not displayed. | |||
| DLR | 3 | This bit selects the 3D display mode. | |
| LE0 | 5:4 | Gun trigger mode. It enables the Display Latch Register 0. When the | 0 |
| mode is 1 or 2, it will clear itself(off) automatically when a gun trigger | |||
| is detected or at time out. This field is double buffered. | |||
| 0 off | |||
| 1 on for 1 field | |||
| 2 on for 2 fields | |||
| 3 always on | |||
| LE1 | 7:6 | To enable Display Latch Register 1. See the description of LE0. | 0 |
| FMT | 9:8 | Indicates current video format: | 0 |
| 0 NTSC | |||
| 1 PAL | |||
| 2 MPAL | |||
| 3 Debug (CCIR656) | |||
[0375] Horizontal Timing 0 Register (RJW)
[0376] This register setups the horizontal timing.
| HLW | 9:0 | Half line width. | − | |
| HCE | 22:16 | Horizontal sync start to color burst end. | − | |
| HCS | 30:24 | Horizontal sync start to color burst start. | − | |
[0377] Horizontal Timing 1 Register (R/W)
[0378] This register setups the horizontal timing.
| HSY | 6:0 | Horizontal sync width. | − |
| HBE | 16:7 | Horizontal sync start to horizontal blanking end. | − |
| HBS | 26:17 | Half line to horizontal blanking start. | − |
[0379] Vertical Timing Register (R/W)
[0380] This register setups the vertical timing. The value ACV is double buffered
| EQU | 3:0 | Equalization pulse in half lines. | − | |
| ACV | 13:4 | Active video in full lines. | − | |
[0381] Odd Field Vertical Timing Register (R/W)
[0382] This register sets up the pre-blanking and post-blanking intervals of odd fields. The values PRB and PSB are double buffered.
| PRB | 9:0 | Pre-blanking in half lines. | − | |
| PSB | 25:16 | Post-blanking in half lines. | − | |
[0383] Even Field Vertical Timing Register (R/W)
[0384] This register sets up the pre-blanking and post-blanking intervals of even fields. The values PRB and PSB are double buffered.
| PRB | 9:0 | Pre-blanking in half lines. | − | |
| PSB | 25:16 | Post-blanking in half lines. | − | |
[0385] Odd Field Burst Blanking Interval Register (R/W)
[0386] This register sets up the burst blanking interval of odd fields.
| BS1 | 4:0 | Field 1 start to burst blanking start in half lines. | − |
| BE1 | 15:5 | Field 1 start to burst blanking end in half lines. | − |
| BS3 | 20:16 | Field 3 start to burst blanking start in half lines. | − |
| BE3 | 31:21 | Field 3 start to burst blanking end in half lines. | − |
[0387] Even Field Burst Blanking Interval Register (R/W)
[0388] This register sets up the burst-blanking interval of even fields.
| BS2 | 4:0 | Field 2 start to burst blanking start in half lines. | − |
| BE2 | 15:5 | Field 2 start to burst blanking end in half lines. | − |
| BS4 | 20:16 | Field 4 start to burst blanking start in half lines. | − |
| BE4 | 31:21 | Field 4 start to burst blanking end in half lines. | − |
[0389] Top Field Base Register L (R/W)
[0390] This register specifies the display origin of the top field of a picture in 2D display mode or for the left picture in 3D display mode.
| FBB | 23:0 | External memory address of the frame buffer image. | − |
| XOF | 27:24 | Horizontal offset, in pixels, of the left-most pixel | − |
| within the first word of the fetched picture. | − | ||
[0391] Top Field Base Register R (R/W)
[0392] This register specifies the base address of the top field for the right picture in the 3D display mode. It is not used in 2D display mode.
| FBB | 23:0 | External memory address of the frame buffer image. | − |
[0393] Bottom Field Base Register L (R/W)
[0394] This register specifies the display origin of the bottom field of a picture in 2D display mode or for the left picture in 3D display mode.
| FBB | 23:0 | External memory address of the frame buffer image. | − |
[0395] Bottom Field Base Register R (R/W)
[0396] This register specifies the base address of the bottom field for the right picture in the 3D display mode. It is not used in 2D display mode.
| FBB | 23:0 | External memory address of the frame buffer image. | − |
[0397] Picture Configuration Register (R/W)
[0398] This register specifies the picture configuration.
| STD | 7:0 | Stride per line in words. | − | |
| WPL | 14:8 | Number of reads per line in words. | − | |
[0399] Display Position Register (R)
[0400] This register contains the current raster position.
[0401] The Horizontal Count is in pixels and runs from 1 to # pixels per line. It is reset to 1 at the beginning of every line.
[0402] The Vertical Count is in lines (on a frame basis) and runs from 1 to # lines per frame. It is 1 at the beginning of pre-equalization. This is a frame line count. So for example: for NTSC vcount=264 is the first (full) line in the second field and vcount=525 is the last line in the frame (fields being numbered 1-4). For non-interlaced modes vcount is on a field-by-field basis (for NTSC vcount ranges from 1-263).
[0403] This counting scheme applies the Display Position, Display Interrupt, and Display Latch registers.
| HCT | 10:0 | Horizontal count. | — | |
| VCT | 26:16 | Vertical count. | — | |
[0404] Display Interrupt Register 0 (R/W)
[0405] There are a total of four display interrupt registers (0-3). They are used to generate interrupts to the main processor at different positions within a field. Each register has a separate enable bit. The interrupt is cleared by writing a zero to the status flag (INT).
| HCT | 10:0 | Horizontal count to generate interrupt. | — |
| VCT | 26:16 | Vertical count to generate interrupt. | — |
| ENB | 28 | Interrupt is enabled if this bit is set. | 0 |
| INT | 31 | Interrupt status. A “1” indicates that an interrupt is | 0 |
| active. | |||
[0406] Display Interrupt Register 1 (R/W)
[0407] See the description of Display Interrupt Register 0.
[0408] Display Interrupt Register 2 (R/W)
[0409] See the description of Display Interrupt Register 0.
[0410] Display Interrupt Register 3 (R/W)
[0411] See the description of Display Interrupt Register 0.
[0412] Display Latch Register 0 (R/W)
[0413] The Display Latch Register 0 latches the value of the Display Position Register at the rising edge of the gt0 signal. The trigger flag is set if a gun trigger is detected. Writing a zero to the register clear the trigger flag.
| HCT | 10:0 | Horizontal count. | 0 | |
| VCT | 26:16 | Vertical count. | 0 | |
| TRG | 31 | Trigger flag. | 0 | |
[0414] Display Latch Register 1 (R/W)
[0415] See the description of Display Latch Register 0. This register is latched on the rising edge of the gt1 signal.
[0416] Output Polarity Register (R/W)
[0417] This register sets up the polarity of the out going control signals
| I_POL | 0 | Inverts Interlace Flag | 0 | |
| N_POL | 1 | Inverts NTSC Flag | 0 | |
| K_POL | 2 | Inverts Burst Blank Flag | 0 | |
| B_POL | 3 | Inverts Burst Flag | 0 | |
| H_POL | 4 | Inverts HSyncb Flag | 0 | |
| V_POL | 5 | Inverts VSyncb Flag | 0 | |
| F_POL | 6 | Inverts Field Flag | 0 | |
| C_POL | 7 | Inverts CSyncb Flag | 0 | |
[0418] Horizontal Scale Register (R/W)
[0419] This register sets up the step size of the horizontal stepper.
| STP | 8:0 | Horizontal stepping size (U1.8). | 256 | |
| HS_EN | 12 | Horizontal Scaler Enable | 0 | |
[0420] Scaling Width Register (R/W)
[0421] This register is the number of source pixels to be scaled. This is only used when the Horizontal Scaler is enabled. For example, if the image is to be scaled from 320x240 to 640x240, 320 would be written into this register.
| SRCWIDTH | 9:0 | Horizontal stepping size | 0 | |
[0422] Border HBE (R/W)
[0423] This register (in conjunction with the border HBS) sets up a black border around the actual active pixels in debug mode. This was done in order to accommodate certain encoders that only support 720 active pixels. The border HBE and HBS can be programmed for 720 active pixels while the regular HBE and HBS can be programmed to the actual active width. This allows the frame buffer to be of any width without having to manually set up a border in memory. These registers will only take effect if enabled and in debug mode.
| HBE656 | 9:0 | Border Horizontal Blank End | 0 | |
| BRDR_EN | 15 | Border Enable | 0 | |
[0424] Border HBS (R/W)
| HBS656 | 9:0 | Border Horizontal Blank Start | 0 | |
[0425] Filter Coefficient Table 0 (R/W)
[0426] This register sets up part of the low pass filter. Taps 0 to 9 are in the range [0.0, 2.0).
| T0 | 9:0 | Tap 0 (U1.9). | — | |
| T1 | 19:10 | Tap 1. | — | |
| T2 | 29:20 | Tap 2. | — | |
| Filter Coefficient Table 1 (R/W) |
|---|
| This register sets up part of the low pass filter. |
| Filter Coefficient Table 2 (R/W) |
|---|
| This register sets up part of the low pass filter. |
| Filter Coefficient Table 3 (R/W) |
|---|
| This register sets up part of the low pass filter. Taps 9 to tap 24 |
| are in the range [−0.125, 0.125). |
| Filter Coefficient Table 4 (R/W) |
|---|
| This register sets up part of the low pass filter. |
| Filter Coefficient Table 5 (R/W) |
|---|
| This register sets up part of the low pass filter. |
| Filter Coefficient Table 6 (R/W) |
|---|
| This register sets up part of the low pass filter. |
| VI Clock Select Register (R/W) |
|---|
| This register selects whether the VI will receive a 27 Mhz or a 54 Mhz |
| clock. The 54 Mhz clock is used only with the progressive |
| display modes. |
| VI DTV Status Register (R) |
|---|
| This register allows software to read the status of two I/O pins. |
Example Detailed Overall System Embodiment/Implementation
[0427] FIG. 12 shows an example, detailed embodiment/implementation of system 50 shown in FIG. 2. In this example implementation:
[0428] A clock generator 1502 provides clocking signals to both main microprocessor 110 and to graphics and audio processor 114.
[0429] A 32-bit address bus and a 64-bit data bus connect the graphics and audio processor 114 with the main microprocessor 110.
[0430] Main memory 112 is implemented as a pair of 96-megabit, 1TSRAM chips manufactured by MOSYS, Inc.
[0431] A multi-pin modem connector 1514 is used to connect the graphics and audio processor 114 to an external or internal modem.
[0432] The boot ROM/real time clock 134 is coupled to the modem connector 1514 and shares its bus for communication with the graphics and audio processor 114.
[0433] Three multi-pin EXI connectors 1516, 1518, 1520 are used to connect the graphics and audio processor 114 to various internal and/or external peripheral or other devices.
[0434] A multi-pin serial connector 1510 is used to couple the graphics and audio processor 114 to four controller connectors 1523a,1523b,1523c,1523deach of which is connected to a different hand controller 52 or other external input/output device.
[0435] A multi-pin disk interface connector 1521 is used to couple the graphics and audio processor 114 to the optical disk drive 106.
[0436] The SDRAM 126 may be provided with a multi-pin expansion connector 1549 that can be used to expand the 128 MB capacity of SDRAM 126 with an additional SDRAM expansion module 126a.
[0437] An analog audio/video connector 1550 having multiple pins communicates analog audio and video information between the graphics and audio processor 114 and external devices such as, for example, television sets, external display monitors, external loudspeakers or other input/output devices.
[0438] A digital audio/video connector 1552 having multiple pins makes the digital and audio interface provided by graphics and audio processor 114 available to the outside world for connection to any of a variety of different digital video and/or audio devices.
[0439] In the example shown, each of connectors 1510, 1514, 1516, 1518, 1520, 1523a-1523d,1549, 1550, 1552, 1521 comprises a mating male and female multi-pin connector that allows connections to be made, broken and remade without destructive or permanent processes such as soldering or permanent (non-deformable) crimping. Use of such connectors allows simple and easy connection and disconnection between different modular portions of system 50 to provide an east-to-manufacture system that can also be expanded, extended and reconfigured in the field without special equipment and involved processes.
[0440] Skipping ahead to FIGS. 22-27, those diagrams show an example external view of system 50 within a housing H. Referring specifically to FIG. 22, housing H includes a front side F, a back side B, a top surface T and a bottom surface Q. Disk drive 106 may be housed beneath a hinged, openable access cover C that allows the user to insert optical disks 62 into a housing H. Controller connectors 1523a,1523b,1523c,1523cmay be disposed on front surface F (as best shown in FIG. 23). Example connectors 1523 may each comprise a 10-10 female connector configured to accept a mating 10-10 male connector of appropriate configuration. Such a connector may, for example, couple system 50 to a wire-connected handheld controller 52, a light gun, or any other peripheral device. FIG. 24 shows an example peripheral device PD (in this case a receiver for a wireless handheld controller 52—but it could be any sort of device) connected to connector 1523aand being supported by the connector configuration.
[0441] Referring now more particularly to FIG. 25, a digital audio/video connector 1552 and an analog audio/video connector 1550 may be disposed on rear surface B of housing H. Each of these connectors 1550, 1552 can output sound and picture signals. However, the digital connector 1552 provides access to the internal video and audio buses described above—thereby providing additional flexibility in terms of interfacing system 50 with sophisticated digital audio and/or video equipment. A connector CH of an appropriate configuration can be connected to the digital connector 1552, and the other end of such a connector/cable CH′ can be connected to any sort of compatible external equipment. Similarly, a connector (not shown) can be coupled to the analog audio/video connector 1550 to provide analog audio and video information to a home television set, display monitor or other such equipment. A two-pin power supply connector P may also be provided on rear panel B for inputting DC power to system 50. For example, an external 12 volt DC power supply can provide 12 volts DC to connector P, and internal voltage regulation circuitry can regulate this 12 volt DC power supply level down to appropriate lower intermediate voltage levels.
[0442] Referring to FIG. 26, the bottom surface U of housing H may include a number of recesses normally covered by covers (not shown). Removal of such covers exposes recesses and associated connectors. For example, a recess R1may include a “high speed port” connector such as the EXI1 connector 1518, a recess R2may expose and provide connection to a modem connector 1514. Further recess R3may expose and provide connection to an additional serial port such as the EXI2 connector 1520 as best seen in FIG. 27, peripheral devices P1, P2, P3can be mechanically configured to fit dimensionally within corresponding recess R1, R2, R3so that such peripheral devices can be mounted flush within the generally cubic configuration of housing H. Such peripheral devices P1, P2, P3may include a broadband adapter, a modem, or any other sort of electronic or electrical device providing data inputs and/or outputs over a serial port. Each of the example preferred embodiment connectors provides power so that devices P1, P2, P3need not provide their own power sources. Devices P1, P2, P3can be modular and inserted or removed into corresponding recess R at will to provide different expansion and flush or other functionality for system 50. Of course, a connecting cable or wireless communications device could be coupled to any of the serial port connectors 1514, 1518, 1520 to allow system 50 to be interconnected with a free-standing external system or device.
[0443] Referring to FIGS. 23, 24 and 28B—28B, additional slots S on front panel F provide access to an additional internal serial bus (e.g., the EXI0 connector 1516, not shown). Slots S may be used to insert portable memory devices such as flash memory for example. A “digicard” memory device M shown in FIG. 28A may include 4 megabits (or 1 half megabit) of flash memory and fits snugly into slot S1underneath the controller port holes 1523a,1523bmounted on front panel F. System 52 also supports SD-digicard adapter A shown in FIG. 28B that is compatible stamped-sized, large capacity recording media, SD-memory cards C made by Matsushita. Such SD cards C may offer 64 megabits or more of non-volatile storage. Other cartridge-based memory cards or other devices may also be received by slots S1, S2to interconnect system 50 with other types of internal or external peripheral or other devices.
[0444] Any of the various connectors described herein can be located in the various connector positions shown in FIGS. 22-28B as desired.
Example Detailed Connection Diagram
[0445] FIGS. 12A-12G show an example overall detailed connection diagram of system 50 shown in FIG. 2. FIG. 12G shows how FIGS. 12A-12F can be laid out together to provide an overall system 50 connection diagram. In this particular, non-limiting detailed implementation, the graphics and audio processor 114 is implemented on a single chip named “Flipper” that connects to a main processor 110 named “Gekko” via a 32-bit address bus and a 64-bit data bus. Various other connections as shown in FIG. 12B are used to maintain coordination between main processor 110 and the graphics and audio processor 114. A crystal-controlled 54 Mhz clock generator 1502 provides various clocking signals to the main microprocessor 110 and the graphics and audio processor 114 (see FIG. 12A). A reset circuit 1504 provides a reset signal in response to power on that is applied to the graphics and audio processor 114. The graphics and audio processor 114 supplies reset signals to the main microprocessor 110 (and other system components). The reset signal provided by reset circuit 1504 is also applied to a special initial program load (IPL) chip 1506 that includes an internal boot ROM and a real time clock. In the example embodiment shown, this IPL chip 1506 includes its own clock generator circuit, and is supplied with a battery signal VCC3 (through an RC time constant circuit 1508 coupled to a serial bus connector 1508). Serial bus connector 1508 is also coupled to the graphics and audio processor 114 serial interface 1000 discussed above. The IPL chip 1506 upon power-on reset, serially provides boot program instructions to main processor 110 via graphics and audio processor 114 upon certain power-on conditions being fulfilled. In the example embodiment, this information is provided via a modem bus 1512 that is also coupled to a modem connector 1514. After power-on reset has completed and the initial program load process is done, the boot ROM portion of chip 1506 becomes transparent and is no longer accessible by the graphics and audio processor 114 and/or the main microprocessor 110 but the real time clock function of chip 1506 (which battery B1 of FIG. 14 and the clock generator coupled to chip 1506 maintains even during system 50 power off) allows continual real time tracking of current time and date.
[0446] As also shown in FIG. 12D, various external interface connectors 1516, 1518, 1520 are coupled to the graphics and audio processor 114 EXI interfaces 132, 142 discussed above. Connectors 1514, 1516, 1518, 1520 allow graphics and audio processor 114 and/or main microprocessor 110 to access external peripheral or other devices such as modems, broadband adapters, printers, or virtually any other sort of peripheral or other device.
[0447] As shown in FIGS. 12E and 12F, main memory 112 in this particular implementation is implemented as a pair of 1TSRAM chips 112a,112bmanufactured by MOSYS, Inc. of Santa Clara, Calif. These high-speed memory chips 112a,112bshare a common 21-bit address bus 1530 in the example embodiment. Each memory chip 112a,112bhas its own dedicated 32-bit data bus 1532 and dedicated clocking and other signals as shown. The memory read/write line 1534, the MEMADSOB, line 1536, and the MEMREFSH line 1538 are also shared between these two chips 112a,112bin this example embodiment. Additional expansion could be provided in another implementation if desired.
[0448] FIG. 12C shows example connections with SDRAM 126 including a 13-bit address bus and an 8-bit data bus along with various read, write, clocking and other control signals. In the example embodiment, an expansion connection is provided to allow expansion of the SDRAM 126 to provide additional memory capacity. FIG. 12C also shows example connections between the graphics and audio processor 114 and example analog audio/video connector 1550 and example digital video/audio connector 1552. In the example embodiment, the video encoder and audio codec 120, 122 are implemented in a common single chip package 1554. An audio amplifier 128 amplifies the stereo left and right audio outputs for application to the analog audio/video connector 1550.
Example Detailed Serial (Joybus) Hand Controller Connections
[0449] FIGS. 13A-13bshow an example detailed implementation of a connection between an example serial connector 1510 and the graphics and audio processor 114, and FIG. 14 shows an example detailed connection between the serial connector 1510 and controller connectors 1523 for hand controllers 52 or other devices. Referring to FIG. 13B, the example serial interface described above in connection with FIGS. 8A-8D (including the various serial data buses SIDO0-SIDO3, SIDI0-SIDI3, and the two gun trigger signals GUNTRG0, GUNTRG1) are coupled via transistor-based isolation buffers 1602a-1602dto pins 3, 4, 6, 7, 9 and 10 of a multi-pin serial interface connector 1510. A reset signal received by graphics and audio processor 114 is also coupled to this same serial interface connector 1510 at pin 2 in the example embodiment. In addition, connector 1510 includes a battery input at pin 1 that is applied to the boot ROM/RTC arrangement 134 discussed above. Example connector 1510 also makes available various supply voltages (e.g., 3.3 volts at pin 8 and 5 volts at pine 12) as well as ground potential (e.g., at pins 5 and 11). Referring to FIG. 12, a mating multi-pin connector 1510ais used to connect connector 1510 to the various controller input port connectors 1523a,1523b,1523c,1523d.A battery B1 may be supplied for connection to pin 1, and a reset switch SWI may be connected to pin 2. The various controller connectors 1523 may be wired similarly with pin 3 carrying bi-directional serial data, pin 4 (if applicable—only two connectors 1523a,1523b,provide this capability in the example embodiment) carrying the gun trigger signals, and with power supply and ground voltages being made available as shown.
Example External Interface Connections
[0450] FIGS. 15A-15C show example external interface connections for use in coupling the example external interfaces described above in connection with FIGS. 9A-9E to external interface connectors 1516, 1518, 1520, respectively. In the example embodiment, the external interface connections for EXI0 and EXI1 are virtually identical. As shown in FIGS. 15A and 15B, the external interface buses described above in connection with FIGS. 9A, 9B and 9C are isolated with various isolation circuitry and coupled to respective pins of a multi-pin connector (1516 for the EXI0 bus, 1518 for the EXI1 bus) with pin assignments as follows:
| Pin Number | Signal Identification |
|---|---|
[0451] FIG. 15C shows and example connection between the external interface channel 2 shown in FIG. 9D and example 8-pin connector 1520 having the following pin assignments.
| Pin Number | Signal Identification |
|---|---|
| 1 | 3.3 volts |
| 2 | GND |
| 3 | INT |
| 4 | CLK |
| 5 | DO |
| 6 | DI |
| 7 | CS |
| 8 | Ground |
[0452] The connector arrangements shown in FIGS. 15A-15C allow the graphics and audio processor 114 to communicate with three different peripheral or other devices simultaneously over separate external interface buses. Such external devices can receive data from the graphics and audio processor 114, provide data to the graphics and audio processor, or both. The main microprocessor 110 can access these devices via the graphics and audio processor 114. Any sort of device may be coupled to system 50 via these connectors 15126, 1518 and /or 1520.
Example Modem Connection
[0453] In the example embodiment, system 50 further includes a modem connector 1514 intended to be coupled directly to an internal and/or external modem of conventional design. In the example embodiment, an additional (fourth) external interface bus and associated external interface is provided by graphics and audio processor 114 for communicating with a modem via connector 1514. Devices other than a modem may also be coupled to the modem connector 1514. In the example embodiment, this modem bus is bi-directional with three lines (EXID00, EXI0CLK0 and EXICSB2) being uni-directionally buffered as outputs to the modem connector 1514 and further line EXIOD10 being uni-directionally buffered as an input to the graphics and audio processor 114. In the example embodiment, the uni-directional buffer provided on the EXID10 line is controlled by the graphics and audio processor 114 via the EXI0CSB2 line (the latter line of which is also passed on as a signal to connector 1514). The other buffers in the example embodiment are controlled by an EXTIN signal asserted by a device coupled to the modem connector 1514. Modem connector 1514 may provide the following example pin assignments for a 12-pin connector:
| Pin Number | Signal Identification |
|---|---|
[0454] As shown in FIG. 12, the modem bus and associated interface is shared with the initial program load/boot ROM/real time clock chip 134. This sharing is not a problem since system 50 will generally not be trying to use a modem at the same time that it is booting up.
Example External Digital Video/Audio Connections
[0455] FIGS. 17A and 17B show example connections which connect the graphics and audio processor 114 digital audio and video interface (see FIGS. 10A-11H) to a digital audio/video connector 1552 (FIGS. 17A, 17B) and/or to an analog audio/video connector 1550 (see FIG. 18). As shown in FIGS. 17A and 17B, in the example embodiment, system 50 provides external access to the digital video and audio bus via a digital video and audio connector 1552. In the example embodiment, connector 1552 receives the 8-bit video bus (e.g., at pins 7, 9, 10, 12, 13, 15, 16 and 18) and receives the digital audio serial bus (e.g., at pines 19, 21, 22). In addition, connector 1552 may receive a video selection signal FSEL0 (at pin 1), video clocking signals (e.g., a 27 Mhz signal at pin 6 and a 54 Mhz signal at pin 2) and an additional VICR signal (e.g., at pine 3). Connector 1552 may also make available two different power supply voltages (e.g., a 12 volt power supply voltage at pin 5 and a 3.3 volt power supply voltage at pin 17) in addition to various ground potential connections (e.g., at pins 4, 8, 11, 14, and 20).
[0456] The digital video/audio connector 1552 shown in FIGS. 17A and 17B allows any sort of digital or digitized video and/or audio signal consumer and/or producer to be connected directly to the graphics and audio processor 114 digital video and/or audio buses. For simpler devices such as home television sets and other displays and/or audio output devices, it may be preferable just to connect isolated analog video and audio outputs to such external devices via the analog audio/video connector 1550. In the example embodiment, this analog connector 1550 makes amplified, isolated left and right audio outputs available (e.g., at pins 11 and 12) as well as composite and luminance/chrominance video signals in analog form available (e.g., at pines 7, 8 and 9).
Example SDRAM Expansion
[0457] FIGS. 19A-19D show an example connector 1549 that may be used to expand the capacity of SDRAM memory chip 126 by connecting one or more additional memory chips. In the example embodiment, connector 1549 may comprise a 36-pin connector having the following example pin out configuration:
| Pin Number | Signal Identification |
|---|---|
Example Disk Interface Connector
[0458] FIGS. 20A-20B show an example disk connector 1521 used to connect the graphics and audio processor 114 to a optical disk drive 106. The following pin outs may be used:
| Pin Number | Signal Identification |
|---|---|
Example Power Supply Connector
[0459] In the example embodiment, system 50 may also include a power supply connector 1700 used to connect power to power all of the components within the system. An example power supply connector is shown in FIG. 4 including the following example pin outs:
| Pin Number | Signal Identification |
|---|---|
| Pin Number | Signal Identification |
|---|---|
| 13 | 1.55 volts DC |
| 14 | 1.55 volts DC |
| 15 | 1.55 volts DC |
| 16 | Ground |
| 17 | Ground |
| 18 | Ground |
| 19 | Thermo detect |
| 20 | 12 volts DC |
| 21 | 5 volts DC |
| 22 | 5 volts DC |
[0460] In the example embodiment, a temperature compensation chip 1702 is connected to connector 17 pin 19.
Other Example Compatible Implementations
[0461] Certain of the above-described system components 50 could be implemented as other than the home video game console configuration described above. For example, one could run graphics application or other software written for system 50 on a platform with a different configuration that emulates system 50 or is otherwise compativle with it. If the other platform can successfully emulate, simulate and/or provide some or all of the hardware and software resources of system 50, then the other platform will be able to successfully execute the software.
[0462] As one example, and emulator may provide a hardware and/or software configuration (platform) that is different from the hardware and/or software configuration (platform) of system 50. The emulator system might include software and/or hardware components that emulate or simulate some or all of hardware and/or software components of the system for which the application software was written. For example, the emulator system could comprise a general purpose digital computer such as a personal computer, which executes a software emulator program that simulates the hardware and/or firmware of system 50.
[0463] Some general purpose digital computers (e.g., IBM or MacIntosh personal computers and compatibles) are now equipped with 3D graphics cards that provide 3D graphics pipelines compliant with DirectX or other standard 3D graphics command APIs. They may also be equipped with stereophonic sound cards that provide high quality stereophonic sound based on a standard set of sound commands. Such multimedia-hardware-equipped personal computers running emulator software may have sufficient performance to approximate the graphics and sound performance of system 50. Emulator software controls the hardware resources on the personal computer platform to simulate the processing, 3D graphics, sound, peripheral and other capabilities of the home video game console platform for which the game programmer wrote the game software.
[0464] FIG. 29A illustrates an example overall emulation process using a host platform 1201, an emulator component 1303, and a game software executable binary image provided on a storage medium 62. Host 1201 may be a general or special purpose digital computing device such as, for example, a personal computer, a video game console, or any other platform with sufficient computing power. Emulator 1303 may be software and/or hardware that runs on host platform 1201, and provides a real-time conversion of commands, data and other information from storage medium 62 into a form that can be processed by host 1201. For example, emulator 1303 fetches “source” binary-image program instructions intended for execution by system 50 from storage medium 62 and converts these program instructions to a target format that can be executed or otherwise processed by host 1201.
[0465] As one example, in the case where the software is written for execution on a platform using an IBM PowerPC or other specific processor and the host 1201 is a personal computer using a different (e.g., Intel) processor, emulator 1203 fetches one or a sequence of binary-image program instructions from storage medium 1305 and converts these program instructions to one or more equivalent Intel binary-image program instructions. The emulator 1203 also fetches and/or generates graphics commands and audio commands intended for processing by the graphics and audio processor 114, and converts these commands into a format or formats that can be processed by hardware and/or software graphics and audio processing resources available on host 1201. As one example, emulator 1303 may convert these commands into commands that can be processed by specific graphics and/or or sound hardware of the host 1201 (e.g., using standard DirectX, OpenGL and/or sound APIs).
[0466] An emulator 1303 used to provide some or all of the features of the video game system described above may also be provided with a graphic user interface (GUI) that simplifies or automates the selection of various options and screen modes for games run using the emulator. In one example, such an emulator 1303 may further include enhanced functionality as compared with the host platform for which the software was originally intended.
[0467] FIG. 29B illustrates an emulation host system 1201 suitable for use with emulator 1303. System 1201 includes a processing unit 1203 and a system memory 1205. A system bus 1207 couples various system components including system memory 1205 to processing unit 1203. System bus 1207 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. System memory 1207 includes read only memory (ROM) 1252 and random access memory (RAM) 1254. A basic input/output system (BIOS) 1256, containing the basic routines that help to transfer information between elements within personal computer system 1201, such as during start-up, is stored in the ROM 1252. System 1201 further includes various drives and associated computer-readable media. A hard disk drive 1209 reads from and writes to a (typically fixed) magnetic hard disk 1211. An additional (possible optional) magnetic disk drive 1213 reads from and writes to a removable “floppy” or other magnetic disk 1215. An optical disk drive 1217 reads from and, in some configurations, writes to a removable optical disk 1219 such as a CD ROM or other optical media. Hard disk drive 1209 and optical disk drive 1217 are connected to system bus 1207 by a hard disk drive interface 1221 and an optical drive interface 1225, respectively. The drives and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, game programs and other data for personal computer system 1201. In other configurations, other types of computer-readable media that can store data that is accessible by a computer (e.g., magnetic cassettes, flash memory cards, digital video disks, Bernoulli cartridges, random access memories (RAMs), read only memories (ROMs) and the like) may also be used.
[0468] A number of program modules including emulator 1303 may be stored on the hard disk 1211, removable magnetic disk 1215, optical disk 1219 and/or the ROM 1252 and/or the RAM 1254 of system memory 1205. Such program modules may include an operating system providing graphics and sound APIs, one or more application programs, other program modules, program data and game data. A user may enter commands and information into personal computer system 1201 through input devices such as a keyboard 1227, pointing device 1229, microphones, joysticks, game controllers, satellite dishes, scanners, or the like. These and other input devices can be connected to processing unit 1203 through a serial port interface 1231 that is coupled to system bus 1207, but may be connected by other interfaces, such as a parallel port, game port Fire wire bus or a universal serial bus (USB). A monitor 1233 or other type of display device is also connected to system bus 1207 via an interface, such as a video adapter 1235.
[0469] System 1201 may also include a modem 1154 or other network interface means for establishing communications over a network 1152 such as the Internet. Modem 1154, which may be internal or external, is connected to system bus 123 via serial port interface 1231. A network interface 1156 may also be provided for allowing system 1201 to communicate with a remote computing device 1150 (e.g., another system 1201) via a local area network 1158 (or such communication may be via wide area network 1152 or other communications path such as dial-up or other communications means). System 1201 will typically include other peripheral output devices, such as printers and other standard peripheral devices.
[0470] In one example, video adapter 1235 may include a 3D graphics pipeline chip set providing fast 3D graphics rendering in response to 3D graphics commands issued based on a standard 3D graphics application programmer interface such as Microsoft's DirectX 7.0 or other version. A set of stereo loudspeakers 1237 is also connected to system bus 1207 via a sound generating interface such as a conventional “sound card” providing hardware and embedded software support for generating high quality stereophonic sound based on sound commands provided by bus 1207. These hardware capabilities allow system 1201 to provide sufficient graphics and sound speed performance to play software stored in storage medium 1305.
[0471] While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements.
Claims
What is claimed is:
1. A gaming peripheral configured for connection to one of a plurality of interfaces of a home video game system of a type which provides external access to a first high potential terminal, a first ground terminal for the first high potential terminal, a second high potential terminal, a second ground terminal for the second high potential terminal, and four other ground terminals, and to a serial data line, wherein one or more of the interfaces also provides external access to a latch signal line and wherein the serial data lines and the latch signal lines of the interfaces connect via isolation buffers to a serial bus coupled to a graphics and audio processor of the home video game system, said gaming peripheral including:
at least one electrical component; and
multi-element electrical connector coupled to the at least electrical component, wherein the multi-element connector comprises:
a first connecting element that connects, in use, to the first high potential terminal,
a second connecting element that connects, in use, to the first group terminal,
a third connecting element that connects, in use, to the second high potential terminal,
a fourth connecting element that connects, in use, to the second ground terminal
a fifth connecting element that connects, in use, to the serial data line,
a sixth connecting element that connects, in use, to the latch signal line, and
seventh, eighth, ninth and tenth connecting elements that respectively connect, in use, to the four ground terminals.
2. The gaming peripheral according to claim 1, wherein the first high potential terminal is a 5 volt terminal and the second high potential terminal is a 3.3 volt terminal.
3. A gaming communication device configured for connection to an interface of a home video game system of a type which provides external access to a first high potential terminal, a first ground terminal coupled to the first high potential terminal, a second high potential terminal, and a second ground terminal coupled to the second high potential terminal and to a bus connected to a graphics and audio processor of the home video game system which includes a device insertion status signal line, a data output line having a first uni-directional output buffer controlled by a signal on the device insertion status signal line, a clock signal line having a second uni-directional output buffer controlled by the signal on the device insertion status signal line, a chip select signal line having a third uni-directional output buffer controlled by the signal on the device insertion status signal line, a data input line having a uni-directional input buffer controlled by a signal on the chip select signal line, an interrupt signal line, said gaming communication device comprising:
a communication circuit; and
a multi-element electrical connector coupled to the communication circuit, wherein the multi-element connector comprises:
a first connecting element that connects, in use, to the device insertion signal status line,
a second connecting element that connects, in use, to the data output line,
a third connecting element that connects, in use, to the clock signal line,
a fourth connecting element that connects, in use, to the chip select signal line,
a fifth connecting element that connects, in use, to the data input line,
a sixth connecting element that connects, in use, to the interrupt signal line,
a seventh connecting element that connects, in use, to the first high potential terminal,
an eighth connecting element that connects, in use, to the first ground potential terminal,
a ninth connecting element that connects, in use, to the second high potential terminal,
a tenth connecting element that connects, in use, to the second high potential terminal,
an eleventh connecting element that connects, in use, to the second ground terminal, and
a twelfth connecting element that connects, in use, to the second ground terminal,
wherein the gaming communication device supplies an insertion status signal to the insertion signal status line via the first connecting element to control the first, second and third uni-directional buffers.
4. The gaming communication device according to claim 3, wherein the communication circuit comprises a modem.
5. The gaming communication device according to claim 3, wherein the communication circuit comprises a network interface.
6. The gaming communication device according to claim 3, wherein the bus is shared with an initial program load/boot ROM/real-time clock chip.
7. The gaming communication device according to claim 3, further comprising:
a box-shaped housing containing the communication circuit and which is configured to fit in a recess formed in the home video game system.
8. The gaming communication device according to claim 3, further comprising:
a box-shaped housing containing the communication circuit and configured to fit in a recess formed in a bottom surface of the home video game system.
9. The gaming communication device according to claim 3, further comprising:
a housing containing the communication circuit and configured to fit in a recess formed in a surface of the home video game system so that when the housing is inserted into the recess the housing is substantially flush with the surface of the home video game system in which the recess is formed.
10. The gaming communication device according to claim 3, further comprising:
a housing containing the communication circuit and configured to fit in a recess formed in a bottom surface of the home video game system so that when the housing is inserted into the recess the housing is substantially flush with the bottom surface of the home video game system.
11. The gaming communication device according to claim 3, wherein the communication circuit is adapted for connection to a telecommunications network.
12. The gaming communication device according to claim 3, wherein the first high potential terminal is a 12 volt terminal and the second high potential terminal is a 3.3 volt terminal.
13. A gaming communication device configured for connection to an interface of a home video game system provided in a recess formed in a surface of the home video game system, the interface being of a type which provides external access to a first high potential terminal, a first ground terminal coupled to the first high potential terminal, a second high potential terminal, and a second ground terminal coupled to the second high potential terminal and to a bus connected to a graphics and audio processor of the home video game system which includes a device insertion status signal line, a data output line having a first uni-directional output buffer controlled by a signal on the device insertion status signal line, a clock signal line having a second uni-directional output buffer controlled by the signal on the device insertion status signal line, a chip select signal line having a third uni-directional output buffer controlled by the signal on the device insertion status signal line, a data input line having a uni-directional input buffer controlled by a signal on the chip select signal line, an interrupt signal line, said gaming communication device comprising:
a communication circuit;
a housing containing the communication circuit and configured to be disposed in the recess formed in the home video game system; and
a multi-element electrical connector coupled to the communication circuit, wherein the multi-element connector comprises:
a first connecting element that connects, in use, to the device insertion signal status line,
a second connecting element that connects, in use, to the data output line,
a third connecting element that connects, in use, to the clock signal line,
a fourth connecting element that connects, in use, to the chip select signal line,
a fifth connecting element that connects, in use, to the data input line, and
a sixth connecting element that connects, in use, to the interrupt signal line,
wherein the gaming communication device supplies an insertion status signal to the insertion signal status line via the first connecting element to control the first, second and third uni-directional buffers.
14. The gaming communication device according to claim 13, wherein the housing is configured so that when the housing is inserted into the recess the housing is substantially flush with the surface of the home video game system in which the recess is formed.
15. The gaming communication device according to claim 13, wherein the recess is formed in the bottom surface of the home video game system.
16. The gaming communication device according to claim 13, wherein the housing is configured so that when the housing is inserted into the recess the housing is substantially flush with the bottom surface of the home video game system.
17. A gaming peripheral device configured for connection to an interface of a home video game system, wherein the interface provides access to a processing system of the home video game system and comprises a data bus, a data direction signal line for a direction signal that controls the direction of data on the data bus, a host strobe signal line for a host strobe signal that qualifies output data on the data bus, a device strobe signal line for a device strobe signal that qualifies input data on the data bus, an error signal line for an error signal indicative of a gaming peripheral device error, a break signal line for a break signal that interrupts a command for the gaming peripheral device, a position signal line for a position signal indicative of a position of a mechanical component of the gaming peripheral device and a reset signal line for a reset signal for the gaming peripheral device, the gaming peripheral device comprising:
at least one electrical component; and
a multi-element electrical connector coupled to the at least one electrical component, wherein the multi-element electrical connector comprises:
first through eighth connecting elements that connect, in use, to the data bus;
a ninth connecting element that connects, in use, to the data direction signal line;
a tenth connecting element that connects, in use, to the host strobe signal line;
an eleventh connecting element that connects, in use, to the device strobe signal line;
a twelfth connecting element that connects, in use, to the error signal line,
a thirteenth connecting element that connects, in use, to the break signal line;
a fourteenth connecting element that connects, in use, to the position signal line; and
a fifteenth connecting element that connects, in use, to the reset signal line.
18. The gaming peripheral device according to claim 17, wherein the at least one electrical component comprises a mass storage access device.
19. The gaming peripheral device according to claim 18, wherein the mass storage access device is responsive to direct memory access commands.
20. The gaming peripheral device according to claim 18, wherein, when the processing system is writing output data to the mass storage access device, the output data is latched on a rising edge of the host strobe signal.
21. The gaming peripheral device according to claim 18, wherein, when the processing system is reading input data from the mass storage access device, the input data is latched on a rising edge of the host strobe signal.
22. The gaming peripheral device according to claim 18, wherein the position signal indicates the position of a cover of the mass storage access device.
23. The gaming peripheral device according to claim 18, wherein the mass storage access device asserts the error signal at the end of a command transfer if there is a mass storage access device error.
24. The gaming peripheral device according to claim 18, wherein the mass storage access device asserts the error signal at the end of a data transfer if there is a mass storage access device error.
25. The gaming peripheral device according to claim 18, wherein the mass storage access device asserts the error signal between blocks of a direct memory access transfer if there is a mass storage access device error.
26. The gaming peripheral device according to claim 17, wherein the at least one electrical component comprises an optical disk drive.
27. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises a 32-bit interface status register.
28. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises three 32-bit command buffer registers.
29. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises a 32-bit direct memory access (DMA) address register.
30. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises a 32-bit direct memory access (DMA) transfer length register.
31. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises a 32-bit control register.
32. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises a 32-bit immediate data buffer register.
33. The gaming peripheral device according to claim 17, wherein the interface of the home video game system further comprises a 32-bit configuration register.
34. A gaming peripheral device configured to connect to an interface of a home video game system, wherein the interface provides access to a processing system of the home video game system and comprises a high level potential terminal, an input signal fine normally at a low level state, serial data out line, a serial data in line, a select signal line, a clocking signal line, and an interrupt signal line, and wherein the home video game system detects that the gaming peripheral device is connected to the interface when the potential of the input signal line becomes a high level state, the gaming peripheral device comprising:
at least one electrical component; and
a multi-element electrical connector coupled to the at least one electrical component, wherein the multi-element electrical connector comprises:
a first connecting element that connects, in use, to the serial data out line;
a second connecting element that connects, in use, to the serial data in line;
a third connecting element that connects, in use, to the select signal line;
a fourth connecting element that connects, in use, to the locking signal line;
a fifth connecting element that connects, in use, to the interrupt signal line;
a sixth connecting element that connects, in use, to the input signal line; and
a seventh connecting element that connects, in use, to the high level potential terminal, wherein
the input signal line is supplied with a signal from the gaining peripheral device having the high level state when the gaming peripheral device is connected to the interface of the home video game system.
35. The gaming peripheral device according to claim 34, wherein the multi-element electrical connector consists of twelve connecting elements.
36. The gaming peripheral device according to claim 34, wherein the low level potential is a ground potential and the high level potential is +3.3 V.
37. The gaming peripheral device according to claim 34, wherein the at least one electrical component comprises a flash memory.
38. The gaming peripheral device according to claim 34, wherein the at least one electrical component comprises a non-volatile memory.
39. The gaming peripheral device according to claim 34, wherein the connecting elements comprise male connecting elements.
40. The gaming peripheral device according to claim 34, wherein the connecting elements comprise pins.
41. The gaming peripheral device according to claim 34, wherein the processing system of the home video game system sends game-related data to the at least one electrical component via the interface.
42. The gaming peripheral device according to claim 34, wherein the processing system of the home video game system reads game-related data from the at least one electrical component via the interface.
43. The gaming peripheral device according to claim 34, wherein the at least one electrical component is contained in a cartridge adapted for insertion into a slot formed in a housing of the home video game system.
44. A memory device configured to connect to an interface of a home video game system, wherein the interface provides access to a processing system of the home video game system and comprises a first high level potential terminal, a second high level potential terminal, a low level potential terminal, an input signal line normally at a low level state, a serial data out line, a serial data in line, a select signal line, a clocking signal line, and an interrupt signal line, and wherein the home video game system detects that the memory device is connected to the interface when the potential of the input signal line becomes a high level state, the memory device comprising:
a memory medium; amid
an electrical connector coupled to the memory medium, wherein the connector comprises:
a first connecting element that connects, in use, to the serial data out line;
a second connecting element that connects, in use, to the serial data in line;
a third connecting element that connects, in use, to the select signal line;
a fourth connecting element that connects, in use, to the clocking signal line;
a fifth connecting element that connects, in use, to the interrupt signal line:
a sixth connecting element that connects, in use, to the interrupt signal line:
seventh, eighth and ninth connecting elements that each connects, in use, to the first high level potential terminal;
a tenth connecting element that connects, in use, to the second high level potential terminal; and
eleventh and twelfth connecting elements that each connects, in use, to the low level potential terminal,
wherein the input signal line is supplied with a signal from the gaming peripheral device having the high level state when the gaming peripheral device is connected to the interface of the home video game system.
45. The memory device according to claim 44, wherein the low level potential is a ground potential, the first high level potential is +3.3 V and the second high level potential is +5 V.
46. The memory device according to claim 44, wherein the memory medium comprises a flash memory.
47. The memory device according to claim 44, wherein the memory medium comprises a non-volatile memory.
48. The memory device according to claim 44, wherein the connecting elements comprise male connecting elements.
49. The memory device according to claim 44, wherein the connecting elements comprise pins.
50. The memory device according to claim 44, wherein the processing system of the home video game system writes game-related data to the memory medium via the interface.
51. The memory device according to claim 44, wherein the processing system of the home video game system reads game-related data from the memory medium via the interface.
52. The memory device according to claim 44, wherein the memory medium is contained in a cartridge adapted for insertion into a slot formed in a housing of the home video game system.
53. The memory device according to claim 44, wherein the interface of the home video game system further comprises at least one channel parameter register.
54. The memory device according to claim 44, wherein the interface of the home video game system further comprises at least one direct memory access (DMA) address register.
55. The memory device according to claim 44, wherein the interface of the home video game system further comprises at least one direct memory access (DMA) transfer length register.
56. The memory device according to claim 44, wherein the interface of the home video game system further comprises at least one control register.
57. The memory device according to claim 44, wherein the interface of the home video game system further comprises at least one data register.
Patent Citations (168)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3369177(A) | 1968-02-01 | Graham et al. | Applicant |
| US4167019(A) | 1979-09-01 | Shepperd | Applicant |
| US4278972(A) | 1981-07-01 | Wozniak | Applicant |
| US4296476(A) | 1981-10-01 | Mayer et al. | Applicant |
| US4324401(A) | 1982-04-01 | Stubben et al. | Applicant |
| US4388620(A) | 1983-06-01 | Sherman | Applicant |
| US4407298(A) | 1983-10-01 | Lentz et al. | Applicant |
| US4425559(A) | 1984-01-01 | Sherman | Applicant |
| US4454594(A) | 1984-06-01 | Heffron et al. | Applicant |
| US4462076(A) | 1984-07-01 | Smith, III | Applicant |
| US4562308(A) | 1985-12-01 | Kopetzky et al. | Applicant |
| US4567516(A) | 1986-01-01 | Scherer et al. | Applicant |
| US4570233(A) | 1986-02-01 | Yan et al. | Applicant |
| US4589089(A) | 1986-05-01 | Frederiksen | Applicant |
| US4592012(A) | 1986-05-01 | Braun | Applicant |
| US4658247(A) | 1987-04-01 | Gharachorloo | Applicant |
| US4725831(A) | 1988-02-01 | Coleman | Applicant |
| US4799635(A) | 1989-01-01 | Nakagawa | Applicant |
| US4829295(A) | 1989-05-01 | Hiroyuki | Applicant |
| US4837488(A) | 1989-06-01 | Donahue | Applicant |
| US4850591(A) | 1989-07-01 | Takezawa et al. | Applicant |
| US4862392(A) | 1989-08-01 | Steiner | Applicant |
| US4866637(A) | 1989-09-01 | Gonzalez-Lopez et al. | Applicant |
| US4901064(A) | 1990-02-01 | Deering | Applicant |
| US4914729(A) | 1990-04-01 | Omori et al. | Applicant |
| US4945500(A) | 1990-07-01 | Deering | Applicant |
| US4972470(A) | 1990-11-01 | Farago | Applicant |
| US4976429(A) | 1990-12-01 | Nagel | Applicant |
| US5004232(A) | 1991-04-01 | Wong et al. | Applicant |
| US5049863(A) | 1991-09-01 | Oka | Applicant |
| US5050041(A) | 1991-09-01 | Shafi | Applicant |
| US5091832(A) | 1992-02-01 | Tortola et al. | Applicant |
| US5136664(A) | 1992-08-01 | Bersack et al. | Applicant |
| US5155768(A) | 1992-10-01 | Matsuhara | Applicant |
| US5170468(A) | 1992-12-01 | Shah et al. | Applicant |
| USRE34161(E) | 1993-01-01 | Nakagawa et al. | Applicant |
| US5213327(A) | 1993-05-01 | Kitaue | Applicant |
| US5230059(A) | 1993-07-01 | Nielsen et al. | Applicant |
| US5239540(A) | 1993-08-01 | Rovira et al. | Applicant |
| US5245320(A) | 1993-09-01 | Bouton | Applicant |
| US5268669(A) | 1993-12-01 | Roskowski | Applicant |
| US5389006(A) | 1995-02-01 | Noschese | Applicant |
| US5392385(A) | 1995-02-01 | Evangelisti et al. | Applicant |
| US5392393(A) | 1995-02-01 | Deering | Applicant |
| US5421028(A) | 1995-05-01 | Swanson | Applicant |
| US5421590(A) | 1995-06-01 | Robbins | Applicant |
| US5428355(A) | 1995-06-01 | Jondrow et al. | Applicant |
| US5457775(A) | 1995-10-01 | Johnson, Jr. et al. | Applicant |
| US5459487(A) | 1995-10-01 | Bouton | Applicant |
| US5504917(A) | 1996-04-01 | Austin | Applicant |
| US5509811(A) | 1996-04-01 | Homic | Applicant |
| US5513302(A) | 1996-04-01 | Tsai | Applicant |
| US5546050(A) | 1996-08-01 | Florian et al. | Applicant |
| US5593350(A) | 1997-01-01 | Bouton et al. | Applicant |
| US5594854(A) | 1997-01-01 | Baldwin et al. | Applicant |
| US5599231(A) | 1997-02-01 | Hibino et al. | Applicant |
| US5599232(A) | 1997-02-01 | Darling | Applicant |
| US5607157(A) | 1997-03-01 | Nagashima | Applicant |
| US5608424(A) | 1997-03-01 | Takahashi et al. | Applicant |
| US5615344(A) | 1997-03-01 | Corder | Applicant |
| US5628686(A) | 1997-05-01 | Svancarek et al. | Applicant |
| US5630170(A) | 1997-05-01 | Koizumi et al. | Applicant |
| US5630174(A) | 1997-05-01 | Stone, III et al. | Applicant |
| US5644790(A) | 1997-07-01 | Li et al. | Applicant |
| US5645277(A) | 1997-07-01 | Cheng | Applicant |
| US5655966(A) | 1997-08-01 | Werdin, Jr. et al. | Applicant |
| US5680534(A) | 1997-10-01 | Yamato et al. | Applicant |
| US5687357(A) | 1997-11-01 | Priem | Applicant |
| US5696912(A) | 1997-12-01 | Bicevskis et al. | Applicant |
| US5701444(A) | 1997-12-01 | Baldwin | Applicant |
| US5708799(A) | 1998-01-01 | Gafken et al. | Applicant |
| US5717428(A) | 1998-02-01 | Barrus et al. | Applicant |
| US5721947(A) | 1998-02-01 | Priem et al. | Applicant |
| US5727192(A) | 1998-03-01 | Baldwin | Applicant |
| US5748756(A) | 1998-05-01 | Leal et al. | Applicant |
| US5754890(A) | 1998-05-01 | Holmdahl et al. | Applicant |
| US5758182(A) | 1998-05-01 | Rosenthal et al. | Applicant |
| US5764243(A) | 1998-06-01 | Baldwin | Applicant |
| US5768626(A) | 1998-06-01 | Munson et al. | Applicant |
| US5768629(A) | 1998-06-01 | Wise et al. | Applicant |
| US5774133(A) | 1998-06-01 | Neave et al. | Applicant |
| US5777629(A) | 1998-07-01 | Baldwin | Applicant |
| US5784064(A) | 1998-07-01 | Penna et al. | Applicant |
| US5798770(A) | 1998-08-01 | Baldwin | Applicant |
| US5801706(A) | 1998-09-01 | Fujita et al. | Applicant |
| US5801716(A) | 1998-09-01 | Silverbrook | Applicant |
| US5805868(A) | 1998-09-01 | Murphy | Applicant |
| US5815166(A) | 1998-09-01 | Baldwin | Applicant |
| US5816921(A) | 1998-10-01 | Hosokawa | Applicant |
| US5821949(A) | 1998-10-01 | Deering | Applicant |
| US5832244(A) | 1998-11-01 | Jolley et al. | Applicant |
| US5867166(A) | 1999-02-01 | Myhrvold et al. | Applicant |
| US5870027(A) | 1999-02-01 | Ho | Applicant |
| US5872999(A) | 1999-02-01 | Koizumi et al. | Applicant |
| US5874969(A) | 1999-02-01 | Storm et al. | Applicant |
| US5886686(A) | 1999-03-01 | Chen | Applicant |
| US5892974(A) | 1999-04-01 | Koizumi et al. | Applicant |
| US5917496(A) | 1999-06-01 | Fujita et al. | Applicant |
| US5920326(A) | 1999-07-01 | Rentschler et al. | Applicant |
| US5935224(A) | 1999-08-01 | Svancarek et al. | Applicant |
| US5940086(A) | 1999-08-01 | Rentschler et al. | Applicant |
| US5949424(A) | 1999-09-01 | Cabral et al. | Applicant |
| US5949440(A) | 1999-09-01 | Krech, Jr. et al. | Applicant |
| US5969726(A) | 1999-10-01 | Rentschler et al. | Applicant |
| US5991546(A) | 1999-11-01 | Chan et al. | Applicant |
| US5996033(A) | 1999-11-01 | Chiu-Hao | Applicant |
| US5999196(A) | 1999-12-01 | Storm et al. | Applicant |
| US6002409(A) | 1999-12-01 | Harkin | Applicant |
| US6006295(A) | 1999-12-01 | Jones et al. | Applicant |
| US6018765(A) | 2000-01-01 | Durana et al. | Applicant |
| US6023738(A) | 2000-02-01 | Priem et al. | Applicant |
| US6025853(A) | 2000-02-01 | Baldwin | Applicant |
| US6028611(A) | 2000-02-01 | Anderson et al. | Applicant |
| US6033309(A) | 2000-03-01 | Couch et al. | Applicant |
| US6037949(A) | 2000-03-01 | DeRose et al. | Applicant |
| US6057852(A) | 2000-05-01 | Krech, Jr. | Applicant |
| US6067411(A) | 2000-05-01 | Poimboeuf et al. | Applicant |
| US6071191(A) | 2000-06-01 | Takeda et al. | Applicant |
| US6076119(A) | 2000-06-01 | Maemura et al. | Applicant |
| US6092124(A) | 2000-07-01 | Priem et al. | Applicant |
| US6098130(A) | 2000-08-01 | Wang | Applicant |
| US6101560(A) | 2000-08-01 | Gulick | Applicant |
| US6131134(A) | 2000-10-01 | Huang et al. | Applicant |
| US6147673(A) | 2000-11-01 | Zarek | Applicant |
| US6166748(A) | 2000-12-01 | Van Hook et al. | Applicant |
| US6171190(B1) | 2001-01-01 | Thanasack et al. | Applicant |
| US6173367(B1) | 2001-01-01 | Aleksic et al. | Applicant |
| US6181352(B1) | 2001-01-01 | Kirk et al. | Applicant |
| US6190257(B1) | 2001-02-01 | Takeda et al. | Applicant |
| US6193609(B1) | 2001-02-01 | D'Achard Van Enschut | Applicant |
| US6198488(B1) | 2001-03-01 | Lindholm et al. | Applicant |
| US6200253(B1) | 2001-03-01 | Nishiumi et al. | Applicant |
| US6213878(B1) | 2001-04-01 | Setsumasa et al. | Applicant |
| US6217351(B1) | 2001-04-01 | Fung et al. | Applicant |
| US6226012(B1) | 2001-05-01 | Priem et al. | Applicant |
| US6230232(B1) | 2001-05-01 | Nishiumi et al. | Applicant |
| US6238291(B1) | 2001-05-01 | Fujimoto et al. | Applicant |
| US6247075(B1) | 2001-06-01 | Wang et al. | Applicant |
| US6263392(B1) | 2001-07-01 | McCauley | Applicant |
| US6264558(B1) | 2001-07-01 | Nishiumi et al. | Applicant |
| US6279906(B1) | 2001-08-01 | Sanderson et al. | Examiner |
| US6307880(B1) | 2001-10-01 | Evans et al. | Applicant |
| US6334160(B1) | 2001-12-01 | Emmert et al. | Applicant |
| US2001/0006391(A1) | 2001-07-01 | Sawano et al. | Applicant |
| US2001/0008847(A1) | 2001-07-01 | Miyamoto et al. | Applicant |
| CA2070934 | 1993-12-01 | Applicant | |
| EP780771 | 1997-06-01 | Applicant | |
| EP1074945 | 2001-02-01 | Applicant | |
| EP1075146 | 2001-02-01 | Applicant | |
| EP1081649 | 2001-03-01 | Applicant | |
| JP11053580 | 1999-02-01 | Applicant | |
| JP11076614 | 1999-03-01 | Applicant | |
| JP11161819 | 1999-06-01 | Applicant | |
| JP11203500 | 1999-07-01 | Applicant | |
| JP11226257 | 1999-08-01 | Applicant | |
| JP11259671 | 1999-09-01 | Applicant | |
| JP11259678 | 1999-09-01 | Applicant | |
| JP2000-66985 | 2000-03-01 | Applicant | |
| JP2000-92390 | 2000-03-01 | Applicant | |
| JP2000-132704 | 2000-05-01 | Applicant | |
| JP2000-132706 | 2000-05-01 | Applicant | |
| JP2000-149053 | 2000-05-01 | Applicant | |
| JP2000-156875 | 2000-06-01 | Applicant | |
| JP2000-182077 | 2000-06-01 | Applicant | |
| JP2000-207582 | 2000-07-01 | Applicant | |
| JP2000-215325 | 2000-08-01 | Applicant | |
| WO8809573 | 1990-06-01 | Applicant | |
| WO94/10641 | 1994-05-01 | Applicant |
Non-Patent Literature (101)
- Website http://www.repairfaq.org/REPAIR/F_Pinouts.html entitled “Pinouts for various connectors in Real Life(tm)”, p. 1 of 3, dated May 20, 1997, author not established.Applicant
- Christy J., Website http://www.repairfaq.org/REPAIR/F_SNES.html entitled “Super Nintendo Entertainment System: pinouts & protocol, Mar. 26, 1996, 5 pages by way of link ″2.2) SNES” in the website above.Applicant
- 68HC705V8 Specification Rev. 2.1 (General Release), MCU System Design Group, Oak Hill, Texas, Aug. 12, 1994, pp. iii-xi, xiii, and 89-96.Applicant
- HCO8—68HC08AS32, Advance Information Rev. 3.0, Motorola, printed out Jul. 24, 2001, pp. 2-27, and 234-308.Applicant
- Photograph of Sony PlayStation II System.Applicant
- Photograph of Sega Dreamcast System.Applicant
- Photograph of Nintendo 64 System.Applicant
- Whitepaper: 3D Graphics Demystified, Nov. 11, 1999, www.nvidia.com.Applicant
- Whitepaper: “Z Buffering, Interpolation and More W-Buffering”, Doug Rogers, Jan. 31, 2000, www.nvidia.com.Applicant
- Whitepaper: Using GL_vertex_array and GL_NV_fence, posted Aug. 1, 2000, www.nvidia.com.Applicant
- Whitepaper: Anisotropic Texture Filtering in OpenGL, posted Jul. 17, 2000, www.nvidia.com.Applicant
- Whitepaper: Mapping Texels to Pixels in D3D, posted Apr. 5, 2000, www.nvidia.com.Applicant
- Whitepaper: Guard Band Clipping, posted Jan. 31, 2000, www.nvidia.com.Applicant
- Whitepaper: Cube Environment Mapping, posted Jan. 14, 2000, www.nvidia.com.Applicant
- Whitepaper: Color Key in D3D, posted Jan. 11, 2000, www.nvidia.com.Applicant
- Whitepaper: Vertex Blending Under DX7 for the GeForce 256, Jan. 5, 2000, www.nvidia.com.Applicant
- Whitepaper: Optimizing Direct3D for the GeForce 256, Jan. 3, 2000, www.nvidia.com.Applicant
- Whitepaper: Dot Product Texture Blending, Dec. 3, 1999, www.nvidia.com.Applicant
- Whitepaper: Technical Brief: AGP 4X with Fast Writes, Nov. 10, 1999, www.nvidia.com.Applicant
- Technical Brief: Transform and Lighting, Nov. 10, 1999, www.nvidia.com.Applicant
- Technical Brief: What's New With Microsoft DirectX7, posted Nov. 10, 1999, www.nvidia.com.Applicant
- Mitchell et al., “Multitexturing in DirectX6”, Game Developer, Sep. 1998, www.gdmag.com.Applicant
- VisionTek, “GeForce2 GS Graphics Processing Unit”, ©2000 www.visiontek.com.Applicant
- Jim Bushnell et al. “Advanced Multitexture Effects With Direct3D and OpenGL”, Pyramid Peak Design & ATI Research, Inc., GameDevelopers Conference, ©1999.Applicant
- Sony PlayStation II Instruction Manual, Sony Computer Entertainment Inc., ©2000.Applicant
- Stand and Be Judged, Next Generation, May 2000.Applicant
- PlayStation II: Hardware Heaven or Hell?, Next Generation, Jan. 2000.Applicant
- Chris Charla, “Play Station II: The Latest News”, Next Generation, Sep. 1999.Applicant
- “First PlayStation II Gameplay Screens Revealed!”, Next Generation, Sep. 1999.Applicant
- Game Enthusiast Online Highlights, Mar. 18, 1999.Applicant
- Game Enthusiast Online Highlights, Mar. 19, 1999.Applicant
- Game Enthusiast Online Highlights, Mar. 17, 1999.Applicant
- Game Enthusiast Online Highlights, Oct. 20, 1999.Applicant
- Joel Easley, “PlayStation II Revealed”, Game Week, Sep. 29, 1999.Applicant
- Inside Sony's Next Generation Playstation, ©1999.Applicant
- Press Releases, Mar. 18, 1999.Applicant
- Chris Johnson, “PlayStation Part Deux”, Press Start, ©1999.Applicant
- Nikkei Shimbun, “Sony Making SME, Chemical and SPT into Wholly-Owned Subsidiaries”, Mar. 9, 1999.Applicant
- AM News: Japanese Developers Not All Sold on PS2, Next Generation, Mar. 16, 1999.Applicant
- Sony To Turn PlayStation Maker Into Wholly Owned Unit—Nikkei, Dow Jones News Service, Mar. 8, 1999.Applicant
- Yumiko Ono, Sony Antes Up Its Chips in Bet On New Game System, Dow Jones News Service, Mar. 4, 1999.Applicant
- MacWeek.Com Gets Inside Story on Connectix VGS for Windows: Controversial Emulator of Sony PlayStation Games Cureently Available for Macs Only, Business Wire, Mar. 12, 1999.Applicant
- “DexDrive Bridges Gap”, The Tampa Tribune, Mar. 12, 1999.Applicant
- A Microprocessor With a 128b CPU, 10 Floating-Point MAC's, 4 Floating-Point Dividers, and an MPEG2 Decoder, 1999 IEEE International Solid-State Circuits Conference, Feb. 16, 1999.Applicant
- DreamCast Instruction Manual, Sega Enterprises, Ltd., ©1998.Applicant
- “Sega To Launch Video Camera for DreamCast”, Reuters Business News, Feb. 16, 2000.Applicant
- David Pescovitz, “Dream On”, Wired, Aug. 1999.Applicant
- Randy Nelson, “DreamCast 101: Everything You Ever Wanted To Know About Sega's Powerful New Console”, Official Sega Dreamcast Magazine, Jun. 1999.Applicant
- 2D/3D Graphics Card User Manual, Guillemot ©1999.Applicant
- Nintendo 64 Instruction Booklet, Nintendo of America, 1998.Applicant
- Steven Levy, “Here Comes PlayStation II”, Newsweek, Mar. 6, 2000.Applicant
- David Sheff, “Sony Smackage: Test Driving The PlayStation II”, Wired, Nov. 1999.Applicant
- Introducing The Next Generation PlayStation, Sony Computer Entertainment Inc., ©1999.Applicant
- Leadtek GTS, Aug. 3, 2000, www.hexus.net.Applicant
- Voodoo 5 5500 Review, Jul. 26, 2000, www.hexus.net.Applicant
- ATI Radeon 64 Meg DDR OEM, Aug. 19, 2000, www.hexus.net.Applicant
- Microsoft Xbox—The Future of Gaming, Microsoft Xbox Performance Sheet, www.xbox.com.Applicant
- Robert L. Cook, “Shade Trees”, Computer Graphics, vol. 18, No. 3, Jul. 1984.Applicant
- Wang et al., “Second-Depth Shadow Mapping”, Department of Computer Science, Univ. N.C, Chapel Hill, N.C. pp. 1-7.Applicant
- Peercy et al., “Efficient Bump Mapping Hardware”, Computer Graphics Proceedings, Annual Conference Series, 1997.Applicant
- Gustavo Oliveira, “Refractive Texture Mapping, Part One”, www.gamasutra.com, Nov. 10, 2000.Applicant
- John Schlag, Fast Embossing Effects on Raster Image Data, Graphics Gems IV, Edited by Paul S. Heckbert, Computer Science Department, Carnegie Mellon University, Academic Press, Inc., 1994,pp. 433-437.Applicant
- James F. Blinn, “Simulated Wrinkled Surfaces,” Caltech/JPL, pp. 26-292, SIGGRAPH 78 (1978).Applicant
- Tomas Möller and Eric Haines “Real-Time Rendering”, AK Peters, Ltd., ©1999, pp. 127-142.Applicant
- Technical Presentation: Vertex Buffers, posted Jun. 12, 2000, www.nvidia.com.Applicant
- Technical Presentation: Hardware Transform and Lighting, www.nvidia.com, posted Jun. 12, 2000.Applicant
- Technical Presentation: Hardware Bump-mapping Choices and Concepts, Jun. 7, 2000, www.nvidia.com.Applicant
- Technical Presentation: How to Bump Map a Skinned Polygonal Model, Jun. 7, 2000, www.nvidia.com.Applicant
- Technical Presentation: Computations for Hardware Lighting and Shading, Mar. 17, 2000, www.nvidia.com.Applicant
- Technical Presentation: Practical Bump-mapping for Today's GPUs, Mar. 17, 2000 www.nvidia.com.Applicant
- Technical Presentation: Shadows, Transparency, & Fog, Mar. 17, 2000 www.nvidia.com.Applicant
- Technical Presentation: GeForce 256 Register Combiners, Mar. 17, 2000, www.nvidia.com.Applicant
- Technical Presentation: TexGen & The Texture Matrix, Mar. 15, 2000 www.nvidia.com.Applicant
- Technical Presentation: Toon Shading, Mar. 15, 2000, www.nvidia.com.Applicant
- Technical Presentation: D3D 7 Vertex Lighting, Mar. 15, 2000, www.nvidia.com.Applicant
- Technical Presentation: Per-Pixel Lighting (by S. Dietrich) Mar. 14, 2000, www.nvidia.com.Applicant
- Technical Presentation: GeForce 256 and RIVA TNT Combiners, Dec. 8, 1999, www.nvidia.com.Applicant
- Technical Presentation: Vertex Cache Optimization, Nov. 12, 1999, www.nvidia.com.Applicant
- Technical Presentation: Vertex Blending, Nov. 12, 1999, www.nvidia.com.Applicant
- Technical Presentation: Hardware Transform and Lighting, Nov. 12, 1999, www.nvidia.com.Applicant
- Technical Presentation: GeForce 256 Overview, Nov. 12, 1999, www.nvidia.com.Applicant
- Technical Presentation: DirectX 7 and Texture Management, Nov. 12, 1999 www.nvidia.com.Applicant
- Technical Presentation: Dot Product Lighting, Nov. 12, 1999, www.nvidia.com.Applicant
- Technical Presentation: Texture Coordinate Generation, Nov. 3, 1999, www.nvidia.com.Applicant
- Technical Presentation: The ARB_multitexture Extension, Nov. 3, 1999 www.nvidia.com.Applicant
- Technical Presentation: Multitexture Combiners, Nov. 3, 1999, www.nvidia.com.Applicant
- Technical Presentation: Emboss Bump Mapping, Nov. 3, 1999, www.nvidia.com.Applicant
- Technical Presentation: Hardware Accelerated Anisotropic Lighting, Nov. 3, 1999 www.nvidia.com.Applicant
- Technical Presentation: Guard Band Clipping, Nov.3, 1999, www.nvidia.com.Applicant
- The RenderMan Interface, Stephan R. Keith, Version 3.1, Pixar Animation Studios, Sep. 1989.Applicant
- The RenderMan Interface, Version 3.2, Pixar Animation Studios, Jul. 2000, www.pixar.com.Applicant
- NVIDIA Product Overview, “GeForce2Ultra”, NVIDIA Corporation, Aug. 21, 2000, www.nvidia.com.Applicant
- Duke, “Dreamcast Technical Specs”, Sega Dreamcast Review, Sega, Feb. 1999, www.game-revolution.com.Applicant
- Marlin Rowley, “GeForce 1 & 2 GPU Speed Tests”, May 11, 2000, www.g256.com.Applicant
- “Dreamcast: The Full Story”, Next Generation, Sep. 1998.Applicant
- DirectX 7.0 Programmer's Reference, Microsoft Corporation, 1995-1999, (as part of the DirectX 7.0 SDK on the Companion CD included with “Inside Direct3D”, Microsoft Programming Series, Peter J. Kovach, Microsoft Press, 1999).Applicant
- “Inside Direct3D”, Microsoft Programming Series, Peter J. Kovach, Microsoft Press, 1999.Applicant
- “Open GL Programming Guide, The Official Guide to Learning OpenGL, Release 1”, Jackie Neider, Tom David, Mason Woo, Addison-Wesley Publishing Co., 1993.Applicant
- “Procedural Elements for Computer Graphics,” Second Edition, David F. Rogers, McGraw Hill, 1998.Applicant
- “Computer Graphics, Principles and Practice,” Second Edition, The Systems Programming Series, Foley, van Dam, Fiener, Hughes, Addison Wesley, 1990.Applicant
- “Principles of Three-Dimensional Computer Animation”, Revised Edition, Michael O'Rourke, W.W. Norton & Company, 1998.Examiner