Automatic bandwidth and stability control for switched pulse width modulation voltage regulator

[0002] This application claims priority to U.S. patent application No. 60/287,917 entitled AUTOMATIC BANDWIDTH AND STABILITY CONTROL FOR SWITCHED PULSE WIDTH MODULATOR POWER CONVERTER filed May 1, 2001, herein incorporated by reference in its entirety.

[0003] The present invention relates to switching voltage regulators. More specifically, it relates to stability control of a switching voltage regulator.

[0004] Pulse width modulated (PWM) voltage regulators are used to convert power from one voltage level to a second voltage level. A Buck voltage regulator typically operates by switching from a first voltage level to a second voltage level that is lower than the first voltage level. FIG. 1 illustrates an embodiment of a Buck regulator topology. Another regulator topology is used to obtain a boost converter that boosts the first voltage level to a second voltage level that is higher than the first voltage level. Still another topology is used to obtain a Buck-boost regulator that may convert the first voltage level to a second voltage level that is either higher or lower than the first voltage level. See Mitchell, DC-DC Switching Regulator Analysis,Bloom Associates, 1999, herein incorporated by reference in its entirety, for further background information regarding switching regulator design.

[0005] Switching regulators are highly efficient at converting from one voltage power level to another voltage power level. However, as described in Mitchell, switching regulators also require careful circuit design to obtain stability. One approach to stability is tuning of the circuit by a technician, which raises the cost of the product. Another approach is to specify external components having narrow tolerances, which leads to higher component cost. Also, the characteristics of components can change over time due to aging resulting in degradation of the stability of the converter circuit.

[0006] An embodiment of a control circuit for a switching voltage regulator circuit, according to the present invention, includes a measuring circuit having a first input terminal coupled to an output terminal of the switching voltage regulator circuit and a second input terminal coupled to an output of a switch drive circuit of the switching voltage regulator circuit. The measuring circuit is configured to generate a phase difference signal responsive to an output voltage signal at the output terminal of the switching voltage regulator circuit and an output signal of the switch drive circuit. The control circuit also includes a transfer function control circuit having a first input terminal for receiving the phase difference signal, the transfer function control circuit being configured to generate a transfer function control signal responsive to the phase difference signal such that the transfer function control signal causes at least one of a first zero or pole to be introduced to a transfer function of a voltage control feedback loop of the switching voltage regulator circuit. A variable characteristic element is disposed in the current control feedback loop and has a variable characteristic that varies responsive to the transfer function control signal. In a further refinement of this embodiment, the measuring circuit includes a first strip section having an input terminal coupled to the first input terminal of the measuring circuit, where the first strip section is configured to generate a measured phase signal in response to the output voltage signal. The measuring circuit also includes a second strip section having an input terminal coupled to the second input terminal of the measuring circuit, where the second strip section is configured to generate a reference signal responsive to a signal at the output of the switch drive circuit. A multiplier receives and multiplies the measured phase signal and the reference signal to generate the phase difference signal and a low pass filter filters the phase difference signal.

[0007] An embodiment of a method, according to the present invention, for automatically adjusting a switching voltage regulator circuit to account for an external component calls for measuring a phase of a ripple signal caused by the external component, generating a reference signal, and comparing the measured phase of the ripple signal to the reference signal to obtain a phase difference signal. The method then calls for adjusting a transfer function of a feedback path of the switching voltage regulator responsive to the phase difference signal to obtain stable operation of the switching voltage regulator circuit. In a further refinement of this embodiment, the step of adjusting a transfer function of a feedback path further includes converting the phase difference signal to a variable characteristic control signal and adjusting a variable characteristic in the feedback path of the switching voltage regulator responsive to the variable characteristic control signal. In still another refinement of this embodiment, the step of adjusting a variable characteristic in the feedback path of the switching voltage regulator responsive to the variable characteristic control signal further comprises adjusting a variable capacitance in the feedback path responsive to the variable characteristic control signal. Another embodiment of the method further calls for measuring an amplitude of the ripple signal. This embodiment then calls for converting the phase difference signal and the measured amplitude of the ripple signal into a second variable characteristic control signal and adjusting the transfer function of the feedback path of the switching voltage regulator responsive to the second variable characteristic control signal to improve a transient response of the switching voltage regulator circuit. In a further refinement of this embodiment, the step of adjusting the transfer function of the feedback path of the switching voltage regulator responsive to the second variable characteristic control signal to improve a transient response of the switching voltage regulator circuit further includes adjusting a gain in the feedback loop responsive to the second variable control signal and introducing at least one of a second pole or zero to the transfer function responsive to the second variable control signal.

[0008] The present invention is described herein with reference to the accompanying drawings, in which like numerals designate corresponding parts in the figures, wherein:

[0009] FIG. 1 is a functional block diagram illustrating an embodiment of a switching voltage regulator according to the present invention;

[0010] FIG. 2 is a waveform diagram illustrating the operation of the switching voltage regulator of FIG. 1;

[0011] FIG. 3A is a frequency response diagram illustrating an example of the frequency response of the error amplifier of the switching voltage regulator of FIG. 1;

[0012] FIG. 3B is an open loop frequency response diagram of the voltage regulator circuit of FIG. 1 with the current control loop closed illustrating an example of the frequency response due to the effect of an equivalent series resistance in the switching voltage regulator of FIG. 1;

[0013] FIG. 4 is a functional block diagram illustrating an embodiment of a measuring circuit according to the present invention for measuring the amplitude and phase of the ripple signal at Vout of FIG. 1;

[0014] FIG. 5 is a functional block diagram illustrating an embodiment of a control circuit according to the present invention that receives the analog amplitude and phase difference signals from the measuring circuit of FIG. 4 and generates a capacitance control signal for controlling a variable capacitance C1 of FIG. 1 and a resistance control signal for controlling a variable resistance that controls the gain of the error amplifier of FIG. 1;

[0015] FIG. 6 is a functional block diagram illustrating an embodiment of variable capacitance C1 of FIG. 1 and FIG. 5;

[0016] FIG. 7 is a functional block diagram illustrating an embodiment of the variable resistance of FIG. 5, where the variable resistance operates as an analog look-up table implementing a stability formula; and

[0017] FIG. 8 is a circuit diagram illustrating a portion of one embodiment of the error amplifier of FIG. 1 adapted to include the variable resistance of FIG. 5, which determines the gain of the error amplifier under control of the control circuit of FIG. 5.

[0018] The present invention is directed to a system and method for automatic stability control of a switching voltage converter.

[0019] FIG. 1 is a diagram illustrating an embodiment of a voltage regulator suitable for use with the present invention, where the regulator has a Buck topology. A first switching device S112 couples an input V_into one end of an inductor L 14 under control of a drive circuit 16. A second switching device S218 couples the end of inductor L 14 to ground also under control of the drive circuit 16. The drive circuit 16 closes switches S112 and S218 as shown in the waveform of FIG. 2 and is driven by a clock signal having a set switching frequency f_Sthat is provided by an oscillator (not shown). Switching devices S112 and S218 are typically implemented as MOSFET devices, but may also be implemented using other forms of switches and even bipolar transistors or diodes may be used in some applications.

[0020] The other end of inductor L 14 is coupled to an output V_outof the voltage regulator. Coupled to the output Vout are a load resistor 20 and a capacitor C₃22 having an equivalent series resistance (ESR) 24, where C₃22 is typically an external component and the ESR 24 is a parasitic resistance in series with the capacitor C₃22. The output is coupled to a gain unit 26 that applies a gain of a to the output voltage. The gain unit 26 is typically a resistive divider that divides the output voltage proportional to the reference voltage V_ref28 that is input to the error amplifier 30. An example of a generator that may be used to produce reference voltage V_ref28 is a bandgap voltage generator. The gain unit 26 is selected to scale the magnitude of desired output voltage at V_outto the reference voltage V_ref28 used by the circuit. For example, if the desired output voltage is two volts and the reference voltage is 1 volt, then α is selected to be 0.5.

[0021] The error amplifier 30 compares the adjusted output voltage to the reference voltage V_ref28 to produce an error signal that reflects a difference between the output voltage and the reference voltage. The error signal is filtered by a filter R₁32, and C₂34 and also by capacitor C₁36. The filtered error signal is then input to a comparator 38 that compares the filtered error signal to a sampled input current signal obtained from a sampling amplifier 40. The sampling amplifier 40 samples the input current signal by measuring the voltage drop V_RSacross a sense resistance 42, which, in one embodiment, is an inherent resistance of the MOSFET device that implements switch device S112. The V_RSvoltage is buffered and amplified by the sampling amplifier 40 and then input to the comparator 38. The output of the comparator 38 provides the input to the drive circuit 16 that controls the switching of switch devices S112 and S218.

[0022] The path from the output V_outthrough the error amplifier 30 and the filter formed by resistor 32, capacitor 34 and capacitor 36 is a feedback path. The feedback path has a transfer function determined by the gain of error amplifier 30 and the filter formed by resistor 32, capacitor 34 and capacitor 36. The feedback path closes a feedback loop through switches S112 and S218 and the inductor L 14 to V_out.

[0023] The stability of the PWM voltage converter circuit of FIG. 1 is determined by the elements in the feedback loop. These elements include the inductor L 14, the output capacitor C₃22, the ESR 24 of C₃22, and the load resistance 20, all of which are typically external components and, therefore, are not under the control of the designer of a PWM integrated circuit. Typically, a high quality capacitor having a very low ESR 24 is specified for C₃22, which typically results in C₃22 being an expensive component. Also, the capacitor may deteriorate resulting in an increased value for the ESR 24 and may also cause the PWM circuit's performance to deteriorate or even fail. Circuit elements C₁36, C₂34, R₁32, the α of the resistive divider 26, the gain of the error amplifier 30 and the gain of the sampling amplifier 40 are also often determined using external components. Some of these components may be integrated into a chip containing the PWM circuit, though this may result in strict tolerances being imposed for these components in order to preserve stability of the PWM converter circuit. The present invention allows more circuit elements, such as one or more of C₁36, C₂34, R₁32, the α of the resistive divider 26, the gain of the error amplifier 30 and the gain of the sampling amplifier 40, to be integrated into a single integrated circuit that automatically adjusts to the tolerances of the external devices, such as C₃22.

[0024] FIGS. 3A and 3B are Bode diagrams that illustrate the frequency response of different portions of the feedback loop of FIG. 1. FIG. 3A represents the gain and frequency response of the error amplifier with the poles and zero introduced by C₁, C₂, and R₁. A first pole is produced by C₂. A zero is introduced by the combination of C₂and R₁. A second pole is introduced by R₁and C₁when C₁is introduced to the feedback loop. The dotted line portion of the Bode diagram of FIG. 3A illustrates the frequency response in the absence of C₁.

[0025] FIG. 3B represents the “open loop” gain and frequency response of a voltage control feedback loop of the PWM converter circuit of FIG. 1 when the current control loop is closed and the ESR is present at the output V_out, but the voltage control feedback loop is open. The current control loop runs from sense resistance 42 through sense amplifier 40 and comparator 38 to drive circuit 16 and back to switches S112 and S218, which control the current through the sense resistance 42. The voltage control feedback loop runs from output V_outthrough scaling circuit 26 to error amplifier 30, through the filters formed by capacitor 34 and resistor 32 along with capacitor 36 to comparator 38, and from the comparator 38 through drive circuit 16 to switches S112 and S218, which produce the output voltage at V_out. Note that the gain decreases until a zero introduced by the ESR is introduced, where the gain levels off. In the absence of the pole introduced by C₁36 to the error amplifier response of FIG. 3A, the gain in FIG. 3B would increase with the introduction of ESR resulting in an unstable PWM circuit response. Due to the pole introduced by C₁36, a 6 decibel (dB) per octave roll-off at 0 dB yields a 90° phase margin and results in a stable circuit.

[0026] In one embodiment of a PWM circuit according to the present invention, C₁36 is adjusted to compensate for the parasitic ESR value that is present in the external capacitor C₃22.In another embodiment of the present invention, in order to provide a stable frequency response, the loop bandwidth is adjusted to obtain a good load transient response while at the same time compensating for the ESR 24 by adjusting the value of C₁36. In conventional devices, C₁36 is typically either fixed by the value chosen for the design and the maximum ESR of C₃22 must be specified or the value of C₁36 is manually set when the converter circuit is assembled. For further information concerning AC signal analysis of PWM switches see Daniel Mitchell in DC-to-DC Switching Response Analysis,1988, McGraw-Hill, herein incorporated by reference.

[0027] In one embodiment of the present invention, the PWM circuit determines the ESR value electronically and automatically adjusts the value of capacitance C₁36 to compensate for the ESR of external capacitor 22. In order to compensate for the ESR, the PWM circuit monitors the phase of the ripple voltage. FIG. 2 illustrates the ripple signal introduced in the output voltage by the ESR. The ripple at Vout occurs largely due to the presence of ESR 24. The ripple may be between 0° and 90° out-of-phase due to the ratio between the ESR 24 and the capacitance of C₃22. A control circuit converts the measured phase difference signal into a control signal for adjusting capacitance C₁36 to introduce a zero to the transfer function of the voltage control feedback loop. Introducing the zero to the transfer function to compensate for the ESR 24 of external capacitor 22 obtains stable operation of the PWM circuit.

[0028] In another embodiment of the present invention, the PWM circuit is configured to automatically improve the bandwidth of the circuit by controlling the gain of error amplifier 30 in the feedback loop and adjusting the capacitance C₂of capacitor 34. In this embodiment, the PWM circuit monitors both the amplitude and phase of the ripple signal present at the output Vout. From these measurements, the gain of error amplifier 30 and capacitance C₂34 in the voltage control feedback loop may be adjusted to optimize bandwidth response of the PWM circuit. Adjusting the gain of amplifier 30 improves the bandwidth response of the feedback loop, but capacitance C₂must be adjusted in combination with the gain to properly position a pole in the transfer function of the voltage control feedback loop for optimal transient response.

[0029] FIG. 4 illustrates an embodiment of a measuring circuit according to the present invention for measuring the amplitude and phase of the ripple signal at V_out. In this embodiment, a pair of intermediate frequency (IF) strip circuits similar to those found in radio receivers are used to obtain the phase of the ripple signal. The embodiment shown in FIG. 4 includes an optional circuit similar to a Radio Signal Strength Indicator (RSSI) circuit that sums portions of one of the IF strips and is used to detect the amplitude of the ripple signal. For further information regarding IF and RSSI circuits, see LOG-AMP design, chapter 9, in the 1992 Amplifier Applications Guide, Analog Devices, ISBN-0-916550-10-9, herein incorporated by reference in its entirety for all purposes. The measuring circuit includes several strip sections, where each section may include a combination of multiple bandpass filters and amplifiers. In one embodiment, a first strip section includes a first bandpass filter 114, an amplifier 116, a second bandpass filter 118 and a limiter 120 coupled between V_outand an input of a multiplier 122. The first strip section derives the phase of the ripple at V_out. A second strip section includes a first bandpass filter 124, an amplifier 126, a second bandpass filter 128 and a limiter 130 coupled between the output of the drive circuit 16, e.g. the switching signal for switches S112 and S218, and another input of the multiplier 122. The second strip section provides a reference signal for comparison to the measured ripple at V_outprovided by the first strip section. The multiplier 122 effectively compares the measured phase of the ripple voltage to the reference signal to output a phase difference signal that drives a low-pass filter formed by a resistor ESR 24 and capacitor C322. The frequencies of the bandpass filters are centered substantially around the switching frequency f_Sof the PWM switching circuit.

[0030] The components of the first strip section may also be tapped to generate an amplitude signal reflecting the amplitude of the ripple signal at V_out. The output of each of the first bandpass filter 114, the amplifier 116, and the second bandpass filter 118 of the first strip section are added together by a series of adders that drive a series resistor 140 and capacitor 142 to produce the amplitude signal. The circuit used to generate the amplitude resembles an RSSI circuit.

[0031] The amplitude and phase difference signals are then converted into control signals the control the transfer function of the voltage control feedback loop. In the present invention, the transfer function of the error amplifier 30 may be controlled by adjusting the one or more of C₁, C₂, R₁, and the gain of the error amplifier. In one embodiment, C₁36 is an adjustable capacitance that is varied in response to the measured phase difference signal generated by the measuring circuit of FIG. 4. In another embodiment of the present invention, error amplifier 30 includes an adjustable resistance, as illustrated in FIG. 8, that determines a gain Gm of the error amplifier and that is controlled to change the transfer function of the error amplifier and C₂is an adjustable capacitance that is controlled to accommodate the change in the gain Gm.

[0032] By way of example, the transfer function for the error amplifier 30 may be calculated as follows. In the following equation (1), K(f) represents the transfer function of the error amplifier and K_optrepresents the optimum gain of the error amp without the filter produced by the introduction of C_{1 and C2}, e.g. (Gm*R₁).

[0033] K(f)=[K_opt(1+j*(f/f_corner))]/jf/f_corner)*(1+jf/f_corner2)]  (1);

[0034] where f_corneris the first pole at C₂*R₁and f_corner2 is the pole at C₁*R₁. Equation (2) demonstrates a formula that may be used for f_cornerand f_corner2.

[0035] f_corner=fn/3, where fn=1/(2*π*(L*C₃))  (2).

[0036] Furthermore, equation (3) below demonstrates a formula that may be used to optimize the error amplifier gain in order to optimize bandwidth:

[0037] K_opt=2*fs*Rs*C₃/α  (3);

[0038] where α is the gain of the resistive divider, fs is switching frequency, Rs is the transimpedance of the I to V converter (e.g. the sampling amplifier) used to measure the current across switch S112 in the converter measurement circuit A, and C₃22 is the value of the output capacitor. Thus, the gain Gm and f_cornercan be set if the output capacitor value of C₃is known.

[0039] The pole f_corner2 can be calculated, for example, using equation (4) below:

[0040] f_corner2=(f_S/10)*{10**[(1−2*phase/π)*2]}  (4);

[0041] which is an approximation of:

[0042] f_corner2=1/(2*π*R_ESR*C₃)  (5).

[0043] Thus phase, which is measured and known, can be set for the f_corner2 pole. If only the phase value is available, then it is possible to compensate for the ESR, e.g. RESR, but not to set the gain and the first zero. This requires the amplitude measurement be obtained.

[0044] The formulae above indicate that Rs, C₃, α and L must be known in order to set the transfer function of the converter circuit. However, by rearranging the formulae above, it is possible to obtain expressions based upon the measured parameters of the amplitude and phase of the ripple voltage along with the value of f_Sand V_RS, the voltage across the sense resistance Rs. V_RSis basically a known value for the circuit design. Thus, according to the present invention, the Kopt, fcorner and fcorner2 may be derived from the measured amplitude and phase measurements.

[0045] In current controlled voltage converters, e.g. current limited converters, V_RSmay be taken as (1/3)V_LIM, where V_LIMsets the current limit of the converter and is typically in the range of 100 to 150 mV. Higher values for V_LIMmay adversely affect the efficiency of the converter. Since V_LIMis set for the circuit, V_RSwill be a known value, e.g. 50 mV. Under this assumption, the following formulae may be obtained:

[0046] ti K=(V_RS/V_{amplitude in})*[tan(phase)+1]/4  (6);

[0047] f_corner=f_S*(2*phase)/[(1−D)*K*1.24*2*π]  (7);

[0048] and

[0049] f_corner2=(f_S/10)*{10**[(1−2*phase/π)*2]}  (8).

[0050] where phase is in radians and D is duty cycle, which may be cxpressed as f_S(time S1 is closed)=(Vout/Vin). Note that the duty cycle is known for the chip design and is available from the output of comparator 38. After the calculation of (6),(7) and (8), the values for C1, C2, Gm follow by using a selected value of R1, which yields equations (9), (10) and (11) below.

[0051] K=Gm*R1  (9)

[0052] f_corner=1(2π*C₂R₁)  (10)

[0053] f_corner2=1(2π*C₁R₁)  (11)

[0054] Note that, because there are four variables and three equations, a similar result may be obtained by selecting a fixed value for one of the other parameters. For example, a small fixed value of C₂may be selected and R₁and C₁varied. Also, C₁may be fixed and Gm, R₁and C₂calculated. R₁is selected to be a fixed value here because it is somewhat easier to then adjust Gm and C₁.There is thus a degree of freedom in the design of the PWM circuit according to the present invention without departing from the teachings of the present invention.

[0055] Note from equation (7) and (9) above that Gm and C₂must both be adjusted to optimize the bandwidth of the transient response of the voltage control feedback loop. Higher bandwidth yields a better transient response for the circuit. However, if the gain Gm becomes too high, then the circuit may become unstable. It is generally desirable that bandwidth response be in the range of (1/3)f_Sto (1/10)f_S. When Gm is adjusted, then K changes, as is seen in equation (9). This causes f_cornerto shift, as is seen in equation (7). From equation (10), it can be seen that C₂may be adjusted to compensate for the change in Gm and to position f_cornerfor improved transient response.

[0056] These formulae may be implemented by a processor, such as a digital signal processor (DSP), or using analog to digital (A/D) converters in combination with an analog look-up table. For example, a four bit A/D converter may be used to implement sixteen discrete values.

[0057] FIG. 5 illustrates one embodiment of a control circuit that converts the analog amplitude and phase difference signals output by the measuring circuit of FIG. 4 into capacitance and resistance control signals that control the variable capacitance C₁of variable capacitance element 36 and a variable resistor element in error amplifier 30 that determines the gain of the error amplifier. The control circuit of FIG. 5 utilizes a first Analog to Digital (A/D) converter 210 to convert the analog amplitude signal 212 into a digital value that is output to a capacitance encoder 230 and a resistance encoder 232. The capacitance encoder 230 encodes the digital value for the amplitude signal output by the first A/D converter 210 to generate a digital capacitance control signal 216. The digital capacitance control signal 216 drives variable capacitance 36 coupled to the output of error amplifier 30. One embodiment of variable capacitance element 36 is illustrated in FIG. 6, where the digital capacitance control signal drives an array of transistors 218 coupled in series with an array of capacitors 220 to vary the adjustable capacitance C₁36 coupled to the output of the error amplifier 30. The digital capacitance control signal 216 selectively activates or deactivates the transistors of variable capacitance C₁to add or remove the capacitance of the individual capacitors of variable capacitance element 36 to the PWM voltage converter circuit transfer function thereby adjusting the variable capacitance C₁of variable capacitance element 36. In some embodiments of the present invention, capacitance C2 may be a variable capacitance that is implemented in a manner similar to the implementation of variable capacitance element 36.

[0058] The control circuit of FIG. 5 utilizes a second Analog to Digital (A/D) converter 220 to convert the analog phase difference signal 214 into a digital value that is output to the capacitance encoder 230 and the resistance encoder 232. The capacitance encoder 230 may use the digital value for the phase difference signal output by the first A/D converter 210 to generate the digital capacitance control signal 216. The resistance encoder 232 uses the digital values for the amplitude and phase difference signals output by the first and second A/D converters 210 and 220 to generate the digital resistance element within the error amplifier 30 that determines the gain Gm of the amplifier. An example of the variable resistance element disposed within a portion of the error amplifier 30 is illustrated in FIG. 8, which shows the variable resistance element disposed between the sources of a differential pair of transistors. The gain Gm is inversely proportional to the value of the variable resistance.

[0059] FIG. 7 illustrates one embodiment of the variable resistance element of FIG. 5. The variable resistance circuit of FIG. 7 includes a first array of transistors 300, where each transistor of the first array is coupled in series with, in this embodiment, a series of five resistors. Each column includes a second array of transistors 320 that selectively bypasses four of the five resistors in the column. The first array of transistors 300 is driven by an amplitude portion of the resistance control signal 218 that, in this embodiment, selects one column of resistors to produce the variable resistance 32. In this embodiment the resistance encoder selects one of sixteen lines to activate so that one of the column values A1 through A16 is active. The resistors in each of the columns is scaled relative to the next column such that selecting, for example the second column results in twice the resistance as the first column and selecting the third column results in three times the resistance of the first column. The second array of transistors 320 is driven by a phase portion of the resistance value, where the resistance within the column is determined by, in this embodiment, the four bit value of the phase portion of the resistance control signal 218. In this embodiment, the variable resistance element implements the [tan(phase)+1]/4 of equation (6) above. The circuit of FIG. 7 is a two dimensional array controlled by transistors driven by the resistance control value. The resistance values of FIG. 7 are selected to implement the function (6), (7) and (8) above. In effect, the variable resistance of FIG. 7 operates as an analog look-up table that selects a resistance in accordance with the resistance control value in order to adjust Gm for stable operation of the switching converter circuit of FIG. 1.

[0060] For example, phase may be represented by the values (0, 1/16, 2/16, . . . π)*π/2, which may be viewed as values A0 through A17. In one embodiment, the resistance value needed to implement the tan(phase) factor to set the value of K for f_cornerin equation (7) above may be scaled in accordance with the following table:

[0061] In Table 1, some values need not be implemented based upon operating assumptions. Thus, A1 for the value 0 need not be implemented because a null resistance will not be needed. Likewise, the value for A17 is so large that it is effectively an open and will not be needed. The number of discrete values can bc lowered to a number of values, e.g. sixteen, that may be implemented with the four bit A/D converter.

[0062] Similarly, the expression 10*{10**[(1−2*phase/π)*2} needed to implement f_corner2 in equation (8) above, may be implemented using resistors scaled according to Table 2 below:

[0063] Again, some entries in Table 2 may be eliminated in order to reduce the number of discrete values implemented to fall within the range controllable by a four bit A/D converter. As one of ordinary skill in the art will readily appreciate, the components of the variable capacitance of FIG. 6 and the variable resistance of FIG. 7 may be scaled to implement the functions above to automatically introduce a pole or a zero to the transfer function of the feedback loop in order to obtain stable operation.

[0064] As noted above, the converter circuit may be implemented in a variety of other ways. For example, a microprocessor may be utilized to analyze the amplitude 212 and phase 214 signals and generate the capacitance control signal 216. Also, the adjustable capacitance C136 may be implemented in a variety of ways, including a. series of capacitors having the approximately the same level of capacitance or a series of capacitors having increasing levels of capacitance. The goal of the conversion circuit is to set the error amplifier 30 gain and the C₁/C₂/R₁value to compensate for the ESR introduced by external output capacitor C₃. Note that if there is no ESR, e.g. a very high quality output capacitor is used for C₃, then no capacitance may be necessary at C₁36.

[0065] It should also be noted that the amplitude and phase measurement at V_outmay be performed when the PWM voltage regulator circuit first starts up. At this point, because error amplifier 30 is clamped to a supply voltage level due to the low voltage level at V_out, the voltage control feedback loop is essentially open and the values of C₁, C₂, R₁, and Gm are not relevant to the operation of the circuit. A start-up period with the feedback loop open permits the value for capacitance C₁, C₂, R₁, and Gm, e.g. the transfer function of the voltage control feedback loop, to be determined before the loop is automatically closed at the termination of a start-up sequence. Typically, the circuit will start in open loop mode as a result of the output voltage being so low that the error amplifier 30 is clamped to the voltage of an internal power supply rail. The error amplifier will not begin to be effective until the voltage at Vout approaches its desired value. A circuit may also be provided to generate a Reset signal input to the A/D converters to be generated when Vout reaches approximately 90% of its desired value.

[0066] In another approach, the start-up sequence may be controlled by a soft start mechanism, e.g. software controlled, that provides for a sufficient period of time, e.g. approximately one hundred switching cycles of the drive circuit, to allow the PWM circuitry, such as the filters and A/D converter, to settle and permit the amplitude and phase values to be measured before loop closure. If a soft start approach is used, then it is easier to implement the A/D converters used in the control circuit of one embodiment of the present invention because the A/D converters are permitted a longer period of time to convert the analog signals to digital values. Further note that the A/D converters may be configured to begin conversion from an intermediate value at start-up. Also note that this mechanism may be configured to periodically repeat, in some applications, in order to compensate for variations in the ESR due to aging of the components and environmental factors.

[0067] In one embodiment, the Reset signal input to the first and second A/D converters 210 AND 220 of FIG. 5 may be driven by a power-on reset signal or another source of control input to cause the A/D converters 210, 220 to evaluate and set the values for the capacitance and resistance control signals 216, 218. In one embodiment, the A/D converters include latches to latch the digital values for the amplitude and phase difference signals. The A/D converters may also be configured to allow a predetermined number of clock cycles of switching clock signal f_Sto pass before latching to allow settling of components before loop closure. In such an embodiment, the A/D converters may include counters to count out the number of cycles, e.g. 8 to 10, or successive approximation A/D converters may be used that automatically latch the digital value when conversion is complete.

[0068] In one embodiment, the present invention contributes to stability and low ripple in a voltage regulator by adjusting the transfer function of a voltage control feedback loop of the voltage regulator to compensate for the characteristics of an external output capacitor. In this embodiment, a phase measurement of the ripple voltage at the output of the voltage regulator is made and used to automatically determine the value of the adjustable capacitance C₁needed to stabilize the switching circuit. In accordance with the present invention, a control circuit according to the present invention automatically adjusts the transfer function of the voltage control feedback loop of the switching voltage regulator circuit to obtain stable operation of the circuit.

[0069] In another embodiment, the present invention balances stability of the voltage regulator circuit with the transient behavior and gain of the feedback loop. The adjustable capacitance compensates for the ESR to create stability in the switching control circuit of the voltage regulator and reduce the gain of the feedback loop at high frequencies. In this embodiment, amplitude and phase measurements of the ripple voltage at the output of the voltage regulator are made and used to automatically determine the value of the adjustable capacitance needed to stabilize the switching circuit. The gain of the error amplifier Gm and another adjustable capacitance C₂are adjusted to improve the bandwidth of the transient response of the voltage regulator circuit.

[0070] In view of the wide variety of embodiments to which the principles of the present invention can be applied, it should be understood that the illustrated embodiments are exemplary only, and should not be taken as limiting the scope of the present invention. For example, a variety of circuit elements may be utilized to perform certain functions of the present invention. Also, the function of some circuit elements may be combined into a single device while the function of other circuit elements may be implemented so as to be performed by multiple devices. For example, while the embodiment discussed above controls the adjustable capacitance C₁to provide stability and improve bandwidth for the PWM circuit, one of ordinary skill in the art will readily appreciate that adjustments to any one or a combination of C₁, C₂, R₁and the gain of the error amplifier may also be employed to alter the transfer function of the error amplifier to compensate for ESR and improve bandwidth. Also, certain aspects of the embodiments shown, such as soft start, may be implemented alternatively in software, hardware, firmware or a combination thereof.

[0071] Also note that while the present invention is described in the context of a switching voltage regulator having a Buck topology, the teachings of the present invention may also be applied to other types of voltage regulators, such as boost converters and Buck-boost converters. While the equations for the transfer functions for these other types of regulators will be different, the automatic adjustment of the transfer function to obtain stability and/or improved transient response may be applied to these topologies.

[0072] The invention is not limited to the precise embodiments shown herein. Therefore, all embodiments that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.