Adding a laplace transform zero to a linear integrated circuit for frequency stability

[0002] 1. Field of the Invention

[0003] The invention relates to a circuit and method for adding a Laplace transform zero to a linear integrated circuit, and more particularly to a circuit and method for adding a Laplace transform zero in a switching regulator feedback loop for providing frequency stability.

[0004] 2. Description of the Related Art

[0005] Closed loop negative feedback systems are commonly employed in linear integrated circuits. For instance, switching regulators use a feedback loop to monitor the output voltage in order to provide regulation. To ensure stability in any closed loop system, the Nyquist criterion must be met. The Nyquist criterion states that a closed loop system is stable if the phase shift around the loop is less than 180 degrees at unity gain. Typically, a compensation circuit is added to a feedback loop to modulate the phase shift of the feedback loop to obtain stability.

[0006] The frequency response of a linear circuit can be characterized by the presence of “poles” and “zeros”. A “pole” is a mathematical term which signifies the complex frequency at which gain reduction begins. On the other hand, a “zero” signifies the complex frequency at which gain increase starts. Poles and zeros on the left half plane of a complex frequency plane or s-plane are considered normal and can be compensated. However, poles and zeros on the right half plane of a complex frequency plane are usually problematic and difficult to manipulate and is not addressed in the present application. Generally, a pole contributes a −90° phase shift while a zero contributes a +90° phase shift. A pole cancels out the phase shift of a zero for zeros in the left half plane. In designing a closed loop system with compensation, the location of the poles and zeros are manipulated so as to avoid a greater than 180° phase shift at unity gain.

[0007] In a linear circuit, poles are created by placing a small capacitor on a node with a high dynamic impedance. If the capacitor is placed at a gain stage, the capacitance can be multiplied by the gain of the stage to increase its effectiveness. Each pole has a zero associated with it. That is, at some point, the dynamic resistance of the gain stage will limit the gain loss capable of being achieved by the capacitor. Thus, a zero can be created by placing a resistor in series with the gain reduction capacitor.

[0008] A conventional voltage mode switching regulator uses an inductor-capacitor (LC) network at the voltage output terminal for filtering the regulated output voltage to produce a relatively constant DC output voltage. FIG. 1 is a schematic diagram of a conventional switching regulator including a switching regulator controller 10 and an LC circuit 11. Switching regulator controller 10 generates a regulated output voltage V_swat an output terminal 13 which is coupled to LC circuit 11 for providing a filtered output voltage V_OUT. The output voltage V_OUTis coupled back to controller 10 at a feedback (FB) terminal 15 for forming a feedback control loop. The LC circuit has associated with it two poles, one pole associated with each element. If the feedback control loop is not compensated, LC circuit 11 alone contributes an −180°. phase shift to the system and loop instability results, causing the output voltage to oscillate. Because virtually every switching regulator uses an LC filter circuit to filter the regulated output voltage, compensation must be provided in the feedback control loop of a switching regulator to compensate for the effect of the two poles introduced by the LC circuit.

[0009] A conventional compensation technique in switching regulators involves adding a circuit in series with the feedback loop which produces a Laplace zero. The zero is added to the feedback control loop to cancel out one of the two poles of the LC filter circuit, thus insuring closed loop stability. U.S. Pat. No. 5,382,918 to Yamatake describes using a capacitance multiplying op-amp to provide a large effective capacitance and a resistor in series as the frequency compensation element of a switching regulator. U.S. Pat. No. 5,514,947 to Berg describes a phase lead compensation circuit for providing additional phase to the loop gain of a switching regulator near the unity gain frequency. The phase lead compensation circuit of Berg uses a transconductance amplifier driving a frequency-dependent load, implemented as a band-limited op amp, in the feedback control loop of the switching regulator. These approaches are problematic because they both require a “high quality” differential amplifier in operation which are significantly large and complex to realize. In practice, differential amplifiers are typically large devices and can be relatively slow. Furthermore, the differential amplifiers tend to sink large amounts of current proportional to speed. The compensation approaches described by Yamatake and Berg are undesirable because the compensation techniques require sacrificing speed for closed loop stability. In addition the op-amp used in the compensation circuit needs to be compensated for stability itself, making the circuit more complex to implement.

[0010] FIG. 1 illustrates another approach for providing compensation in a feedback control loop of a switching regulator. Referring to FIG. 1, the output voltage V_OUTis coupled to the feedback terminal 15 and further to a voltage divider including resistors R₁and R₂. The operation of the feedback control loop in controller 10 is well known in the art. The voltage divider steps down output voltage V_OUTand the divided voltage V_Ris coupled to an error amplifier 20 which compares the divided voltage V_Rto a reference voltage V_Ref. Error amplifier 20 generates an error output signal indicative of the difference between voltage V_Rand reference voltage V_Ref. The feedback control loop of controller 10 operates to regulate the output voltage V_OUTbased on the error output of error amplifier 20 so that voltage V_Requals voltage V_Ref.

[0011] FIG. 2ais a plot of the loop gain magnitude vs. frequency in log scale for the switching regulator of FIG. 1 without any compensation. The low frequency loop gain is first reduced by a pole associated with error amplifier 20. The gain loss is modified by a zero also associated with the error amplifier. Then, at high frequency, the effect of the double-pole in the LC filter circuit causes a large loss in the loop gain such that the phase shift at unity gain is equal to or greater than 180°. The feedback control loop of the uncompensated switching regulator of FIG. 1 is unstable unless the gain is substantially reduced.

[0012] In the switching regulator of FIG. 1, a capacitor 18 (typically referred to as a “zero capacitor”) is connected in parallel to resistor R₁of the voltage divider.

[0013] Capacitor 18 introduces a zero-pole pair in the feedback loop. The location (or frequency) of the zero-pole pair is determined by the resistance of the voltage divider and the capacitance of capacitor 18. For practical resistance and capacitance values, the zero and pole introduced by capacitor 18 are typically located close to each other so that the zero is canceled out quickly by the nearby associated pole. FIG. 2bis a plot of the loop gain magnitude vs. frequency in log scale in the switching regulator of FIG. 1 incorporating zero capacitor 18. Here, the operation of the zero capacitor ensures that the phase shift is less than 180° near unity gain. However, the compensation provided by zero capacitor 18 is limited and often does not provide sufficient phase margin at unity gain. For example, at high frequency, zero capacitor 18 shorts out resistor R₁, resulting in no or minimal gain loss in the feedback loop. Thus, the compensation provided by capacitor 18 is not effective at high frequency. Also, the voltage divider of resistors R₁and R₂typically provides only a gain loss of 3 dB. The 3 dB gain loss limits the ratio of the pole to zero angular frequency of capacitor 18, and thus, limits the compensation range capable of being achieved by the use of a single zero capacitor 18. The feedback loop of switching regulator of FIG. 1 is susceptible to instability when the switching regulator is subjected to fluctuations in the load impedance because of this limited compensation range.

[0014] Thus, it is desirable to provide a compensation circuit in a feedback loop of a linear circuit which is capable of providing effective pole cancellation.

[0015] According to one embodiment of the present invention, a compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system is provided. The first circuit includes a first terminal generating a first voltage for the closed loop feedback system and a feedback terminal for receiving a feedback voltage from the closed loop feedback system and coupling the feedback voltage to an input node in the first circuit. The compensation circuit includes a first capacitor, an amplifier and a second capacitor. The first capacitor is coupled between the feedback terminal of the first circuit and a first node. The first capacitor receives the feedback voltage at the feedback terminal and functions to block out the DC component of the feedback voltage. The amplifier is coupled between the first node and a second node. The second capacitor is coupled between the second node and the input node of the first circuit. The compensation circuit further includes a first resistor coupled between the feedback terminal and the input node for providing a resistive load to the compensation circuit.

[0016] The compensation circuit amplifies the capacitance of the second capacitor and introduces a zero in the first circuit effective for pole-cancellation in the closed loop feedback system. Furthermore, the zero introduced by the compensation circuit has effectiveness over a wide range of frequencies.

[0017] In one embodiment, the compensation circuit of the present invention is applied to a switching regulator controller circuit for providing an effective zero in the feedback loop of a switching regulator. The zero acts to compensate for the effect of the double-pole introduced by the LC filter circuit generally applied to the regulated output voltage of the switching regulator controller circuit.

[0018] The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

[0019] FIG. 1 is a schematic diagram of a conventional switching regulator including a zero capacitor for compensation.

[0020] FIG. 2ais a loop gain vs. frequency plot for a conventional feedback system in a switching regulator without zero compensation.

[0021] FIG. 2bis a loop gain vs. frequency plot for a feedback system in a switching regulator including a zero capacitor for compensation.

[0022] FIG. 3 is a schematic diagram of a switching regulator including a switching regulator controller incorporating a zero generation circuit according to one embodiment of the present invention.

[0023] FIG. 4 is a loop gain vs. frequency plot for the feedback system of the switching regulator in FIG. 3.

[0024] FIG. 5 is a circuit diagram of a zero generation circuit implemented using CMOS devices according to one embodiment of the present invention.

[0025] FIG. 6 is a schematic diagram of a switching regulator controller incorporating a zero generation circuit according to another embodiment of the present invention.

[0026] In the present disclosure, like objects which appear in more than one figure are provided with like reference numerals.

[0027] In accordance with the present invention, a zero generation circuit for adding a Laplace transform zero in a linear or analog circuit includes a blocking capacitor and an open loop amplifier coupled to a zero capacitor for multiplying the capacitance of the zero capacitor. The zero generation circuit provides a wide band and effective zero for pole cancellation in a linear circuit for obtaining frequency stability. The zero generation circuit of the resent invention has the advantages of consuming a small circuit area and being power efficient, drawing only a small bias current. Furthermore, the zero generation circuit can operate at high frequency to provide compensation for a large frequency range. The zero generation circuit of the present invention can be applied in switching voltage regulators and other closed loop feedback systems with multiple poles for introducing an effective “zero” compensation and improving frequency stability.

[0028] In the present description, a “zero” and a “pole” have meanings well understood by one skilled in the art. Specifically, a “zero” refers to the complex frequency at which the frequency response of a linear circuit has a zero amplitude, and a “pole” refers to the complex frequency at which the frequency response of a linear circuit has an infinite amplitude. In a feedback system, a pole signifies the frequency at which gain reduction begins while a zero signifies the frequency at which gain increase starts.

[0029] FIG. 3 is a schematic diagram of a switching regulator including a switching regulator controller incorporating a zero generation circuit according to one embodiment of the present invention. The circuitry of switching regulator controller 330 is conventional except for the zero generation circuit 310. Switching regulator controller 330 generates a regulated output voltage V_SWon an output terminal 302. The regulated output voltage V_SWis coupled to an LC filter circuit 11 to generate an output voltage V_OUThaving substantially constant magnitudes. Switching regulator 300, constructed using controller 330 and LC circuit 11, forms a closed loop feedback system for regulating output voltage V_SWand consequently, the output voltage V_OUT. The output voltage V_OUTfrom LC filter circuit 11 is fed back to controller 330 on a feedback terminal 304. Typically, the output voltage V_OUTis coupled to a voltage divider including resistors R₁and R₂and generating in feedback voltage VFB is coupled to the control circuitry of controller 330. In FIG. 3, the control circuitry of controller 330

[0030] In the feedback loop of switching regulator 300, error amplifier 308 has associated with it a pole and a zero. The pole and zero within error amplifier 308 are typically easy to generate because error amplifier 308 includes high impedance nodes. However, it is difficult to generate more than one pole or zero within error amplifier 308. On the other hand, LC filter circuit 11 introduces two poles to the feedback loop of switching regulator 300 which need to be compensated. In the present embodiment, a zero generation circuit 310 is incorporated in controller 330 to introduce a zero to the feedback loop of switching regulator 300, in addition to the zero generated by the error amplifier. Zero generation circuit 310 functions to ensure that the feedback system of switching regulator 300 meets the Nyquist criterion for frequency stability.

[0031] According to one embodiment of the present embodiment, zero generation circuit 310 includes a blocking capacitor C_B, an amplifier AZ, and a zero capacitor C_Z, connected in series between feedback terminal 304 and feedback voltage V_FB(node 306). In FIG. 3, circuit 310 is illustrated with a resistor R_Z1, between capacitor C_Band amplifier AZ and with a resistor R_Z2between amplifier AZ and capacitor C_Zdrawn in dotted line. Resistors R_Z1and R_Z2are illustrative only and are used to represent the equivalent input impedance and the equivalent output impedance, respectively, of amplifier AZ. Although resistors R_Z1and R_Z2are not meant to be actual elements or components in an actual implementation of circuit 310, circuit 310 may include resistors as needed for the implementation of amplifier AZ or for other purposes. As will be explained in more detail below, one embodiment of amplifier AZ includes an input resistor R_ZIwhich, when combined with the gain of the first gain stage in amplifier AZ, creates the input impedance R_Z1shown in FIG. 3.

[0032] In operation, capacitor C_Breceives output voltage V_OUTon feedback terminal 304 and functions to block out the DC component of output voltage V_OUT. Amplifier AZ amplifies the AC component of output voltage V_OUTprovided by capacitor C_Bbefore coupling the AC signal to zero capacitor C_Z. The amplification function performed by amplifier AZ has the effect of amplifying the capacitance of capacitor C_zsuch that capacitor C_zcan be implemented as a smaller capacitor while capable of introducing an effective zero in the feedback system. Furthermore, the AC signal amplification provided by amplifier AZ is also capable of introducing a zero having a wide range of applicability so that the zero is effective over a wide band of frequency. The zero signal generated by capacitor C_Zis summed with feedback voltage V_FBat node 306 before the feedback voltage V_FBis coupled to the control circuitry of controller 330. In FIG. 3, the summed feedback voltage is coupled to error amplifier 308.

[0033] The transfer function from the feedback voltage V_FBto the error output (denoted voltage V_EOUT), in the limiting conditions of R₁>>R_Z2, A_Z>=1 and r˜1, is given as follows: $\begin{array}{cc}\frac{V_{\mathrm{FB}}}{V_{\mathrm{EOUT}}}\approx \frac{1}{r}\frac{\left(A_Z*C_Z*R_1*s+1\right)}{\left(\left(R_1/r\right)*C_Z*s+1\right)},& \text{(1)}\end{array}$

[0034] where A_Zis the gain of amplifier AZ, s is the complex frequency of the Laplace transform and r is given as: $\begin{array}{cc}r=\frac{R_1}{R_2}+1.& \text{(2)}\end{array}$

[0035] Equation (1) above yields a pole and a zero angular frequency as follows:

[0036] ω_Z=1/A_Z*R₁*C_Z, and   (3)

[0037] ω_P=1/(R₁/r)*C_Z.   (4)

[0038] As can be seen from equation (3) above, resistor R₁of the voltage divider of controller 330 provides the resistive load to capacitor C_Zand amplifier AZ for adding a zero in the feedback system. On the other hand, while in equation (4), both resistors R₁and R₂are used to provide a resistive load for introducing the pole of zero generation circuit 310, resistor R₂is not critical for the placement of the pole and can be omitted in other embodiments of the present invention. When resistor R₂is omitted (that is, resistance of resistor R₂is infinite), the factor r has a value of 1 (equation 2) and the angular frequency of the pole, ω_p, depends only on the resistive load of R₁.

[0039] The ratio of pole angular frequency (equation 4 above) to the zero angular frequency (equation 3 above) is given as follows: $\begin{array}{cc}\frac{{\omega }_P}{{\omega }_Z}=A_Z*r.& \text{(5)}\end{array}$

[0040] By adjusting the gain A_Zof amplifier AZ, a very effective and wide band zero for pole cancellation can be generated in the feedback system of switching regulator 300. Referring to equation (5) above, in a conventional feedback system without any “zero” amplification, i. e., when the gain A_Zis equal to 1, the ratio of the pole to zero angular frequency is equal to r and is approximately 2. On the other hand, in a feedback system employing zero generation circuit 310, even when amplifier AZ only has a modest gain of 10, a pole-to-zero frequency ratio of 20 can be obtained. Thus, the zero generation circuit of the present invention is effective in generating a zero with a much broader effective range than that can be obtained with the conventional compensation techniques.

[0041] FIG. 4 is a loop gain vs. frequency plot (in log scale) for the feedback system of the switching regulator of FIG. 3. FIG. 4 illustrates the effect on the loop gain vs. frequency behavior of switching regulator 300 after zero generation circuit 310 introduces a zero in the feedback system of the switching regulator. Referring to FIG. 4, the pole and zero of error amplifier 308 first diminishes the low frequency loop gain of switching regulator 300. At frequency f₁, the double-pole of LC filter circuit 11 takes effect. At high frequency, the zero introduced by zero generation circuit 310 (also called the “amplified zero”) takes effect. If the onset of the effect of the amplified zero is perfectly matched to the position of double-pole LC filter circuit 11, then the amplified zero will cancel out the effect of one of the double poles. As shown in FIG. 4, the zero-pole pair of the amplified zero is spread much further apart in frequency range than that of the conventional single zero capacitor compensation circuit as shown in FIG. 2b. The wide-range spacing of the zero-pole pair of circuit 310 allows for a wider design latitude either for optimizing compensation or for increasing loop gain. Zero generation circuit 310 of the present invention amplifies the effect of the zero of zero capacitor C_Z. The action of amplifier AZ introduces a zero having a wide range of effectiveness. Therefore, the placement of the zero in the feedback system is not as critical as in conventional systems. Consequently, zero generation circuit 310 has more tolerance for variations in capacitance values of capacitor C_Z. Zero generation circuit 310 improves the overall performance of switching regulator 300.

[0042] Amplifier AZ of zero generation circuit 310 is an open loop amplifier and can be implemented as any conventional gain stages known in the art. FIG. 5 is a circuit diagram of a zero generation circuit implemented using CMOS devices according to one embodiment of the present invention. Capacitors C_Band C_Zcan be implemented as any conventional capacitor structures and in the present embodiment, capacitors C_Band C_Zare MOS capacitors. Capacitor C_Zcan have a capacitance value between 1 to 5 picofarads while capacitor C_Bhas a capacitance value about one-fifth of capacitor C_Z. As described above, capacitor C_Bfunctions to block out the DC component of the output voltage V_OUTpresented at the circuit input node 520. Thus, the voltage V₁at the other side of capacitor C_B(node 501) is the AC component of the output voltage V_OUT. In the present embodiment, amplifier AZ is implemented as a two-stage gain block with self-biasing capability. The first gain stage includes a resistor R_ZIcoupled between nodes 501 and 505 and an NMOS transistor 506 biased by a current mirror. Resistor R_ZIand the gain of the first gain stage create the effective input impedance R_Z1of amplifier AZ. Resistor R_Z1can be implemented as a diffused resistor or a polysilicon resistor. In the present embodiment, resistor R_ZI, is a diffused resistor having a resistance value of approximately 400 kΩ. The current mirror of the first gain stage is implemented by PMOS transistor 502. The gate terminal of transistor 502 is coupled to a reference voltage V_Refpfor generating a reference current I_refpat the drain terminal (node 505) of transistor 502. The source terminal of transistor 502 is coupled to a power supply terminal 503 providing a supply voltage V_DD. NMOS transistor 506 has its gate terminal connected to node 501 and its drain and source terminals connected between node 505 and a ground node 509. Thus, transistor 506 amplifies the voltage V₁, and generates an output voltage V₂at node 505. The second gain stage of amplifier AZ includes an NMOS transistor 508 biased by a current mirror including a PMOS transistor 504. PMOS transistor 504 is connected in an analogous manner as PMOS transistor 502 and generates a reference current I_refpat the drain terminal (node 507) of transistor 504. NMOS transistor 508 has its gate terminal coupled to node 505 and amplifies the voltage V₂to provide an output voltage V₃at output node 507. The amplified voltage V₃is coupled to zero capacitor C_Z. The action of amplifier voltage V₃and zero capacitor C_Zintroduces a zero at a circuit output node 521 having more effectiveness than a zero introduced by conventional compensation circuits. In the present embodiment, PMOS transistors 502 and 504 are of the same sizes while NMOS transistors 506 and 508 are also of the same sizes. In one embodiment, PMOS transistors 502 and 504 each has a width of 20 μm and a length of 3μm. On the other hand, NMOS transistors 506 and 508 each has a width of 6 μm and a length of 2 μm.

[0043] The zero generation circuit of the present invention achieves advantages not obtainable in conventional compensation circuits. First, the zero generation circuit utilizes common circuit components and is simple to implement. Contrary to conventional compensation techniques where a closed loop amplifier is used to set the proper gain and phase for the zero function, the zero generation circuit of the present invention simply modulates the location or placement of the zero generated by a zero capacitor. When applied in a switching regulator controller, the zero generation circuit of the present invention is connected to the voltage divider already present in the controller and requires little modification of the overall controller design. The circuit of the present invention avoids adding complex and space consuming compensation circuits to the switching regulator controller as is done the prior art. Second, the zero generation circuit is small in size and thus, is cost effective to incorporate in any linear circuits. Because the capacitance of zero capacitor C_Zis amplified by the action of amplifier AZ, a small capacitor C_Zcan be used, resulting in a smaller circuit area in implementation. Through the use of CMOS devices and an open loop amplifier AZ, the zero generation circuit can be operated at very high frequency. Furthermore, the zero generated in the zero generation circuit of the present invention has effectiveness over a wide range of frequencies and thus the circuit can tolerate variations in manufacturing processes and fluctuations in the load impedance.

[0044] In the above embodiment, the zero generation circuit is incorporated in a controller for a fixed switching regulator having an internal voltage divider. As mentioned above, resistor R₁of the voltage divider in controller 330 is used to provide a resistive load to zero generation circuit 310 for introducing an effective zero at node 306. In another embodiment of the present invention, the zero generation circuit of the present invention can also be incorporated in a switching regulator controller for an adjustable switching regulator as illustrated in FIG. 6. Referring to FIG. 6, in an adjustable switching regulator 600, an external voltage divider, including resistors R_E1, and R_E2, are used for stepping down the output voltage V_OUT. The output of the voltage divider of resistors R_E1, and R_E2generates the feedback voltage V_FBto be coupled to switching regulator controller 630 on a feedback terminal 604 to form the feedback loop for regulating the output voltage V_SW. In conventional switching regulator controllers, the feedback voltage V_FBis coupled directly to error amplifier 608. However, in accordance with the present embodiment, a zero generation circuit 610 is incorporated into switching regulator controller 630 to generate an effective zero for compensating the double-pole of the LC filter circuit in the feedback system of adjustable switching regulator 600. In switching regulator controller 630, zero generation circuit 610 is coupled between feedback terminal 604 and a node 606 which is the inverting input terminal of error amplifier 608. The structure and operation of zero generation circuit 610 is the same as circuit 310 described above. Basically, capacitor C_Bblocks out the DC components of the feedback voltage V_FBand amplifier AZ amplifies the AC components of the feedback voltage and couples the amplified voltage signal to zero capacitor C_Z. In the case of the adjustable switching regulator, zero generation circuit 610 further includes a resistor R₁connected in parallel to the capacitors and amplifier circuit elements of the zero generation circuit (i. e. between node 604 and node 606). Resistor R₁is used to provide a resistive load to zero generation circuit 610 for introducing an effective zero at node 606. In the present embodiment, the resistance of resistor R₁is between 100 k to 200 k ohms. In one embodiment, resistor R₁of circuit 610 is the same resistor R₁in the voltage divider of switching regulator controller 330 of fixed switching regulator 300. Thus, controller 630 for an adjustable switching regulator can be built using the same circuit design as controller 330 for a fixed switching regulator except that, for controller 630, resistor R₂of the voltage divider of controller 330 is disconnected from node 606. Zero generation circuit 610 generates a wide band zero for effective pole-cancellation in the feedback system of switching regulator 600 and ensures that the switching regulator can achieve frequency stability in operation.

[0045] The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. For example, while the above descriptions describe incorporating the zero generating circuit of the present invention in a switching regulator controller, the zero generating circuit of the present invention can be incorporated in any linear circuits being operated in a closed loop feedback system to ensure frequency stability. Also, while the implementation of the zero generation circuit has been described using CMOS devices, the circuit can also be implemented using bipolar devices to provide the same frequency stabilizing result. Lastly, while in the present descriptions, the voltage divider of controller 330 includes two resistors R₁and R₂, a person of ordinary skill in the art would appreciate that the voltage divider can be implemented using any numbers of resistors to produce the desired divided voltage. The present invention is defined by the appended claims.