Silicon carbide semiconductor device and manufacturing method

[0002] This application relates to and claims priority to Japanese Patent Application Nos. 2001-137822 filed on May 8, 2001 and 2001-151594, filed on May 21, 2001, the contents of which are hereby incorporated by reference.

[0003] The present invention relates to a silicon carbide semiconductor device having a J-FET and a manufacturing method.

[0004] Efforts are underway to develop MOSFETs using SiC, but devices developed to date have not reached their full potential, because of inadequate mobility and reliability. On the other hand, it has been reported that normally-on J-FETs offer high voltage resistance and low on-resistance.

[0005] Such a semiconductor device, having a J-FET, is provided in, for example, U.S. Pat. No. 5,396,085. This semiconductor device operates as a normally-off transistor by having a combination of a normally-on J-FET made of SiC and an MOSFET made of silicon, having a low voltage resistance. This device is able to resist a small reverse bias voltage (low drain voltage) with the MOSFET made of silicon and to resist a large reverse bias voltage (high drain voltage) with a depletion layer extending out in the J-FET made of SiC.

[0006] This conventional semiconductor device, however, includes two types of semiconductor materials, which are silicon and SiC, and requires two chips. For this reason, this device has a large package and suffers from losses caused by wiring lines. Furthermore, this semiconductor device cannot operate at high temperature (for example, 200 degrees C. or above), because of the silicon MOSFET.

[0007] The present invention addresses this issue by providing a single chip, normally-off J-FET with low on-resistance. The objective of the present invention is to provide a silicon carbide semiconductor device that can operate at high temperature and a method of manufacturing such a device.

[0008] To achieve this objective, the invention is a silicon carbide semiconductor device, which includes a semiconductor substrate of a first conductance type made of silicon carbide, a semiconductor layer of the first conductance type made of silicon carbide of a higher resistance than the semiconductor substrate and formed on a main surface of the semiconductor substrate, first gate areas of a second conductance type formed on a surface of the semiconductor layer on both sides of a channel, which is formed in a prescribed area on the surface of the semiconductor layer, a channel layer of the first conductance type formed over the semiconductor layer and the first gate area, second gate areas of the second conductance type formed in isolation from the first gate area in the channel layer, high impurity concentration areas of the first conductance type formed in the channel layer, source areas of the first conductance type formed in positions above the first gate areas in the channel layer, a third gate area of the second conductance type formed above the channel layer or on the surface of the channel layer and having parts that face the second gate areas, source electrodes electrically connected to the first gate areas and the source areas, a gate electrode electrically connected to the third gate area, and a drain electrode formed on a backside of the semiconductor substrate.

[0009] FIG. 1 is a cross sectional diagram of the silicon carbide semiconductor device of the first embodiment of the present invention;

[0010] FIG. 2A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device in FIG. 1;

[0011] FIG. 2B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device in FIG. 1;

[0012] FIG. 3A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 2;

[0013] FIG. 3B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 3A;

[0014] FIG. 4A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 3;

[0015] FIG. 4B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 4A;

[0016] FIG. 5A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 4;

[0017] FIG. 5B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 5A;

[0018] FIG. 6A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 5;

[0019] FIG. 6B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 6A;

[0020] FIG. 7A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 6;

[0021] FIG. 7B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 7A;

[0022] FIG. 8A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 7;

[0023] FIG. 8B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 8A;

[0024] FIG. 9 is a cross sectional diagram showing the silicon carbide semiconductor device of the second embodiment of the present invention;

[0025] FIG. 10 is a cross sectional diagram showing the silicon carbide semiconductor device of the third embodiment of the present invention;

[0026] FIG. 11 is a cross sectional diagram showing the silicon carbide semiconductor device of the fourth embodiment of the present invention;

[0027] FIG. 12 is a cross sectional diagram showing the silicon carbide semiconductor device of the fifth embodiment of the present invention;

[0028] FIG. 13 is a cross sectional diagram showing the silicon carbide semiconductor device of the sixth embodiment of the present invention;

[0029] FIG. 14 is a cross sectional diagram showing the silicon carbide semiconductor device of the seventh embodiment of the present invention;

[0030] FIG. 15 is a cross sectional diagram showing the silicon carbide semiconductor device of the eighth embodiment of the present invention;

[0031] FIG. 16 is a cross sectional diagram showing the silicon carbide semiconductor device of the ninth embodiment of the present invention;

[0032] FIG. 17 is a cross sectional diagram showing the silicon carbide semiconductor device of the tenth embodiment of the present invention;

[0033] FIG. 18 is a cross sectional diagram showing the silicon carbide semiconductor device of the eleventh embodiment of the present invention;

[0034] FIG. 19A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device shown in FIG. 18;

[0035] FIG. 19B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device shown in FIG. 18;

[0036] FIG. 20A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 19;

[0037] FIG. 20B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 20A;

[0038] FIG. 21A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 20;

[0039] FIG. 21B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 21A;

[0040] FIG. 22A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 21;

[0041] FIG. 22B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 22A;

[0042] FIG. 23A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 22;

[0043] FIG. 23B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 23A;

[0044] FIG. 24A is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 23;

[0045] FIG. 24B is a cross sectional diagram showing a manufacturing process for the silicon carbide semiconductor device that follows FIG. 24A;

[0046] FIG. 25 is a cross sectional diagram showing the silicon carbide semiconductor device of the twelfth embodiment of the present invention;

[0047] FIG. 26 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirteenth embodiment of the present invention;

[0048] FIG. 27 is a cross sectional diagram showing the silicon carbide semiconductor device of the fourteenth embodiment of the present invention;

[0049] FIG. 28 is a cross sectional diagram showing the silicon carbide semiconductor device of the fifteenth embodiment of the present invention;

[0050] FIG. 29 is a cross sectional diagram showing the silicon carbide semiconductor device of the sixteenth embodiment of the present invention;

[0051] FIG. 30 is a cross sectional diagram showing the silicon carbide semiconductor device of the seventeenth embodiment of the present invention;

[0052] FIG. 31 is a cross sectional diagram showing the silicon carbide semiconductor device of the eighteenth embodiment of the present invention;

[0053] FIG. 32 is a cross sectional diagram showing the silicon carbide semiconductor device of the nineteenth embodiment of the present invention;

[0054] FIG. 33 is a cross sectional diagram showing the silicon carbide semiconductor device of the twentieth embodiment of the present invention;

[0055] FIG. 34 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-first embodiment of the present invention;

[0056] FIG. 35 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-second embodiment of the present invention;

[0057] FIG. 36 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-third embodiment of the present invention;

[0058] FIG. 37 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-fourth embodiment of the present invention;

[0059] FIG. 38 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-fifth embodiment of the present invention;

[0060] FIG. 39 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-sixth embodiment of the present invention;

[0061] FIG. 40 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-seventh embodiment of the present invention;

[0062] FIG. 41 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-eighth embodiment of the present invention;

[0063] FIG. 42 is a cross sectional diagram showing the silicon carbide semiconductor device of the twenty-ninth embodiment of the present invention;

[0064] FIG. 43 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirtieth embodiment of the present invention;

[0065] FIG. 44 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirty-first embodiment of the present invention

[0066] FIG. 45 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirty-second embodiment of the present invention;

[0067] FIG. 46 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirty-third embodiment of the present invention;

[0068] FIG. 47 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirty-fourth embodiment of the present invention;

[0069] FIG. 48 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirty-fifth embodiment of the present invention; and

[0070] FIG. 49 is a cross sectional diagram showing the silicon carbide semiconductor device of the thirty-sixth embodiment of the present invention.

[0071] First Embodiment

[0072] FIG. 1 shows a cross-section of a single cell in the silicon carbide semiconductor device. An n⁺-type substrate 1, consisting of silicon carbide, has a top, main and a bottom surface. The bottom surface is opposite to the main surface. An n⁻-type epitaxial layer 2, consisting of silicon carbide, is grown epitaxially on the main surface of the n⁺-type substrate 1. The n⁻-type epitaxial layer 2 has a lower dopant concentration than the substrate 1.

[0073] At prescribed areas at the surface of the n⁻-type epitaxial layer 2 are formed, symmetrically to the right and left in FIG. 1, first gate areas 3, each consisting of a p⁺-type layer. A channel layer 4, consisting of an n⁻-type layer, is grown epitaxially on the surface of the n⁻type epitaxial layer 2 and also covers the first gate areas 3. Field enhanced areas 5, each consisting of an n⁺-type layer, and second gate areas 6, each consisting of a p⁺-type layer, are formed at the surface of the channel layer 4 above the first gate areas 3.

[0074] A plurality of n⁺-type source areas 7 are formed above the second gate areas 6 at the surface of the channel layer 4. A third gate area 8 is formed at the surface of the channel layer 4 and covers the second gate areas 6.

[0075] Also formed in the channel layer 4 are grooves 9, which reach down to the second gate areas 6. Contact areas 10 are formed at the bottom of the grooves 9, and the contact areas 10 extend down to the first gate areas 3 to a level deeper than the field enhanced areas 5. The contact areas 10 provide electrical connection between the first gate areas 3 and the second gate areas 6.

[0076] Furthermore, source electrodes 11 are formed over the n⁺-type source areas 7 and contact areas 10 to establish electrical contacts with the n⁺-type source areas 7, as well as with the first gate areas 3 and second gate areas 6 via the contact areas 10. A gate electrode 12 is formed on top of the third gate area 8 for making electrical contact with the third gate area 8. The source electrodes 11 and gate electrode 12 are electrically isolated by the interlayer dielectric films 13. Formed on the back surface of the n⁺-type substrate 1 is a drain electrode 14, which is electrically connected to the n⁺-type substrate 1 to complete the structure of the silicon carbide semiconductor device.

[0077] The resulting silicon carbide semiconductor device includes a first J-FET, which includes the n⁺-type source areas 7 and the n⁺-type substrate 1 as source and drain and the first gate areas 3 on both sides of FIG. 1 as the gate, and a second J-FET, which includes the n⁺-type source areas 7 and the n⁺-type substrate 1 as source and drain and the second gate areas 6 and the third gate area 8 as the gate. With this embodiment, the first J-FET, out of the first and second J-FETs, operates as normally-on, while the second J-FET operates as normally-off. More particularly, a spacing between the first gate areas 3 on the right and left sides in FIG. 1 and the impurity concentration level in each part are set in such a way that the first J-FET operates as normally-on, while the spacing between the second and third gate areas 6 and 8 and the impurity concentration level in each part are set such that the second J-FET operates as normally-off.

[0078] Operation of the silicon carbide semiconductor device, as the device is turned off and turned on, will be described next.

[0079] Firstly, when the silicon carbide semiconductor device is turned off, or when a voltage is not applied to the gate electrode 12, depletion layers extending out of the second and third gate areas 6 and 8 pinch off the channel layer 4 and turn off the second J-FET. Although depletion layers also extend out of the first gate areas 3, the n⁻-type epitaxial layer 2 does not get pinched off, because the spacing between the right and left first gate areas 3 in FIG. 1 is larger than the distances by which these depletion layers extend. Consequently, the first J-FET remains turned on.

[0080] When a reverse bias is applied to the device and a positive voltage is applied to the drain electrode 14, the channel in the second J-FET remains depleted due to the normally-off design, even though the channel in the first J-FET is not be depleted because of the normally-on design. Consequently, the voltage applied to the drain electrode 14 will be blocked, as long as the voltage level is low,

[0081] As the voltage applied to the drain electrode 14 is gradually increased, the potential around the second gate areas 6 is increased. Because the field enhanced areas 5 are positioned below the second gate areas 6, the potential of the field enhanced areas 5 also goes up. Because the first gate areas 3 and the second gate areas 6 are connected to the source electrodes 11 and are grounded (potential=0 V), a reverse bias is applied between the field enhanced areas 5 and the first and second gate areas 3 and 6. Consequently, depletion layers from the first gate areas 3 stretch out and pinch off the channel in the first J-FET. Once the channel is pinched off, the potential no longer rises in the upper part of the first gate areas 3. Consequently, even when a higher voltage is applied to the drain electrode 14, the voltage is blocked by the first gate areas 3.

[0082] On the other hand, when the device is turned on, or when a voltage is applied to the gate electrode 12, a smaller depletion layer would stretch out of the third gate area 8, and the second J-FET is turned on. The first J-FET would also be turned on, because this J-FET is normally turned on. Because both the first and second J-FETs are turned on, currents would flow from the source electrodes 11 to the n⁺-type source areas 7, the channel layer 4, the n⁻-type epitaxial layer 2, the n⁺-type substrate 1, and the drain electrode 14 in that order.

[0083] The device structure of this embodiment, therefore, would operate as a normally-off transistor and can resist a reverse bias.

[0084] This silicon carbide semiconductor device is basically made of one type of semiconductor material, which is silicon carbide. For this reason, the silicon carbide semiconductor device can be built into a single chip and will not require a large package. The device does not suffer from losses due to wire conductance. Because the device is made of silicon carbide and does not rely on silicon, high temperature operation (at above 200 degrees C., for example) is possible.

[0085] A method of manufacturing the silicon carbide semiconductor device in FIG. 1 will be described by referring to FIG. 2 through FIG. 8.

[0086] Step Shown in FIG. 2A

[0087] Firstly, the n⁺-type substrate 1 should be an n-type 4H, 6H, 3C, or 15R SiC substrate. For example, the n⁺-type substrate 1 may be a 400 μm thick substrate, the main surface of which is a (0001) Si face or a (112-0) a face. A 5 μm thick n⁻-type epitaxial layer 2 is grown epitaxially on a main surface of the substrate 1. Because the n⁻-type epitaxial layer 2 would have the same crystal structure as the substrate 1 underneath, the crystal structure of this layer would be n⁻-type 4H, 6H, 3C, or 15 R-SiC.

[0088] Step Shown in FIG. 2B

[0089] After a low temperature oxide (LTO) film 20 is formed at prescribed areas on top of the n⁻-type epitaxial layer 2, the LTO film 20 is patterned by photo lithography to open holes at prescribed areas. Ion implanting is next performed using the LTO film 20 as a mask. More specifically, boron or aluminum is ion implanted as a p-type impurity at positions where the first gate areas 3 are to be formed.

[0090] Step Shown in FIG. 3A

[0091] After the LTO film 20 is stripped, implanted ions are activated with an anneal treatment in a furnace or by rapid thermal annealing to form the first gate areas 3. In order to keep the p-type impurities from diffusing, when forming these first gate areas 3, either aluminum, which does not diffuse too much under heat, or carbon and boron in an appropriate dose ratio (preferably 1:10 for boron:carbon) should be implanted in the step shown in FIG. 2B.

[0092] Step Shown in FIG. 3B

[0093] The channel layer 4, consisting of an n⁻-type film, is deposited by epitaxial growth on the n⁻-type epitaxial layer 2 to cover the first gate areas 3. In order to make the second J-FET operate as normally-off, impurity concentration level in the channel layer 4 should be lower than in the n⁻-type epitaxial layer 2.

[0094] Step Shown in FIG. 4A

[0095] After an LTO film 21 is grown on top of the channel layer 4, the LTO film 21 is patterned by photo lithography to open holes at prescribed areas. Using the LTO film 21 as a mask, ion implanting is performed. More specifically, boron or aluminum is ion implanted as a p-type impurity at positions where the second gate areas 6 are to be formed.

[0096] Step Shown in FIG. 4B

[0097] An oxide film 21ais deposited, while the LTO film 21 remains on the surface. Then, the oxide film 21ais etched to make the openings in the LTO film 21 smaller.

[0098] Step Shown in FIG. 5A

[0099] Using the oxide film 21aand LTO film 21 as a mask, ion implanting is performed. More specifically, phosphorous (P) or nitrogen (N) is implanted as an n-type impurity at positions where the field enhanced areas 5 are to be formed.

[0100] Step Shown in FIG. 5B

[0101] After the LTO film 21 and oxide film 21aare stripped, implanted ions are activated by an anneal treatment using a furnace or by rapid thermal annealing to form the field enhanced areas 5 and second gate areas 6. In order to keep the p-type impurities from diffusing too much as the second gate areas 6 are formed, either aluminum, which does not diffuse too much, or boron and carbon in an appropriate dose ratio (preferably 1:10 for boron:carbon) should be implanted during the step shown in FIG. 4A.

[0102] Step Shown in FIG. 6A

[0103] The third gate area 8, consisting of a p⁺-type layer, is formed by epitaxial growth with a high dosage of p-type impurities on the surface of the channel layer 4.

[0104] Step Shown in FIG. 6B

[0105] After forming an LTO film 22 on the third gate area 8, the LTO film 22 is patterned by photo lithography to open holes at prescribed areas. Using the LTO film 22 as a mask, etching is performed to form grooves 9. Grooves 9, for example, should be deep enough to reach the surface of the channel layer 4.

[0106] Step Shown in FIG. 7A

[0107] Using the LTO film 22 as a mask, ion implanting is performed. More specifically, phosphorous or nitrogen is ion implanted as an n-type impurity at positions where the n⁺-type source areas 7 are to be formed.

[0108] Step Shown in FIG. 7B

[0109] After growing an LTO film 23 over the third gate area 8 and n⁺-type source area 7, the LTO film 23 is patterned by photo lithography to open holes at prescribed areas. Etching is performed using the LTO film 23 as a mask to make the grooves 9 deep enough to reach the second gate areas 6.

[0110] Step Shown in FIG. 8A

[0111] Ion implanting is performed using the LTO film 23 as a mask. More specifically, aluminum or nitrogen is ion implanted as a p-type impurity at areas where the contact areas 10 are to be formed.

[0112] Step Shown in FIG. 8B

[0113] After the LTO film 23 is stripped, implanted ions are activated by an anneal treatment in a furnace or by rapid thermal annealing to form the contact areas 10. In order to prevent the p-type impurities from diffusing too much as the contact areas 10 are formed, either aluminum, which does not diffuse easily, or an appropriate ratio of boron and carbon (preferably 1:10 for boron:carbon) should be implanted in the step shown in FIG. 8A to prevent excessive thermal diffusion.

[0114] In the steps described so far, each impurity was activated one at a time. It is also possible to activate all impurities at once in the step shown in FIG. 8B. This will simplify the manufacturing process. It is also possible to activate two or more implanted impurities simultaneously to simplify the manufacturing process, without activating all impurities at once in this step.

[0115] The steps that would follow are not shown in the figures but would include a step for forming the interlayer dielectric film 13 on the substrate surface, and a step for forming the contact holes that connect the third gate area 8 and the n⁺-type source areas 7 by patterning the interlayer dielectric film 13. Then, an electrode layer is deposited on the interlayer dielectric film 13, and the electrode layer is patterned to form the source electrodes 11 and the gate electrode 12. Finally, the drain electrode 14 is formed on the substrate backside to complete the J-FET shown in FIG. 1.

[0116] Second Embodiment

[0117] FIG. 9 shows a cross-sectional view of the silicon carbide semiconductor device in the second embodiment of the present invention. While the third gate area 8 was formed by epitaxial growth in the first embodiment, it is also possible to form the third gate area 8 by ion implanting p-type impurities into the channel layer 4, as shown in FIG. 9. Furthermore, while the grooves 9 are first formed and contact areas 10 are then formed at the bottom of the grooves 9 in the first embodiment, it is also possible to form the contact areas 10 directly on the surface of the channel layer 4 as shown in FIG. 9. The silicon carbide semiconductor device of this structure would also operate in the same way as the device in the first embodiment and provide similar effects as the device in the first embodiment.

[0118] Furthermore, the silicon carbide semiconductor device of such a structure can be manufactured by ion implanting p-type impurities in areas where the contact areas 10 are to be formed when p-type impurities are ion implanted at an area where the third gate area 8 is to be formed in the step shown in FIG. 4A.

[0119] Third Embodiment

[0120] FIG. 10 shows a cross-sectional view of the silicon carbide semiconductor device of the third embodiment of the present invention. While the field enhanced areas 5 in FIG. 1 are placed to the right and left of the device in isolation from each other in the first embodiment, it is also possible, as shown in FIG. 10, to have the field enhanced areas 5 connected with each other, so that the field enhanced area 5 would stretch across an area of resistance in the J-FET.

[0121] Such a layout would make it possible to reduce the J-FET resistance and further reduce the on-resistance of the silicon carbide semiconductor device.

[0122] Fourth Embodiment

[0123] FIG. 11 shows a cross-sectional view of the silicon carbide semiconductor device in the fourth embodiment of the present invention. While the field enhanced area 5 is placed near the contact areas 10 to the right and left of the device in the third embodiment, it is also possible to have more space between the field enhanced area 5 and the contact areas 10, as shown in FIG. 11. Such a device structure would also yield similar effects as the device in the third embodiment. However, it is still necessary to have the field enhanced area 5 be placed between the first gate areas 3 and the second gate areas 6.

[0124] Fifth Embodiment

[0125] FIG. 12 shows a cross-sectional view of the silicon carbide semiconductor device in the fifth embodiment of the present invention. As shown in FIG. 12, in this embodiment the field enhanced areas 5 in the device of the first embodiment are eliminated, and an area between the first gate areas 3 and second gate areas 6 inside the channel layer 4 has a higher level of impurity concentration than other parts (for example, an area that makes up the channel of the second J-FET).

[0126] Even with this structure, the area of high level of impurity concentration between the first gate areas 3 and the second gate areas 6 in the channel layer 4 would function similarly to the field enhanced areas 5 to yield similar effects as the device in the first embodiment.

[0127] Sixth Embodiment

[0128] FIG. 13 shows a cross-sectional view of the silicon carbide semiconductor device of the sixth embodiment of the present invention. As shown in FIG. 13, the device in this embodiment includes low impurity concentration contact areas 10a, formed by diffusion from the contact areas 10 during a thermal treatment. This device structure is different from the device in the first embodiment in that the second gate areas 6 are electrically connected to the source electrodes 11 through these low impurity concentration contact areas 10a.

[0129] It is possible to obtain a silicon carbide semiconductor device offering similar effects as the device in the first embodiment by forming the low impurity concentration contact areas 10aby diffusion from the contact areas 10.

[0130] On the other hand, low impurity concentration contact areas 10aand field enhanced areas 5 can come into contact sometimes. Even in such instances, the PN junction can resist voltage because the low impurity concentration contact areas 10ais placed between the PN junction made of the p⁺-type contact areas 10 and the n⁺-type field enhanced areas 5.

[0131] As far as the method of manufacturing the silicon carbide semiconductor device in this embodiment, only a step for thermal diffusion needs to be added after ion implanting in the first embodiment for forming the contact areas 10. Other manufacturing steps remain the same as the first embodiment.

[0132] In the first embodiment, the second gate areas 6 are in contact with the contact areas 10 but not in contact with the field enhanced areas 5. Different masks are used for the second gate areas 6 and the field enhanced areas 5, so that the field enhanced areas 5 would be further away from the contact areas 10 than the second gate areas 6 are. With the device structure in the present embodiment, however, it is not necessary to have the field enhanced areas 5 be further away from the contact areas 10 than the second gate areas 6 are. Therefore, it is possible to use the same mask for forming both the second gate areas 6 and the field enhanced areas 5.

[0133] Seventh Embodiment

[0134] FIG. 14 shows a cross-sectional view of the silicon carbide semiconductor device in the seventh embodiment of the present invention. As shown in FIG. 14, this embodiment differs from the first embodiment in that the second gate areas 6 are isolated from the contact areas 10, and the second gate areas 6 are in a floating state. Because the second gate areas 6 are floating, it is possible to have the depletion layers also extend from the second gate areas 6 to further improve resistance to voltage.

[0135] Although the second gate areas 6 may be in a floating state, the second gate areas 6 may also be at the same potential as the third gate area 8. For example, it is possible to have the second gate areas 6 extend to the outside of the cell and be in contact with the third gate area 8. With such a structure, it would be possible to drive the second gate areas 6 at the same time as the third gate area 8 and simultaneously shrink the depletion layers extending from the areas 6 and 8 to further reduce the on resistance.

[0136] Whether, as described above, the second gate areas are in the floating state or at the same potential as the third gate area 8, the silicon carbide semiconductor device can be manufactured using the same method as the first embodiment. However, because the second gate areas 6 and the contact areas 10 are not in contact in the present embodiment, the same mask can be used for forming both the second gate areas 6 and the field enhanced areas 5.

[0137] Eighth Embodiment

[0138] FIG. 15 shows a cross-sectional view of the silicon carbide semiconductor device of the eighth embodiment of the present invention. As shown in FIG. 15, the present embodiment differs from the first embodiment in that the field enhanced area 5 is placed between the neighboring second gate areas 6. Such a device structure would yield similar effects as the first embodiment, while reducing the J-FET resistance between the second gate areas 6 and reduce the on resistance.

[0139] The manufacturing method for the silicon carbide semiconductor device in the present embodiment is similar to the first embodiment, except that the mask patterns used for forming the field enhanced areas 5 in the first embodiment must be modified, and ion implanting conditions must also be modified.

[0140] Ninth Embodiment

[0141] FIG. 16 shows a cross-sectional view of the silicon carbide semiconductor device in the ninth embodiment of the present invention. As shown in FIG. 16, the present embodiment differs from the first embodiment in that the field enhanced area 5 lays across the entire cell, and the first gate areas 3 are electrically connected to the source electrodes 11 at outside of the cell, instead of by the contact areas 10 shown in FIG. 1. This device structure offers similar effects as the first embodiment.

[0142] The method of manufacturing the silicon carbide semiconductor device in the present embodiment is similar to the first embodiment except that the step for forming the contact areas 10 is no longer needed. Similar to the first embodiment, the field enhanced area 5 may be formed by ion implanting. It is also possible to form the field enhanced area 5 by epitaxial growth.

[0143] Tenth Embodiment

[0144] FIG. 17 shows a cross-sectional view of the silicon carbide semiconductor device in the tenth embodiment of the present invention. As shown in FIG. 17, in this embodiment, the first gate area 3 is formed differently compared with the ninth embodiment. More particularly, the first gate area 3 is placed to block the lower part of the J-FET area of the second J-FET, and the edges of the first gate area 3 are beneath the areas where the second gate areas 6 and the source electrodes 11 come into contact, making these areas act as a channel for the first J-FET.

[0145] In this device structure, (voltage) potential of the n⁻-type epitaxial layer 2 extends toward the channel area of the second J-FET through a passage formed between the first gate area 3 and the second gate areas 6. Because the potential must travel across a larger distance before reaching the channel area of the second J-FET, the potential is less likely to directly hit the channel area of the second J-FET. As a result, voltage resistance improves.

[0146] With the device structure in the present embodiment, currents between the source and drain must also travel over a longer distance. However, impact on the on resistance would be negligible, because the field enhanced area 5 with a high level of impurity concentration is formed in the area where this distance would be longer compared with the ninth embodiment.

[0147] The method of manufacturing the silicon carbide semiconductor device in the present embodiment would be similar to the ninth embodiment except that the mask patterns for forming the first gate area 3 need to be modified.

[0148] Eleventh Embodiment

[0149] FIG. 18 shows a cross-sectional view of the silicon carbide semiconductor device in the eleventh embodiment of the present invention. In this embodiment, one of the embodiments of the present invention is applied to a silicon carbide semiconductor device having a trench single gate drive J-FET.

[0150] As shown in FIG. 18, a trench 30 is formed to penetrate between the n⁺-type source areas 7 and reach the second gate areas 6, which are next to each other. The third gate area 8 is formed on the inner walls of the trench 30, and the gate electrode 12 is formed on the surface of the third gate area 8 inside the trench 30. The field enhanced area 5 is formed beneath the trench 30 in the channel layer 4. Other parts of the device structure are similar to the first embodiment.

[0151] A silicon carbide semiconductor device with this trench J-FET would operate similarly to the device in the first embodiment, providing similar effects.

[0152] The method of manufacturing the silicon carbide semiconductor device in FIG. 18 is shown in FIG. 19 through FIG. 24. The method of manufacturing the silicon carbide semiconductor device will be described using these figures. Parts of the method of manufacturing that are similar to the first embodiment, however, will not be described and will reference the FIG. 2 through FIG. 8.

[0153] The steps shown in FIG. 19A through FIG. 21A are similar to the steps shown in FIG. 2A through FIG. 4A for the first embodiment. After forming an n⁻-type epitaxial layer 2 on an n⁺-type substrate 1, the first gate areas 3 are formed at the surface of the n⁻-type epitaxial layer 2, the channel layer 4 is formed at the surface of the n⁻-type epitaxial layer 2, and the second gate areas 6 are formed at the middle-layer part of the channel layer 4. The steps shown in FIG. 21B then follow.

[0154] Steps Shown in FIG. 21B

[0155] After forming an LTO film 24 on the channel layer 4, the LTO film 24 is patterned by photo lithography to open holes at prescribed areas. Using the LTO film 24 as a mask, ion implanting is next performed. More specifically, phosphorous or a combination of phosphorous and nitrogen are ion implanted as an n-type impurity into areas where the n⁺-type source areas 7 are to be formed.

[0156] The LTO film 24 is next stripped, and implanted ions are activated with an anneal treatment in a furnace or by rapid thermal annealing to form the n⁺-type source areas 7.

[0157] Steps Shown in FIG. 22A

[0158] An LTO film 25 is formed on top of the channel layer 4 to also cover the n⁺-type source areas 7. The LTO film 25 is patterned by photo lithography to open holes at prescribed areas. Etching is performed using the LTO film 25 as a mask. Trench 30 is thus formed to penetrate between the n⁺-type source areas 7, reach down to the depth of the second gate areas 6, and wedge between the neighboring second gate areas 6.

[0159] Steps Shown in FIG. 22B

[0160] Next, the LTO film 25 is used again as a mask for ion implanting to implant phosphorous or a combination of phosphorous and nitrogen as an n-type impurity into an area below the trench 30 in the channel layer 4. Next, the LTO film 25 is stripped, and implanted ions are activated with an anneal treatment in a furnace or by rapid thermal annealing to form the field enhanced area 5.

[0161] Steps Shown in FIG. 23A

[0162] After forming a p⁺-type layer by epitaxial growth inside the trench 30 and on the channel layer 4, the surface of this film is planarized by chemical mechanical polishing to leave the third gate area 8 behind in the trench 30. Although the third gate area 8 is grown epitaxially in this step, it is also possible to form this area by ion implanting.

[0163] Steps Shown in FIG. 23B

[0164] An LTO film 26 is formed over the third gate area 8 and the channel layer 4. The LTO film 26 is then patterned by photo lithography to open holes at prescribed areas. Next, grooves 9, reaching down to the second gate areas 6, are formed by etching using the LTO film 26 as a mask.

[0165] Steps Shown in FIG. 24A

[0166] Using the LTO film 26 as a mask again, boron (B) or aluminum (Al) is ion implanted as a p-type impurity to penetrate through the channel layer 4 at the bottom surface of the grooves 9 and deep enough to reach surface of the first gate areas 3. Then, after the LTO film 26 is stripped, contact areas 10 are formed by activating the implanted ions with an anneal treatment in a furnace or by rapid thermal annealing.

[0167] If it is necessary to keep the p-type impurities from diffusing too much, as the contact areas 10 are formed, then either aluminum, which does not diffuse much, or an appropriate ratio of boron and carbon (preferably 1:10 for boron:carbon) should be implanted in this step to prevent too much diffusion.

[0168] The ensuing steps will not reference any figures. Firstly, an interlayer dielectric film 13 is deposited on the substrate surface, and the interlayer dielectric film 13 is patterned to form contact holes that connect to the third gate area 8 and the n⁺-type source areas 7. After depositing an electrode layer on the interlayer dielectric film 13, the electrode layer is patterned to form the source electrodes 11 and gate electrode 12. Furthermore, the drain electrode 14 is formed on the backside of the substrate to complete the J-FET structure shown in FIG. 1.

[0169] Twelfth Embodiment

[0170] FIG. 25 shows a cross-sectional view of the silicon carbide semiconductor device in the twelfth embodiment of the present invention. The device structure in this embodiment combines the trench J-FET in the eleventh embodiment and the structure of the field enhanced area 5 in the ninth embodiment. Such a device structure would yield similar effects as the eleventh embodiment.

[0171] A method of manufacturing the silicon carbide semiconductor device in this embodiment is similar to the eleventh embodiment except for the step for forming the contact areas 10, which is eliminated. The field enhanced area 5 may be formed by ion implanting as in the eleventh embodiment, but the field enhanced area 5 may also be formed by epitaxial growth.

[0172] Thirteenth Embodiment

[0173] FIG. 26 shows a cross-sectional view of the silicon carbide semiconductor device in the thirteenth embodiment of the present invention. The device structure in this embodiment combines the trench J-FET in the eleventh embodiment and the layout of the first gate areas 3 in the tenth embodiment. With this structure, effects similar to the tenth embodiment are achieved with the trench J-FET shown in the eleventh embodiment.

[0174] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the eleventh embodiment except that the mask patterns for forming the first gate area 3 need to be modified.

[0175] Fourteenth Embodiment

[0176] FIG. 27 shows a cross-sectional view of the silicon carbide semiconductor device of the fourteenth embodiment of the present invention. In this embodiment, the second gate areas 6 of the trench J-FET, shown in the twelfth embodiment, are formed by epitaxial growth. In this silicon carbide semiconductor device, an n⁻-type layer 31 is formed inside the trench, and the third gate area 8 is formed on top of this n⁻-type layer 31.

[0177] In this device structure, the second J-FET operates with the n⁻-type layer 31, positioned between the second and third gate areas 6 and 8, as a channel area, to yield similar effects as the device in the eleventh embodiment.

[0178] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the twelfth embodiment. However, once the second gate areas 6 are grown epitaxially, the trench 30 is formed to penetrate between the second gate areas 6, the n⁻-type layer 31 is formed inside this trench 30, and the third gate area 8 is then formed.

[0179] Fifteenth Embodiment

[0180] FIG. 28 shows a cross-sectional view of the silicon carbide semiconductor device of the fifteenth embodiment of the present invention. The device structure in this embodiment combines the trench J-FET of the fourteenth embodiment and the layout of the third gate area 3 of the tenth embodiment.

[0181] With this device structure, effects similar to the tenth embodiment are obtained with the trench J-FET in the fourteenth embodiment.

[0182] A method of manufacturing the silicon carbide semiconductor device of this embodiment is similar to the fourteenth embodiment, except that the mask patterns for forming the first gate areas 3 need to be modified.

[0183] Sixteenth Embodiment

[0184] FIG. 29 shows a cross-sectional view of the silicon carbide semiconductor device of the sixteenth embodiment of the present invention. The device structure in this embodiment combines the trench J-FET in the eleventh embodiment with the structure in the fifth embodiment, in which the field enhanced areas 5 are eliminated, and instead the area in the channel layer 4 sandwiched between the first and second gate areas 3 and 6 has a higher level of impurity concentration than other areas.

[0185] This device structure would yield similar effects as the eleventh embodiment. A method of manufacturing the silicon carbide semiconductor device of this structure is similar to the eleventh embodiment, except that the step for forming the field enhanced areas 5, required in the eleventh embodiment, is eliminated.

[0186] In this structure, the area in the channel layer 4 is located between the first and second gate areas 3 and 6 has a higher level of impurity concentration than other parts. The impurity concentration in this part is determined by the distance between the adjacent first gate areas 3. The effects described above can also be obtained by adjusting this distance but having the same level of impurity concentration throughout the entire channel layer 4.

[0187] Seventeenth Embodiment

[0188] FIG. 30 shows a cross-sectional view of the silicon carbide semiconductor device in the seventeenth embodiment of the present invention. With this embodiment, one of the embodiments of the present invention is applied to a planar double-gate drive J-FET.

[0189] As shown in FIG. 30, the grooves 9 have steps, and grooves 9 penetrate through the second gate areas 6. Contact areas 10 are formed at the bottom of the grooves 9. In other words, contact areas 10 are isolated from the second gate areas 6, and only the first gate areas 3 are connected to the contact areas 10. First, second, and third gate electrodes 41, 42, 43, respectively, are connected separately to the first, second, and third gate areas 3, 6, 8, respectively. The first gate electrodes 41 are connected to the source electrodes 11 and ground, and the second gate electrodes 42 and third gate electrode 43 are connected together to simultaneously control the potential of the second and third gate areas 6 and 8. The structure of this device is otherwise similar to the first embodiment.

[0190] This device structure enables double-gate drive for controlling the extension of depletion layers from both the second and third gate areas 6 and 8 by applying a bias on the second and third gate areas 6 and 8. The silicon carbide semiconductor device having such a double-gate drive J-FET also provides similar effects as the first embodiment.

[0191] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the first embodiment. After the step for forming the grooves 9 shown in the first embodiment, another mask is formed with prescribed patterns, followed by an etching step using that mask to have the grooves 9 penetrate through the second gate areas 6. Finally, contact areas 10 are formed.

[0192] Eighteenth Embodiment

[0193] FIG. 31 shows a cross-sectional view of the silicon carbide semiconductor device of the eighteenth embodiment of the present invention. In this embodiment, grooves 9 are made even deeper than in the seventeenth embodiment, so that the first gate electrodes 41 would come into direct contact with the first gate areas 3, without the contact areas 10 shown in FIG. 30. This device structure yields similar effects as the device in the seventeenth embodiment.

[0194] A manufacturing method for this silicon carbide semiconductor device is similar to the seventeenth embodiment, except that the grooves 9 are etched deep enough to reach the first gate areas 3 during the etching step for the grooves 9, and the step for forming the contact areas 10, described earlier, is eliminated.

[0195] Nineteenth Embodiment

[0196] FIG. 32 shows a cross-sectional view of the silicon carbide semiconductor device of the nineteenth embodiment of the present invention. As in the third embodiment, the device structure of this embodiment has the field enhanced area 5 placed in the device structure of the seventeenth embodiment in such a way that the field enhanced area 5 functions as a resistor component of the J-FET. This structure yields similar effects as the third embodiment on the J-FET described in the seventeenth embodiment.

[0197] A manufacturing method of this silicon carbide semiconductor device is similar to the seventeenth embodiment, except for a modification in the mask patterns for forming the field enhanced area 5.

[0198] Twentieth Embodiment

[0199] FIG. 33 shows a cross-sectional view of the silicon carbide semiconductor device of the twentieth embodiment of the present invention. This embodiment combines the device structure of the seventeenth embodiment with the field enhanced area 5, as in the fourth embodiment, which is positioned only in an area where the field enhanced area 5 would function as a resistive component of the J-FET. This device structure offers similar effects as the fourth embodiment in the J-FET of the seventeenth embodiment.

[0200] A method of manufacturing this silicon carbide semiconductor device is similar to the seventeenth embodiment except for a modification in the mask patterns for forming the field enhanced area 5.

[0201] Twenty-First Embodiment

[0202] FIG. 34 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-first embodiment of the present invention. With this embodiment, the device structure of the seventeenth embodiment is combined with the device structure of the fifth embodiment, in which the field enhanced area 5 is eliminated, and an area sandwiched between the first and second gate areas 3 and 6 in the channel layer 4 has a higher level of impurity concentration than other areas.

[0203] This device structure yields similar effects as the device structure in the seventeenth embodiment. A method of manufacturing this silicon carbide semiconductor device is similar to the seventeenth embodiment, except that the step for forming the field enhanced area 5 is eliminated.

[0204] Twenty-Second Embodiment

[0205] FIG. 35 shows a cross-sectional view of the silicon carbide semiconductor device in the twenty-second embodiment of the present invention. With this embodiment, the device structure in the seventeenth embodiment is combined with the device structure in the eighth embodiment in which the field enhanced area 5 is placed between the neighboring second gate areas 6. This device offers similar effects as the seventeenth embodiment while reducing the J-FET resistance between the second gate areas 6 and reducing the on resistance.

[0206] A method of manufacturing this silicon carbide semiconductor device in this embodiment is similar to the seventeenth embodiment, except for a modification in the mask patterns for forming the field enhanced area 5 and a modification in the ion implanting conditions.

[0207] Twenty-Third Embodiment

[0208] FIG. 36 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-third embodiment of the present invention. The device structure in this embodiment combines the device structure in the seventeenth embodiment with the device structure in the ninth embodiment, in which the field enhanced area 5 is formed across the entire cell, and the first gate areas 3 and source electrodes 11 are electrically connected at outside of the cell. This device structure yields similar effects as the seventeenth embodiment. Also in this structure the first gate electrodes, which are in contact with the first gate areas 3, are placed outside of the cell, and the first gate electrodes and the source electrodes 11 are connected at outside the cell.

[0209] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the seventeenth embodiment, except that the step for forming the contact areas 10 is eliminated. The field enhanced area 5 may be formed by ion implanting, in a way similar to the seventeenth embodiment, but the field enhanced area 5 may also be formed by epitaxial growth.

[0210] Twenty-Fourth Embodiment

[0211] FIG. 37 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-fourth embodiment of the present invention. The device structure in this invention combines the device structure of the seventeenth embodiment and the layout of the first gate areas 3 in the tenth embodiment. The resulting structure yields similar effects as the tenth embodiment on the J-FET of the seventeenth embodiment.

[0212] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the seventeenth embodiment, except for a modification in the mask patterns for forming the first gate areas 3.

[0213] Twenty-Fifth Embodiment

[0214] FIG. 38 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-fifth embodiment of the present invention. This embodiment applies one of the embodiments of the present invention on a silicon carbide semiconductor device having a trench, double-gate drive J-FET and is comparable to the transformation of the trench, single-gate drive J-FET of the eleventh embodiment into the double-gate drive structure of the eighteenth embodiment.

[0215] In other words, the device structure of this embodiment differs from the device structure of the eleventh embodiment in that the grooves 9 reach down to the first gate areas 3; the first, second, and third gate areas 3, 6, and 8, respectively, are connected separately to the first, second, and third gate electrodes 41, 42, and 43, respectively; the first gate electrode 41 is connected to the source electrode 11 and is grounded; and the second gate electrodes 42 and the third electrodes 43 are connected to each other and able to control the potential levels of the second and third gate areas 6 and 8. In other respects, the device structure of the present embodiment is similar to the eleventh embodiment.

[0216] The silicon carbide semiconductor device having the double-gate drive J-FET structure offers similar effects as the first embodiment.

[0217] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the eleventh embodiment, except that, after a step for forming the grooves 9 shown in the eleventh embodiment (shown in FIG. 23B), another mask with prescribed patterns is formed, and etching is performed using this mask to make the grooves 9 penetrate through the second gate areas 6.

[0218] Twenty-Sixth Embodiment

[0219] FIG. 39 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-sixth embodiment of the present invention. The device structure of this embodiment has a wider field enhanced area 5 compared with the twenty-fifth embodiment. This device structure yields similar effects as the twenty-fifth embodiment.

[0220] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the twenty-fifth embodiment, except that the field enhanced area 5 is formed by ion implanting using a mask with prescribed patterns after the channel layer 4 is formed.

[0221] Twenty-Seventh Embodiment

[0222] FIG. 40 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-seventh embodiment of the present invention. The device structure of this embodiment combines the device structure of the twelfth embodiment and the double-gate structure of the twenty-fifth embodiment. The resulting double-gate structure, similar to the twelfth embodiment, offers similar effects as the device structure of the twelfth embodiment. In this structure, the first gate electrodes that are in contact with the first gate areas 3 are placed outside of the cell, and the first gate electrodes and the source electrodes 11 are connected at outside of the cell.

[0223] Twenty-Eighth Embodiment

[0224] FIG. 41 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-eighth embodiment of the present invention. The device structure of this embodiment combines the device structure of the thirteenth embodiment and the double-gate structure of the twenty-fifth embodiment. This device structure offers a double-gate structure similar to the thirteenth embodiment and offers effects that are similar to the thirteenth embodiment. In this device structure, the first gate electrodes in contact with the first gate areas 3 are also outside of the cell, and the first gate electrodes and source electrodes 11 are connected at outside of the cell.

[0225] Twenty-Ninth Embodiment

[0226] FIG. 42 shows a cross-sectional view of the silicon carbide semiconductor device of the twenty-ninth embodiment of the present invention. The device structure of this embodiment combines the device structure of the fourteenth embodiment and the double-gate structure of the twenty-fifth embodiment. This device structure offers a double-gate structure similar to the fourteenth embodiment and offers the same effects as the fourteenth embodiment. The first gate electrodes connected to the first gate areas 3 are also outside of the cell, and the first gate electrodes are connected to the source electrodes 11 at outside of the cell.

[0227] Thirtieth Embodiment

[0228] FIG. 43 shows a cross-sectional view of the silicon carbide semiconductor device of the thirtieth embodiment of the present invention. The device structure of this embodiment combines the device structure of the fifteenth embodiment and the double-gate structure of the twenty-fifth embodiment. This device structure offers a double-gate structure similar to the fifteenth embodiment and offers the same effects as the fifteenth embodiment. The first gate electrodes connected to the first gate areas 3 are also at the outside of the cell, and the first gate electrodes are connected to the source electrodes 11 at outside of the cell.

[0229] Thirty-First Embodiment

[0230] FIG. 44 shows a cross-sectional view of the silicon carbide semiconductor device of the thirty-first embodiment of the present invention. This embodiment applies one of the embodiments of the present invention on the silicon carbide semiconductor device having a single-gate J-FET. This silicon carbide semiconductor device is described and compared with the silicon carbide semiconductor device in FIG. 30.

[0231] As shown in FIG. 44, in this embodiment, spacing between the neighboring second gate areas 6 is much smaller than in FIG. 30. Furthermore, the n⁺-type source area 7 in this embodiment is placed where the third gate area 8 is located in FIG. 30, and the third gate area 8 is eliminated. In addition, the first gate areas 3 are connected to the source electrodes 11 through the first gate electrodes 41 and to the ground, and the second gate areas 6 are driven through the second gate electrodes 42.

[0232] This device structure includes a vertical J-FET, the channel of which, formed between neighboring second gate areas 6, is controlled by the distance by which depletion layers from the second gate areas 6 extend. This vertical J-FET is comparable to the second J-FET of the various embodiments discussed earlier.

[0233] This silicon carbide semiconductor device, which has a double-gate structure, the first and second J-FETs of which are both vertical J-FETs, has effects similar to those of the first embodiment.

[0234] A method of manufacturing this silicon carbide semiconductor device is similar to the method of the seventeenth embodiment. After the second gate areas 6 and field enhanced areas 5 are formed in the channel layer 4, an n⁺-type source area 7 is formed by depositing an n⁺-type layer on the surface of the channel layer 4.

[0235] Thirty-Second Embodiment

[0236] FIG. 45 shows a cross-sectional view of the silicon carbide semiconductor device of the thirty-second embodiment of the present invention. The device structure of the present embodiment has a wider stretching field enhanced area 5 compared with the thirty-first embodiment. This device structure has effects similar to those of the thirty-first embodiment.

[0237] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the method of the thirty-first embodiment, except for a modification in the mask patterns for forming the field enhanced area 5.

[0238] Thirty-Third Embodiment

[0239] FIG. 46 shows a cross-sectional view of the silicon carbide semiconductor device of the thirty-third embodiment of the present invention. The device structure of this embodiment combines the device structures of the thirty-first embodiment and the ninth embodiment. In other words, the field enhanced area 5 spreads across the entire cell, and the first gate areas 3 are electrically connected to the source electrodes 11 at outside of the cell. This device structure has effects similar to those of the device of the thirty-first embodiment.

[0240] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the thirty-first embodiment, except that the step for forming the contact areas 10 is eliminated. The field enhanced area 5 may be formed by ion implanting as in the thirty-first embodiment or by epitaxial growth.

[0241] Thirty-Fourth Embodiment

[0242] FIG. 47 shows a cross-sectional view of the silicon carbide semiconductor device of the thirty-fourth embodiment of the present invention. The device structure in this embodiment combines the device structure in the thirty-first embodiment and the layout of the first gate electrodes 3 in the tenth embodiment. This device structure offers a J-FET structure of the thirty-first embodiment with the effects similar to the tenth embodiment.

[0243] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the thirty-first embodiment, except for a modification in the mask patterns for forming the first gate areas 3.

[0244] Thirty-Fifth Embodiment

[0245] FIG. 48 shows a cross-sectional view of the silicon carbide semiconductor device of the thirty-fifth embodiment of the present invention. The device structure of this embodiment combines the device structure of the thirty-first embodiment with the field enhanced area of the fourth embodiment, which is positioned only at a spot where the field enhanced area 5 functions as a resistor component of the J-FET. This device structure offers similar effects on the J-FET of the thirty-first embodiment as those of the fourth embodiment.

[0246] A method of manufacturing the silicon carbide semiconductor device of the present embodiment is similar to the thirty-first embodiment, except for a modification in the mask patterns for forming the field enhanced area 5.

[0247] Thirty-Sixth Embodiment

[0248] FIG. 49 shows a cross-sectional view of the silicon carbide semiconductor device of the thirty-sixth embodiment of the present invention. The device structure of this embodiment combines the device structure of the thirty-first embodiment with the device structure of the fifth embodiment, in which the field enhanced area 5 is eliminated, and an area sandwiched between the first and second gate areas 3 and 6 in the channel layer 4 has a higher level of impurity concentration than other areas. This structure offers similar effects on the J-FET of the thirty-first embodiment as those of the fifth embodiment.

[0249] A method of manufacturing the silicon carbide semiconductor device of this embodiment is similar to the thirty-first embodiment, except that the step for forming the field enhanced area 5 is eliminated.

[0250] Other Embodiments

[0251] Silicon carbide semiconductor devices having a single-gate structure, the first and second gate areas 3 and 6 of which are at the same potential as the n⁺-type source areas 7, were described in the various embodiments above. The silicon carbide semiconductor devices may also have a double-gate structure, the potential levels for the first and second gate areas 3 and 6 of which are controlled independently of the n⁺-type source areas 7.

[0252] Furthermore, impurity concentration levels in the drift area 2 and the channel layer 4 may be controlled independently. This would make it easier to design normally-on and normally-off FETs. Various n-channel silicon carbide semiconductor devices were described in the embodiments above. The present invention, of course, would also be applicable to silicon carbide semiconductor devices in which the conductance types in the various parts are reversed from those illustrated.