Silicon carbide vertical MOSFET and method for manufacturing the same

[0002] This is a Division of application Ser. No. 09/027,305 filed Feb. 20, 1998 now U.S. Pat. No. 6,054,352.

[0003] The present invention relates to power semiconductor devices, in particular, vertical MOSFETS having MOS type gates, which use silicon carbide as a semiconductor material, and a method for manufacturing such semiconductor devices.

[0004] Silicon carbide (that will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon (that will be referred to as Si) by one order of magnitude. Thus, SiC has been considered as a material advantageously used for power semiconductor devices in the next generation. Such devices as Shottky diodes, vertical MOSFETS, and thyristors, using SiC as a semiconductor material have been proposed, and it has been confirmed that these devices exhibit far more excellent characteristics than known devices using Si. The present invention is particularly concerned with a SiC vertical MOSFET, among the above-indicated devices.

[0005] FIG. 7 is a cross sectional view of a unit cell of planar a type vertical MOSFET, which is the most prevailing type of power semiconductor device using Si. When a voltage is applied to a gate electrode layer 6 on a gate insulating film 5, a channel 10 is induced in a surface portion of a p base region 3 right under the gate electrode layer 6, and an n source region 4 and an n drift layer 2 are electrically shorted. As a result, current is allowed to flow from a drain electrode 8 formed on the rear surface of an n⁺ substrate 1 under the n drift layer 2, to a source electrode 7 formed on the surface of the n source region 4. When the voltage applied to the gate electrode layer 6 is removed, the drain electrode 8 and source electrode 7 are electrically disconnected from each other. Thus, the vertical MOSFET of FIG. 7 performs a switching function by applying and removing voltage to and from the gate electrode layer 6.

[0006] FIG. 9(a) through FIG. 9(f) are cross sectional views showing the flow of the process of fabricating the structure as described above. The process shown in these figures is only a part of the whole process of producing the semiconductor device, in particular, a process of forming junctions that relates to the present invention.

[0007] Initially, the n drift layer 2 having high resistance is epitaxially grown on the n⁺ substrate 1, and the gate insulating film 5 in the form of a silicon dioxide film (referred to as “SiO₂film”) is formed by thermal oxidation on the surface of the n drift layer 2. Then, a polycrystalline silicon layer 6ais deposited on the gate insulating film 5, as shown in FIG. 9(a). The polycrystalline silicon layer 6ais then formed in a given pattern by photolithography to provide the gate electrode layer 6, as shown in FIG. 9(b).

[0008] Subsequently, p-type impurities, such as boron ions 3a, are implanted, as shown in FIG. 9(c), and the implanted boron atoms 3bare activated and diffused by heat treatment to form the p base region 3, as shown in FIG. 9(d).

[0009] Further, n-type impurities, such as phosphorous ions 4a, are implanted, as shown in FIG. 9(e), and the implanted phosphorous atoms 4bare activated and diffused by heat treatment to form the n source region 4, as shown in FIG. 9(f).

[0010] In the following steps that are not illustrated, phosphorous glass is deposited by reduced-pressure chemical vapor deposition (CVD)) to provide an insulating film, and an opening or window is formed through the insulating film, so that the source electrode 7 is formed in contact with the n source region 4. At the same time, a gate electrode is formed in contact with the gate electrode layer 6, and a drain electrode is provided on the rear surface of the n⁺ substrate 1.

[0011] What is most important in the above-described process is as follows: in the process of implanting the p-type boron ions 3aand n-type phosphorous ions 4a, the gate electrode layer 6 formed in the previous step serves as a mask during ion implantation, and both types of ions are introduced into the n drift layer 2 using the same mask, and then thermally diffused. The thus formed structure is called double diffusion MOS (D-MOS) structure. In this manner, the length of the channel region 10 that greatly influences characteristics of the MOSFET can be controlled with considerably high accuracy, thus assuring a high yield in the manufacture of the MOSFET.

[0012] The above-described process has been most widely employed to produce MOSFETS using Si as a semiconductor material, but cannot applied as it is when producing MOSFETS using SiC. This is because SiC has poor ability to activate impurities introduced by ion implantation, and, in order to improve this ability, ion implantation at 1000° C. or higher and heat treatment for activation at 1600° C. or higher are needed. In addition, the impurities introduced by ion implantation hardly diffuses in the SiC substrate.

[0013] While SiO₂film is normally used as a gate insulating film, and polycrystalline silicon is used as a gate electrode, the SiO₂film softens at 1300° C. or higher, and polycrystalline silicon has a fusing point of 1412° C. Accordingly, heat treatment cannot be implemented at such high temperatures as indicated above after the gate insulating film 5 and gate electrode layer 6 are formed, as in the process of FIG. 9(a) through FIG. 9(f).

[0014] In view of the above problem, trench-type MOSFET have been proposed which use SiC substrates. FIG. 10 is a cross sectional view showing a unit cell of a known example of trench-type MOSFETS.

[0015] In the structure shown in FIG. 10, a p base layer 13 is formed by epitaxial growth, rather than by diffusing impurities. Alter an n source region 14 is formed by implantation of phosphorous ions, for example, a trench 19 is formed which extends from the surface of the n source region 14 down to n drift layer 12. Gate insulating film 15 is formed on the inner wall of the trench 19, and a gate electrode layer 16 is formed to fill the interior of the trench 19. The thus formed structure may be also advantageously employed as a Si device. This is because channel regions 20 are formed in the vertical direction in this structure, thus allowing cells to be closely positioned with high area efficiency, and the resulting device exhibits improved characteristics due to its geometry.

[0016] When the above structure is employed in SiC devices, however, there arises another problem as follows. The boundary condition of the electric field strength at the interface between the semiconductor and the gate insulating film upon application of voltage is represented by:

[0017] εiEi=εsEs  (1)

[0018] where εi, εs are dielectric constants of the gate insulating film and semiconductor, respectively, and Ei, Es are electric field strengths of the gate insulating film and semiconductor, respectively. Accordingly, the electric field of the gate insulating film is represented by the following equation: $\mathrm{Ei}=\frac{\epsilon s}{\epsilon i}·\mathrm{Es}$

[0019] Since εs of Si is 11.7 and εi of the SiO₂film is 3.8, an electric field that is about 3 times as much as that of Si substrate is applied to the gate insulating film even in the case where a breakdown electric field is applied to the Si substrate. This electric field is equivalent to about 30% of the breakdown electric field of the gate insulating film. On the other hand, the εs of SiC is 10.2, which is not so different from that of Si, but its breakdown electric field is larger than that of Si by about one order of magnitude, as mentioned above. In the SiC device, therefore, an electric field that is ten times as high as that in the case of the Si device is applied to the gate insulating film.

[0020] Furthermore, the trench structure as shown in FIG. 10 includes corner portions 15a. The presence of the corner portions 15aprevents the SiC device from taking advantage of its high breakdown electric field since an electric field is concentrated at this corner portion. Namely, as voltage applied to the device is increased, the gate insulating film reaches its breakdown electric field before the semiconductor reaches its breakdown electric field, thus causing the device to break down.

[0021] Recently, Shenoy, J. N. et al. has reported in 54^thDevice Research Conference, Santa Barbara (1996) on a prototype of SiC vertical MOSFET having a high withstand voltage. FIG. 11 is a cross sectional view showing a part of the SiC vertical MOSFET. The report states that this semiconductor device is produced by double ion implantation, though no description is provided on details of the manufacturing method. In FIG. 11, p base region 23 and n source region 24 are formed by applying increased acceleration voltage upon ion implantation so as to introduce respective impurities to large depth, thereby solving the problem of diffusion of impurities as mentioned above. This SiC vertical MOSFET is in the form of a planar structure, and is therefore free from the above-described problem of the withstand voltage of the oxide film in the trench structure.

[0022] The double ion implantation method as described above, however, has the following problem. Namely, ion implantation (or the degree of introduction of ions) varies to a great extent in different directions, whereas diffusion of impurities occurs substantially in the same way in all directions. If ions are implanted in a selected region of the substrate using a mask, therefore, the amount of impurities introduced sideways from the edge of the mask is reduced. Namely, in FIG. 11, the lateral dimension of the p base region 23, i.e., the length of the channel region 30, is reduced relative to the thickness of the region 23 in the depth direction. With the length of the channel region 30 thus reduced, punch-through is more likely to occur, and the withstand voltage cannot be increased.

[0023] To solve the above problems, the present invention provides a silicon carbide vertical MOSFET comprising: a first conductivity type silicon carbide substrate, a first conductivity type drift layer comprising silicon carbide, which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base region formed in a selected region of a surface layer of the first conductivity type drift layer, a first conductivity type source region formed in a selected region of the second conductivity type base region; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer, a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base region; and a drain electrode formed on a rear surface of the silicon carbide substrate; wherein ion implantation of first conductivity type impurities for forming the first conductivity type source region is conducted using a first mask, and ion implantation of second conductivity type impurities for forming the second conductivity type base region is conducted using a second mask, the first mask having a larger width than the second mask.

[0024] In the vertical MOSFET as described above, the length of the channel region and the thickness of the second conductivity type base region can be independently controlled to desired values.

[0025] In particular, the width of the exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer is preferably larger than the dimension of the second conductivity type base region as measured in a thickness direction of the first conductivity type drift layer. In this arrangement, punch-through at the channel region can be avoided, and the withstand voltage of the thus constructed MOSFET can be increased.

[0026] In one form of the vertical MOSFET of the present invention as described above, a part of at least the second conductivity type base region protrudes from a surface of the first conductivity type source region. In this arrangement, the width of the second conductivity type base region between the exposed surface portion of the first conductivity type drift layer and the first conductivity type source region can be set to a sufficiently large value.

[0027] The present invention also provides a method for manufacturing the silicon carbide vertical MOSFET as described above, wherein ions are implanted in selected regions of the first conductivity type drift layer, using different masks for forming the second conductivity type base region and first conductivity type source region, respectively, and the gate insulating film is formed after removing the masks and conducting heat treatment.

[0028] According to the above method, the gate insulating film and gate electrode layer are formed after ion implantation and activation of the implanted ions, thus making it possible to produce a planar type vertical MOSFET.

[0029] In the method of the present invention, the ion implantation of second conductivity type impurities for forming the second conductivity type base region is preferably conducted a plurality of times while varying an acceleration voltage. In this case, the thickness of the second conductivity type base region may be increased as desired.

[0030] In the above-described method, the first mask used during ion implantation of first conductivity type impurities for forming the first conductivity type source region may consist of the second mask used during ion implantation of second conductivity type impurities for forming the second conductivity type base region, and a spacer formed on side faces of the first mask. In this case, the length of the channel region can be controlled to a desired value by suitably determining the width of the spacer, and therefore the device can be easily designed with increased freedom.

[0031] The present invention also provides another method for forming a silicon carbide vertical MOSFET, which includes the steps of forming a first conductivity type drift layer comprising silicon carbide on a first conductivity type silicon carbide substrate; covering a part of the first conductivity type drift layer with a mask, and etching the first conductivity type drift layer to a given depth to form a protruding portion; implanting ions for forming a second conductivity type base region in a selected region of the first conductivity type drift layer; forming a spacer on side faces of the protruding portion formed as a result of etching of the first conductivity type drift layer; implanting ions for forming a first conductivity type source region in a selected region of the second conductivity type base region; and reducing a height of the protruding portion of the first conductivity type drift layer so as to provide a flat surface.

[0032] According to the above-described method, the protruding portion of the first conductivity type drift layer serves as a mask, and thus eliminates a need to form a thick mask made of another material that is selected to permit ion implantation of impurities at high acceleration voltage.

[0033] The present invention further provides a silicon carbide vertical MOSFET comprising: a first conductivity type silicon carbide substrate, a first conductivity type drift layer comprising silicon carbide, which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base layer formed on the first conductivity type drift layer; a first conductivity type source region formed in a selected region of a surface layer of the second conductivity type base layer; a first conductivity type well region formed through the second conductivity type base layer to extend from a surface of the base layer to the first conductivity type drift layer; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base layer interposed between the first conductivity type source region and the first conductivity type well region; a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base layer; and a drain electrode formed on a rear surface of the silicon carbide substrate. In this arrangement, ions of second conductivity type impurities need not be implanted to form the second conductivity type base layer, and therefore the MOSFET can be more easily manufactured.

[0034] In the vertical MOSFET as described above, the first conductivity type may be n type, and the second conductivity type may be p type. In this case, the vertical MOSFET can be easily manufactured since the second conductivity type base layer is formed by epitaxial growth, without requiring ion implantation of p type impurities that are difficult to be activated.

[0035] The present invention provides a method for manufacturing the silicon carbide vertical MOSFET as described just above, which includes the steps of: forming a first conductivity type drift layer comprising silicon carbide and a second conductivity type base layer on a first conductivity type silicon carbide substrate by epitaxial growth, to provide a substrate; forming a first mask on a surface of the second conductivity type base layer, forming a second mask on the surface of the base layer such that the second mask overlaps the first mask; implanting ions for forming a first conductivity type source region in a selected region of a surface layer of the second conductivity type base layer, using the first mask and the second mask; forming a third mask on the surface of the second conductivity type base layer such that the third mask and overlaps the first mask; implanting ions for forming a first conductivity type well region in a selected region of the surface layer of the second conductivity type base layer, using the first mask and the third mask, so that the well region extends from the surface of the second conductivity type base layer to the first conductivity type drift layer through the base layer.

[0036] The invention will be described in greater detail with reference to preferred embodiments thereof and the accompanying drawings, wherein:

[0037] FIG. 1 is a cross sectional view of a silicon carbide vertical MOSFET according to the first embodiment of the present invention;

[0038] FIG. 2(a) through FIG. 2(f) are cross sectional views showing process steps in a method for manufacturing the silicon carbide vertical MOSFET of the first embodiment of the present invention;

[0039] FIG. 3(a) through FIG. 3(g) are cross sectional views showing process steps in a method for manufacturing a silicon carbide vertical MOSFET according to the second embodiment of the present invention,

[0040] FIG. 4(a) through FIG. 4(f) are cross sectional views showing process steps in a method for manufacturing a silicon carbide vertical MOSFET according to the third embodiment of the present invention,

[0041] FIG. 5(a) through FIG. 5(d) are cross sectional views showing process steps following the step of FIG. 4(f),

[0042] FIG. 6 is a cross sectional view of a silicon carbide vertical MOSFET according to the fourth embodiment of the present invention;

[0043] FIG. 7 is a cross sectional view showing a known vertical MOSFET having a silicon substrate;

[0044] FIG. 8(a) through FIG. 8(g) are cross sectional views showing process steps in a method for manufacturing the silicon carbide vertical MOSFET of the fourth embodiment of the present invention;

[0045] FIG. 9(a) through FIG. 9(f) are cross sectional views showing process steps for producing the silicon vertical MOSFET of FIG. 7;

[0046] FIG. 10 is a cross sectional view of a trench type silicon carbide MOSFET; and

[0047] FIG. 11 is a cross sectional view of a known planer type silicon carbide MOSFET.

[0048] Some embodiments of the present invention will be described in detail. It is, however, to be noted that no description will be provided on process steps that are similar to those of the known method of FIG. 9 and process steps that have no relation with the present invention.

[0049] First Embodiment

[0050] FIG. 1 is a cross sectional view showing a silicon carbide MOSFET constructed according to the first embodiment of the present invention.

[0051] The basic structure of this embodiment is substantially identical with that of the planar type MOSFET of FIG. 11. More specifically, an n drift layer 32 is deposited by epitaxial growth on an n⁺ silicon carbide substrate 31, and a p base region 33 is formed in a surface layer of the n drift layer 32 by implantation of boron ions while an n source region 34 is formed inside the p base region 33 by implantation of phosphorous ions. A gate electrode layer 36 made of polycrystalline silicon is formed on a gate insulating film 35 over exposed surface portions of p base regions 33 and n drift layer 32 interposed between two n source regions 34. A source electrode 37 is formed in contact with both of the n source region 34 and p base region 33, and a drain electrode 38 is formed in contact with the rear surface of the n⁺ silicon substrate.

[0052] The silicon carbide MOSFET of FIG. 1 is different from the planar type MOSFET of FIG. 11 in that the n source region 34 and p base region 33 are not formed in respectively selected regions using the same mask. In particular, a pattern of a mask used for forming the p base region 33 has a smaller width than that of a mask used for forming the n source region 34. As a result, the length of a channel region 40 that is an exposed surface portion of the p base region 33 interposed between the n source region 34 and n drift layer 32 becomes greater than that of the MOSFET in which the regions 33, 34 are formed by ion implantation using the same mask.

[0053] FIG. 2(a) through FIG. 2(f) are cross sectional views showing the process of manufacturing the silicon carbide MOSFET of the first embodiment shown in FIG. 1, more particularly, the process of forming the junction structure as in FIGS. 9(a)-9(f).

[0054] Initially, the n drift layer 32 is laminated on the n⁺ silicon carbide substrate 31 by epitaxial growth, and a polycrystalline silicon layer 36ais deposited by reduced-pressure CVD on the surface of the n drift layer 32, and formed in a given pattern by photolithography to provide a mask for ion implantation, as shown in FIG. 2(a). The thickness of the polycrystalline silicon layer 36ais 5 μm. The mask needs to be formed of a material, such as polycrystalline silicon, that can withstand high temperature during ion implantation.

[0055] Using the mask as described above, phosphorous ions are implanted so as to form the n source region. The implantation conditions are as follows: the acceleration voltages are 20 keV and 140 keV, the dose amount is 3×10¹⁵cm⁻², and the implantation temperature is 1000° C.

[0056] Then, a polycrystalline silicon layer 36bis formed again in another pattern by photolithography, and boron ions 33aare implanted so as to form the p base region, as shown in FIG. 2(c). The implantation conditions are as follows: the acceleration voltages are 40 keV, 120 keV, 400 keV and 1 MeV, the dose amount is 3×10¹³cm⁻², and the implantation temperature is 1000° C.

[0057] After removing the polycrystalline silicon layer 36bas a mask material by dry etching using a nixed gas of carbon tetrafluoride (CF₄) and oxygen (O₂), heat treatment is conducted for two hours at 1600° C., to activate the impurities thus implanted, thereby to form the p base region 33 and n source region 34, as shown in FIG. 2(d). Although diffusion of the impurities hardly occurs in the SiC substrate in normal conditions, the impurities are activated and diffused in this case due to the high acceleration voltages, so that the junction depth of the p base region 33 is about 2 μm, and the junction depth of the n source region 34 is about 0.2 μm.

[0058] Subsequently, the gate insulating film 35ahaving a thickness of 50 nm is formed by conducting thermal oxidation for two hours at 1200° C., and an about 1 μm-thickness polycrystalline silicon layer 36cthat provides the gate electrode layer is deposited on the gate insulating film 35 by reduced-pressure CVD, as shown in FIG. 2(e). The polycrystalline silicon layer 36cis then formed in a given pattern by photolithography, to thus provide the gate electrode layer 36, as shown in FIG. 2(f).

[0059] After covering the gate electrode layer 36 with an insulating protective film, such as phosphorous glass, an opening is formed through the insulating protective film, and aluminum alloy is vapor-deposited and patterned to form the source electrode and gate electrode (not illustrated). In the meantime, the drain electrode is formed on the rear surface of the n⁺ silicon substrate. Thus, the process for fabricating the vertical MOSFET is finished.

[0060] Referring back to FIG. 1 showing the silicon carbide MOSFET, a voltage is applied to the gate electrode layer 36 on the gate insulating layer 35, so that a channel 40 is induced in a surface portion of the p base region 33, and the n source region 34 and n drift layer 32 are electrically shorted. As a result, current flows from the drain electrode 38 to the source electrode 37 in a manner similar to the operation of the known MOSFET of FIG. 11.

[0061] The silicon carbide vertical MOSFET of the first embodiment is characterized in that the depth of the p base region 33 may be set as desired to either a large value or small value, and thus the junction structure may be designed with increased freedom. For example, the length of the channel region becomes 0.3 μm when the p base region and n source region are formed by ion implantation using the same mask in the known method. In the present embodiment, on the other hand, different masks are used for forming these regions, so that the channel length becomes equal to about 1. 0 μm. The resulting semiconductor device has a high withstand voltage of about 1000 V, and punch-through at the channel region of this device can be advantageously avoided.

[0062] Also, the silicon carbide MOSFET formed by the above-described method is of a planar type, and is therefore free from the above-described problem encountered in the known trench type silicon carbide MOSFET, namely, the problem of excessive electric field applied to the gate insulating film. Thus, the device produced by the method of the present embodiment is less likely to break down.

[0063] The method for manufacturing the silicon MOSFET as shown in FIG. 2(a) through FIG. 2(f) is different from that as shown in FIG. 9(a) through FIG. 9(f) in that the gate electrode layer is not formed in self alignment with the n source layer or p base region. This does not cause any problem in the manufacture of high-voltage devices that do not require high-frequency operations. The method of the present embodiment is advantageous in that the n source region and p base region can be designed with increased freedom, and the length of the channel region is controlled with high accuracy, assuring stable characteristics and a high yield.

[0064] Since the mask used upon implantation of boron ions is smaller than the mask used upon implantation of phosphorous ions, only one formation of the mask material is required if phosphorous ions are implanted earlier than boron ions as in the present embodiment. If the mask material is formed twice, the boron ions for forming the p base region may be implanted first, followed by ion implantation for forming the n source region.

[0065] Second Embodiment

[0066] FIG. 3(a) through FIG. 3(g) are cross sectional views showing process steps in another method of manufacturing a silicon carbide vertical MOSFET according to the present invention. The process will be described below step by step.

[0067] Initially, an n drift layer 41 is laminated on an n⁺ silicon carbide substrate 42 by epitaxial growth, and a polycrystalline silicon layer 46ais deposited on the surface of the n drift layer 42 by reduced-pressure CVD, and patterned by photolithography to form a mask for ion implantation, as shown in FIG. 3(a). The thickness of the polycrystalline silicon layer 46ais 5 μm.

[0068] Subsequently, boron ions 43aare implanted, as shown in FIG. 3(b). The implantation conditions are as follows: the acceleration voltages are 40 keV, 120 keV, 400 keV and 1 MeV, the total dose amount is 3×10¹³cm⁻², and the implantation temperature is 1000° C. In FIG. 3(b), reference numeral 43bdenotes boron atoms thus implanted.

[0069] Subsequently, a silicon dioxide film 45ais deposited by normal-pressure CVD, as shown in FIG. 3(c), and this film 45ais then subjected to reactive ion etching, using a mixed gas of carbon tetrafluoride and hydrogen. As a result of the reactive ion etching which is a type of an isotropic ion etching, a spacer 45bhaving a thickness of about 0.5 μm is formed on side faces of the mask formed by the polycrystalline silicon layer 46a. Then, phosphorous ions 44aare implanted, using these spacer 45band polycrystalline silicon layer 46aas a mask. The acceleration voltages are 20 keV and 140 keV, and the total dose amount is 3×10¹⁵cm⁻². In FIG. 3(d), reference numeral 44bdenotes phosphorous atoms thus implanted.

[0070] After removing the polycrystalline silicon layer 46aand spacer 45bas a mask material by dry etching using a mixed gas of carbon tetrafluoride and hydrogen, heat treatment is conducted for two hours at 1600° C., to activate the impurities and form the p base region 43 and n source region 44, as shown in FIG. 3(e). The depth of the junction between the p base region 43 and n drift layer 42 is about 2 μm, and the depth of the junction between the n source region 44 and the p base region 43 is about 0.2 μm. Since the spacer 45bformed on the side faces of the polycrystalline silicon layer 46adetermines differences in the dimensions between the p base region 43 and n source region 44, the length of channel region 40 can be uniformly controlled with high accuracy, assuring stable characteristics of the resulting device and a higher yield in the manufacture thereof The process following the above steps is similar to that of the first embodiment of FIG. 2. Namely, a gate oxide film 45cis formed by thermal oxidation, and a polycrystalline silicon layer 46bhaving a thickness of about 1 μm is deposited on the gate oxide film 45cby reduced-pressure CVD, as shown in FIG. 3(f). The polycrystalline silicon layer 46bis then patterned by photolithography, to form a gate electrode layer 46, as shown in FIG. 3(g).

[0071] While the method of manufacturing the silicon carbide vertical MOSFET according to the second embodiment is somewhat different from that of the first embodiment, the resulting structure and its operation of this embodiment are almost the same as those of the first embodiment.

[0072] Similar to the first embodiment, the silicon carbide vertical MOSFET produced according to the method of the second embodiment is characterized in that the depths of the p base region 43 and n source region 44 and the length of the channel region may be controlled to desired values, and the junction structure may be designed with increased freedom. For example, the length of the channel region is equal to about 0.3 μm when the ions are implanted using the same mask to form the p base region and n source region, whereas the length of the channel region 40 is equal to about 1.0 μm in the present embodiment in which the spacer 45bis used to define a difference in the depth between the p base region 43 and the n source region 44. With the length of the channel region thus increased, the resulting device is given a withstand voltage as high as about 1000V, and punch-through can be avoided at the channel region of the device.

[0073] As an alternative method, phosphorous ions may be implanted first to form the n source region 44, using the polycrystalline silicon layer 46aand the spacer 45bas a mask, and, after removing the spacer 45b, boron ions may be implanted to form the p base region 43 using only the polycrystalline silicon layer 46aas a mask.

[0074] Third Embodiment

[0075] FIG. 4(a) through FIG. 4(f) and FIG. 5(a) through FIG. 5(d) are cross sectional views showing the process of manufacturing a silicon carbide MOSFET according to the third embodiment of the present invention.

[0076] Initially, an n drift layer 52 is laminated on an n⁺ silicon carbide substrate 51 by epitaxial growth, and a silicon nitride film 56ais deposited on the surface of the n drift layer 52 by plasma CVD, and patterned by photolithography to form a mask for etching, as shown in FIG. 4(a).

[0077] Using the silicon nitride film 56aas a mask, the surface layer of the SiC substrate is etched to a depth of about 5 μm, by reactive ion etching using a mixed gas of carbon tetrafluoride and oxygen, so as to form a protruding portion 52a.

[0078] In the next step shown in FIG. 4(c), boron ions 53aare implanted with the patterned silicon nitride film 56aleft on the protruding portion 52a. The acceleration voltages and dose amount may be controlled to be at substantially the same level as those of the first embodiment. In FIG. 4(c), reference numeral 53bare boron atoms thus implanted. Some boron ions 53amay be introduced into the protruding portion 52a. Then, after removing the silicon nitride film 56a, a silicon dioxide film 55ais deposited by normal-pressure CVD, as shown in FIG. 4(d).

[0079] Subsequently, the entire surface of the silicon dioxide film 55athus deposited is subjected to reactive ion etching using a mixed gas of carbon tetrafluoride and hydrogen, to form a 0.5 μm-thickness spacer 55bon side faces of the protruding portion 52a. Then, phosphorous ions 54aare implanted, using the spacer 55band the protruding portion 52aas a mask, as shown in FIG. 4(e). The acceleration voltage and dose amount may be controlled to be substantially at the same level as those of the first embodiment. In FIG. 4(e), reference numeral 54bdenotes phosphorous atoms thus implanted. Some phosphorous ions may be introduced into the surface layer of the protruding portion 52a.

[0080] Thereafter, the spacer 55bis removed, and the surface is coated with a photoresist 55c, as shown in FIG. 4(f), such that a portion of the photoresist 55con the protruding portion 52ahas a relatively small thickness and the other portion has a relatively large thickness.

[0081] In the next step, reactive ion etching is conducted using a mixed gas of carbon tetrafluoride and oxygen, under such etching conditions that the photoresist 55cand the protruding portion 52aare etched at almost the same rate, to thus provide a substantially flat surface, as shown in FIG. 5(a). Protrusions and recesses on this surface are made as small as possible, for example, controlled to be in a range of 0.1 to 0.2 μm. Instead of etching, this flat surface may be formed by mechanical grinding.

[0082] In the next step shown in FIG. 5(b), the photoresist 55cremaining on the surface is removed, and heat treatment is conducted for two hours at 1600° C. The process following this step is similar to that of the first embodiment. Namely, a gate oxide film 55dis formed by thermal oxidation, and a polycrystalline silicon layer 56bthat provides a gate electrode layer 56 is deposited on the gate oxide film 55dby reduced-pressure CVD, as shown in FIG. 5(c). The gate electrode layer 56 is then formed in a given pattern, as shown in FIG. 5(d).

[0083] Similarly to the first and second embodiments, the third embodiment is characterized in that the depths and other dimensions of the p base region 53 and n source region 54 may be freely controlled to desired values, thus allowing the junction structure to be designed with increased freedom.

[0084] Furthermore, the third embodiment is characterized in the use of the n drift layer 52 itself as a mask for forming the p base region in a selected region of the substrate. In the first and second embodiments, it is difficult to find an appropriate material to be used as a mask material, and ions cannot be introduced so deeply that they penetrate through the mask material. If the n drift layer 52 itself is used as the mask material as in the present embodiment, no problem arises in terms of the stability and limit to the thickness.

[0085] Fourth Embodiment

[0086] FIG. 6 is a cross sectional view showing a silicon carbide MOSFET according to the fourth embodiment of the present invention.

[0087] In this silicon carbide MOSFET, an n drift layer 62 and a p base layer 63 are laminated on an n⁺ substrate 61 by epitaxial growth, and an n source region 64 is formed in a surface layer of the silicon carbide substrate by implantation of phosphorous ions. In a portion of the surface layer of the substrate in which the n source region 64 is not formed, an n well region 71 is formed through the p base layer 63 to reach the n drift layer 62. A gate electrode layer 66 made of polycrystalline silicon is formed on a gate insulating film 65 over a surface of the p base layer 63 that is interposed between the n well region 71 and n source region 64. Further, a source electrode 67 is formed in contact with surfaces of both of the n source region 64 and p base layer 63, and a drain electrode 68 is formed in contact with the rear surface of the n+substrate 61.

[0088] FIG. 8(a) through FIG. 8(g) are cross sectional views showing the process of manufacturing the silicon carbide MOSFET of the fourth embodiment.

[0089] Initially, the n drift layer 62 having a thickness of 10 μm is laminated on the n⁺ silicon carbide substrate 61 by epitaxial growth, and then the p base layer 63 having a thickness of 2 μm is epitaxially grown on the n drift layer 62, as shown in FIG. 8(a). In the next step shown in FIG. 8(b), a polycrystalline silicon layer having a thickness of 4 μm is deposited on the surface of the p base layer 63 by reduced-pressure CVD, and then patterned to form a first mask 66a. This mask is used during ion implantation for forming both the n source region 64 and n well region 71 as described below.

[0090] With the mask 66aleft on the p base layer 63, an oxide film is deposited on the substrate by a CVD method, and patterned by photolithography to form a second mask 65a, and phosphorous ions 64aare implanted in the p base layer 63 so as to form the n source region 64, as shown in FIG. 8(c). Since the edge of the mask is defined by that of the first mask 66a, the second mask 65amay be patterned with reduced accuracy. The conditions of ion implantation may be similar to those under which the n source region of the first embodiment is formed. In FIG. 8(c), reference numeral 64bdenotes phosphorous atoms thus implanted.

[0091] After implantation of phosphorous ions, the second mask 65ais removed, and polycrystalline silicon is deposited again by reduced-pressure CVD, and patterned by photolithography to form a third mask 66b. Using the first mask 66aand third mask 66bthus formed, phosphorous ions 71aare implanted into the p base layer 63 as shown in FIG. 8(d) so as to form the n well region 71 that extends through the p base layer 63. Since the edge of the resulting mask is defined by that of the first mask 66a, the third mask 66bmay be formed with reduced accuracy. The conditions of ion implantation are as follows: the acceleration voltages are 40 keV, 120 keV, 400 keV and 1 MeV, the total dose amount is 3×10¹³cm⁻², and the implantation temperature is 1000° C. In FIG. 8(d), reference numeral 71bdenotes phosphorous atoms thus implanted.

[0092] After removing the first and third masks 66a, 66bby dry etching using a mixed gas of carbon tetrafluoride (CF₄) and oxygen (O²), heat treatment is conducted for two hours at 1600° C., to activate the impurities so as to form the n source region 64 and n well region 71, as shown in FIG. 8(e). The depth of the junction between the p base layer 63 and the n source region 64 is about 0.2 μm.

[0093] Thereafter, the gate insulating film 65 having a thickness of 60 nm is formed by thermal oxidation, and polycrystalline silicon layer 66cis deposited on the gate insulating film 65 by reduced-pressure CVD, and is patterned by photolithography to form the gate electrode layer 66, as shown in FIG. 8(f) and FIG. 8(g).

[0094] In the next step that is not illustrated, phosphorous glass is deposited by reduced-pressure CVD to form an insulating film, and an opening is formed through the insulating film, so that the source electrode is formed in contact with the n source region 64. At the same time, a gate electrode is formed in contact with the gate electrode layer 66, and the drain electrode 68 is formed on the rear surface of the n⁺silicon carbide substrate 61.

[0095] In the silicon carbide MOSFET of the fourth embodiment, the width of the p base layer interposed between the n source region 64 and n well region 71, namely, the length of the channel region 70, can be uniformly set to a desired value with high accuracy by suitably controlling the width of the first mask 66a. Thus, the above-described process is advantageously employed to form a high voltage silicon carbide MOSFET in which impurities are less likely to be diffused, as compared with the known process in which the n source region and p base region are formed by self alignment using the edge of the same mask.

[0096] The silicon carbide MOSFET of the fourth embodiment shown in FIG. 6 is different from that of the first embodiment shown in FIG. 1 in that the p base layer 63 is formed by epitaxial growth, and then well region 71 that extends through the p base layer 63 is formed by ion implantation. This method does not require implantation of ions as p-type impurities that are normally difficult to be implanted and activated in the SiC substrate, and therefore the silicon carbide MOSFET can be manufactured by this method with a considerably improved efficiency.

[0097] While the silicon carbide MOSFET of the illustrated embodiments are of n-channel type, the present invention may be equally applied to a MOSFET in which the conductivity types are reversed with respect to those of the illustrated embodiments.

[0098] While phosphorous and boron are used as n-type and p-type impurities, respectively, in the illustrated embodiments, nitrogen or arsenic may be used as n-type impurities, and aluminum may be used as p-type impurities.

[0099] According to the present invention as explained above, the first conductivity type source region of the silicon carbide vertical MOSFET is formed by ion implantation of first conductivity type impurities in a selected region of the first conductivity type drift layer, using a mask that has a larger width than a mask used during ion implantation of second conductivity type impurities in a selected region of the drift layer. Thus, the length of the channel and the thickness of the second conductivity type base region can be independently controlled to desired values, to thus provide a structure that has a high withstand voltage and is free from punch through at the channel region.

[0100] The above vertical MOSFET is manufactured by implanting ions in selected regions of the first conductivity type drift layer, using different masks for forming the second conductivity type base region and first conductivity type source region, respectively, and forming a gate insulating film after removing the masks and conducting heat treatment. The silicon carbide vertical MOSFET produced according to this method has reduced stresses due to an electric field applied to the gate insulating film, and is thus able to withstand a sufficiently high voltage.

[0101] If a spacer is used to form one of the above masks, the length of the channel region can be controlled with high accuracy, assuring stable characteristics of the MOSFET and an increased yield in the manufacture thereof

[0102] In another manufacturing method, the first conductivity type well region is formed by ion implantation such that this well region extends from the surface of the second conductivity type base region to the first conductivity type drift layer, and the first conductivity type source region is formed by ion implantation in a selected region of the surface layer of the second conductivity type base layer. Since this method does not require ion implantation of second conductivity impurities for forming the second conductivity type base layer, the silicon carbide vertical MOSFET may be manufactured with improved efficiency.