Duty cycle integrator with tracking common mode feedback control

[0002] This invention relates to differential amplifiers and to clock duty cycle integrators.

[0003] Differential amplifiers are used for a variety of purposes. One use of a differential amplifier is in a circuit that measures and corrects for duty cycle error in a clock signal.

[0004] A clock is typically desired to have a 50% duty cycle. A duty cycle integrator is used to produce a differential output voltage that represents the integral of the duty cycle error on a clock signal over time. That voltage is then used to correct the duty cycle of the signal back to 50%.

[0005] FIG. 1 shows a simplified prior art duty cycle integrator 10. As input, the duty cycle integrator accepts complementary clock inputs CLK+ and CLK−, and produces a differential output voltage on nodes OUT+ and OUT−.

[0006] Duty cycle integrator 10 comprises a differential pair of transistors M₁and M₂. The transistors in this example are n-channel MOSFETs whose sources are connected in common to a lower supply voltage V_ss. The drain of each transistor is connected to an upper supply voltage V_ddthrough a load circuit 12. The load circuit typically provides a bias and preferably exhibits high differential mode impedance to facilitate integration of the duty cycle error.

[0007] A capacitance C is connected to integrate the output current and generate voltages OUT+ and OUT−.

[0008] The gates of transistor M₁and M₂receive the complementary clock inputs CLK+ and CLK−, and the transistors switch on and off in response. Because of the complementary nature of the clock inputs, one transistor is on while the other is off. If there is a 50% duty cycle, each transistor is on for same duration, and the integrated outputs equal each other. If there is other than a 50% duty cycle, however, one of the transistors is on for longer durations than the other transistor. Over time, this causes the integrated outputs OUT+ and OUT− to become unequal, producing a differential signal. The rate of change of that differential signal is indicative of the duty cycle error on the clock inputs.

[0009] FIG. 2 shows a prior art duty cycle integrator 20 having an active load. Transistors M₁and M₂are connected as in FIG. 1, except that a current source I is connected between V_ssand the common sources of the transistors. The load comprises two pairs 21 and 22 of p-channel MOSFETs. Each pair has its drains connected in common to the drain of a corresponding one of transistors M₁and M₂, and its sources connected in common to V_dd. Within each pair, the gate of one transistor is tied to the drain of the corresponding one of differential transistors M₁and M₂, while the gate of the other transistor is tied to the drain of the other, opposing one of differential transistors M₁and M₂. For example, of the pair 21, one transistor has its gate tied to the drain of differential transistor M₁, while the other transistor has its gate tied to the drain of differential transistor M₂.

[0010] This load is advantageous in certain situations because it exhibits a very low common mode impedance and a very high differential impedance.

[0011] A load such as this is described in U.S. Pat. No. 5,422,529, entitled “Differential Charge Pump Circuit With High Differential and Low Common Mode Impedance,” which states that the described load eliminates the need for common mode feedback.

[0012] FIGS. 1 and 2 are schematic diagrams of prior art clock duty cycle integrators.

[0013] FIG. 3 is a schematic diagram of a duty cycle integrator.

[0014] FIG. 4 is a schematic diagram of an integrator circuit.

[0015] FIG. 5 is a block diagram of a reference generator circuit.

[0016] FIG. 6 is a block diagram of a buffer circuit.

[0017] The following description sets forth a specific embodiment that incorporates elements recited in the appended claims. The embodiment is described with specificity in order to meet statutory requirements. However, the description itself is not intended to limit the scope of this patent. Rather, the inventors have contemplated that the claimed invention might also be embodied in other ways, to include different elements or combinations of elements similar to the ones described in this document, in conjunction with other present or future technologies.

[0018] FIG. 3 shows a clock duty cycle integration circuit 30, also referred to herein as a duty cycle detection circuit. The circuit receives a clock input CLK and produces a differential output signal OUT that comprises a pair of differential voltages OUT+ and OUT−.

[0019] Detection circuit 30 has inverters and/or buffers 32 that receive the CLK signal and in response produce complementary, full-swing clock inputs CLK+ and CLK−. Inverters and/or buffers 32 are configured to maintain an accurate phase relationship between CLK+ and CLK− so that CLK+ is on when CLK− is off and vise versa.

[0020] Detection circuit 30 also has reference generation circuit 37. Reference generation circuit 37 produces biasing voltages V_cm1and V_cm2that control the common mode voltages of the differential input signal IN and of the differential output signal OUT, respectively.

[0021] Detection circuit 30 also has reference generation circuit 40. Reference generation circuit 40 produces biasing voltages V_cm1and V_cm2that control the common mode voltages of the differential input signal IN and of the differential output signal OUT, respectively.

[0022] FIG. 4 shows an implementation of integrator circuit 36, which is fabricated in this example using CMOS technology. The circuit comprises a differential pair 40 formed by n-channel MOSFET transistors M_n1and M_n2. The gates of these transistors are connected to receive the input voltages IN+ and IN−, respectively, of the differential input signal produced by buffer 35. The drains of M_n1and M_n2are connected to a load 41 and to capacitances C+ and C− respectively. The capacitances integrate the output current of differential pair 40, to produce differential output signal OUT.

[0023] The load 41 associated with differential transistors M_n1and M_n2comprises a pair of matching current source transistors M_p1and M_p2. These are p-channel MOSFETs connected in series with the respective differential transistors M_n1and M_n2. Specifically, each of transistors M_p1and M_p2has its source connected to upper supply voltage V_ddand its drain connected to the drain of one of differential transistors M_n1and M_n2.

[0024] Load transistors M_p1and M_p2are configured to mirror a reference current that is established by a biasing circuit 42. Biasing circuit 42 includes a current source I_biasand transistors M_bs1, M_bs2, M_bs3, M_bs4, and M_bs5. M_bs1, M_bs2, M_bs3, and M_bs4are n-channel MOSFETs, while M_bs5is a p-channel MOSFET.

[0025] Transistor M_bs5is configured as a current mirror transistor with load transistors M_p1and M_p2: the gates of all three transistors are connected in common to the drain of transistor M_bs5while the sources of all three transistors are connected to V_dd. Each one of transistors M_p1and M_p2is half the width of transistor M_bs5. Thus, load transistors M_p1and M_p2mirror half of the reference current I_Rthat flows through transistor M_bs5.

[0026] Reference current I_Ris established through transistor M_bs5as follows. Current source I_bias, transistor M_bs2and transistor M_bs1are connected in series: I_biasflows between V_ddand the drain of M_bs2; the source of M_bs2is connected to the drain of M_bs1, and the source of M_bs1is connected to V_ss. Thus, the current through M_bs1and M_bs2is equal to I_bias.

[0027] Transistor M_bs4is configured to act as a current source in series with transistor M_bs5, to establish a reference current I_Rthrough M_bs5. Specifically, the drain of transistor M_bs4is connected to the drain of transistor M_bs5; the source of transistor Mbs4 is connected to the drain of transistor M_bs3, and the source of transistor M_bs3is connected to V_ss. The gate of transistor M_bs4is connected to both the drain and the gate of transistor M_bs2. Accordingly, transistor M_bs4mirrors transistor M_bs2, and establishes a current I_R=I_biasthrough transistor M_bs5.

[0028] Transistors M_bs1and M_bs3are controlled by a reference voltage V_cm1connected to their gates, and function as references to common mode feedback circuitry described below. V_cm1is supplied from reference generator 37 (FIG. 3). Transistors M_bs1and M_bs3are configured to operate in their linear region.

[0029] Load transistors M_p1and M_p2are mirrors of transistor M_bs5, and therefore source a total current I_biasto output nodes OUT+ and OUT−. In addition, an n-channel transistor M_csis connected in series with the common sources of differential transistors M_n1and M_n2. Transistor M_csis connected to mirror whatever current flows through transistor Mbs4, and therefore establishes a current I_R=Ibias that is allowed to flow differentially through transistors M_n1and M_n2.

[0030] Integrator circuit 36 further comprises common mode feedback circuitry 44 that controls the common mode output voltage of integrator circuit 36. Common mode feedback circuitry 44 is responsive to reference voltage V_cm1and to the common mode voltage of differential output signal OUT to minimize the difference between the common mode voltage and the reference voltage. The common mode output voltage is defined as the average voltage of OUT+ and OUT−.

[0031] Common mode feedback circuitry 44 includes a pair of n-channel MOSFET transistors M_f1and M_f2connected in parallel with each other and in series with differential pair 40. Transistors M_f1and M_f2are controlled by the differential output signal of differential pair 40 to establish a desired common mode output voltage. These transistors, like reference transistors M_bs1and M_bs3, are configured to operate in their linear region.

[0032] More specifically, the drains of transistors M_f1and M_f2are connected in common to the sources of differential transistors M_n1and M_n2through the source-drain channel of the current-source transistor M_cs. The sources of transistors M_f1and M_f2are connected in common to V_ss. The gate of transistor M_f1is connected to the differential output voltage OUT+ and the gate of transistor M_f2is connected to the differential output voltage OUT−.

[0033] In conjunction with the differential pair 40 and load elements M_p1and M_p2, feedback transistors M_f1and M_f2function similarly to transistors M_bs1and M_bs3in biasing circuit 42. The gates of M_bs1and M_bs3are connected to reference voltage V_cm1. The remaining voltages of biasing circuit 42 assume whatever values are necessary to maintain I_Requal to I_bias. Specifically, the voltage at the gate of transistor M_bs5will be such that M_bs5will pass currents equal to I_Ror I_bias.

[0034] For the circuit to maintain equilibrium, feedback transistors M_f1and M_f2should also pass a total current equal to I_Ror I_bias, Since M_f1and M_f2are in positions similar to that of transistors M_bs1and M_bs3, M_f1and M_f2need gate voltages equal to V_cm1to pass I_Ror I_bias. Accordingly, and since the gates of these transistors are connected to the differential outputs OUT+ and OUT−, a common mode output voltage that is higher than V_cm1will cause feedback transistors M_f1and M_f2to conduct a current greater than I_R, which will over time lower the common mode output voltage. A common mode output voltage that is lower than V_cm1will cause feedback transistors M_f1and M_f2to conduct a current less than I_R, which will over time increase the common mode output voltage. This feedback mechanism, therefore, keeps the common mode voltage equal to V_cm1.

[0035] It is desirable to provide for as much voltage swing as possible in the differential output signal OUT. Thus, V_cm1, which corresponds to the common mode output voltage, is set at a value approximately midway between the possible voltage extremes of OUT+ and OUT−.

[0036] In the circuit of FIG. 4, the upper value of the OUT+ and OUT− signals is desirably limited to the highest voltage at which load transistors M_p1and M_p2remain in their saturation regions and therefore behave as approximately ideal current sources. This highest voltage is equal to V_dd−V_SAT, where the saturation voltage V_SATis the lowest drain to source voltage at which a transistor remains in its saturation region. V_SATis typically defined as V_GS−V_T, where V_GSis the gate to source voltage of the transistor and V_Tis the voltage threshold of the transistor. In this case, V_GScan be made quite low—e.g. 100 mV above V_T. As a result, the circuit of FIG. 4 permits a relatively high upper limit on the differential output voltages OUT+ and OUT−. This is a highly desirable characteristic in modern integrated circuits where supply voltages are decreased as much as possible to accommodate fine transistor geometry.

[0037] To further exploit the relatively high upper voltage limit of the differential output voltages, it is desirable to generate V_cm1in a way such that it varies with the supply voltage V_ddand saturation voltage V_SAT. In the described embodiment, this is accomplished by varying V_cm1as a function of V_ddand V_TP, where V_TPis the voltage threshold of p-channel MOSFETs used in the circuit. Specifically, V_cm1is generated such that it varies directly with V_ddand in proportion to V_TP.

[0038] FIG. 5 shows an exemplary implementation of a reference generator 37 that generates reference voltage V_cm1and that varies V_cm1as a function of a p-channel voltage threshold. The circuit includes a p-channel load transistor M₉and a series of transistors M₁₀, M₁₁, M₁₂, M₁₃and M₁₄that are connected to establish a voltage at node A that is equal to V_dd−V_TP, where V_TPis the characteristic voltage threshold of p-channel transistors used in the implementation of the duty cycle integrator.

[0039] Transistors M₁₀, M₁₁and M₁₂are n-channel MOSFETs whose sources and drains are connected in series from V_ssto the drain of transistor M13. Transistor M₁₃is a p-channel MOSFET whose source is connected to V_dd. The gates of transistors M₁₀, M₁₁, M₁₂and M₁₃are connected together and to node A. The source of load transistor M₉is connected to V_ddand its drain is connected to node A. The gate of load transistor M₉is connected to V_ss.

[0040] Transistor M₁₄is a p-channel MOSFET whose gate is connected to the drain of transistor M₁₃. The source of transistor M₁₄is connected to node A. The drain of transistor M₁₄is connected through the drain and source of an n-channel MOSFET M₁₅to V_ss.

[0041] M₁₀, M₁₁, and M₁₂are very weak transistors compared to transistor M₁₃. Therefore, transistors M₁₀, M₁₁, and M₁₂can be viewed as a very large resistor. When the voltage at Node A is greater than V_dd−V_TP, transistor M₁₃is off and transistors M₁₀, M₁₁, and M₁₂are on. This pulls the gate of transistor M₁₄low to increase the current flowing through transistor M₉, thereby decreasing the voltage of node A. When the voltage at Node A is less than V_dd−V_TP, Transistors M₁₃, M₁₀, M₁₁, and M₁₂are all on. Because transistors M₁₀, M₁₁, and M₁₂are equivalent to a very large resistor, transistor M₁₃only needs to be weakly turned on to pull the gate of transistor M₁₄high to decrease the current flowing through transistor M₉, thereby increasing the voltage of node A. At equilibrium, therefore, the voltage at node A will be maintained at V_dd−V_TP. Furthermore, the current through M₉will be inversely proportional to V_TP.

[0042] Transistors M₁₆and M₁₇are configured in a current branch between V_ddand V_ssthat parallels the branch established by transistors M₁₅, M₁₄, and M₉. Transistor M₁₆is configured to mirror the current that flows through transistor M₁₅—the gates of transistors M₁₅and M₁₆are connected to each other and to the drain of transistor M₁₅. The source of transistor M₁₆is connected to V_ssand the drain of transistor M₁₆is connected to the drain of transistor M₁₇. The source of transistor M₁₇is connected to V_dd, and the gate of transistor M₁₇is connected to V_ss.

[0043] Because of the current mirror between transistors M₁₅and M₁₆, the currents through transistors M₉and M₁₇are the same and are inversely proportional to V_TP. Accordingly, if these transistors are fabricated to be the same size they will drop the same voltage and V_cm1, the voltage at the drain of transistor M₁₇, will equal the voltage at node A. It is also possible through this circuit to set V_cm1at arbitrary voltages below or above node A by choosing an appropriate size ratio between transistor M₁₇and transistor M₉. Furthermore, because the current through both M₉and M₁₇is inversely proportional to V_TP, reference voltage V_cm1varies in proportion to V_TP. Note that M₉and M₁₇could be replaced by resistors if available 15 in the fabrication process used to create the circuits.

[0044] In the described embodiment, M₉and M₁₇are sized to set V_cm1at approximately V_dd−V_SAT−V_SW/2, where V_SATis the saturation voltage of transistors M_p1and M_p2of FIG. 4, and V_SWis the desired voltage swing of the differential outputs OUT+ and OUT−. Because V_cm1tracks V_TP, and because V_SATis a function of V_TP, the common mode output voltage will track V_SAT, ensuring that load transistors M_p1and M_p2remain in saturation in spite of process, voltage, and temperature variations.

[0045] FIG. 6 shows an exemplary implementation of a buffer 35. This circuit receives complementary clock inputs CLK+ and CLK− and produces differential input signals IN+ and IN− that are in turn received by the integrator circuit 36 of FIG. 4. Buffer 35 is designed to control the common mode voltage of IN+ and IN− and to vary this common mode voltage as a function of V_TP. Varying the common mode voltage with V_TPensures that differential transistors M_n1and M_n2remain in saturation over process, voltage, and temperature variations.

[0046] Buffer 35 comprises a simple differential amplifier having a differential pair of n-channel transistors M₂₀and M₂₁, configured through a T-resistor load formed by transistors M₂₂, M₂₃, and M₂₄. The bias of the differential pair is established by an n-channel bias transistor M₂₅that is connected as a current mirror of transistor M₁₅of FIG. 5. Accordingly, the bias current through the differential pair M₂₀and M₂₁will vary inversely in proportion to V_TP, and both the common mode voltage and the high voltage levels of IN+ and IN− will vary directly in proportion to V_TP.

[0047] Although the invention has been described in language specific to structural features and/or methodological steps, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or steps described. Rather, the specific features and steps are disclosed as preferred forms of implementing the claimed invention.