Linearly controlled CMOS phase interpolator

[0002] This invention relates to control of a CMOS phase interpolator.

[0003] Accurate control of a zero crossing point of a signal has several useful applications, including phase interpolation for a varying signal. What is needed is a phase interpolation system in which the zero crossing point varies linearly with a controllable parameter that can be varied over a finite parameter range. Preferably, the range of the zero crossing parameter should be flexible so that the range can be increased or decreased according to the particular circumstances.

[0004] These needs are met by the invention, which provides a CMOS phase interpolator in which a linear change in a parameter in the input control signal produces a linear change in phase of the output waveform relative to the input waveform. The interpolation approach works on a principle of weighted addition of two two-sided triangle waves that have a selected phase difference. The weighted sum of two triangle waves produces an output signal having a zero crossing point that ranges over the selected phase difference. Each of two spaced apart segments within the period of the triangular waves provides a zero crossing point, and the location and temporal length of each segment can be varied by choice of a relative phase of the two triangular waves.

[0005] FIG. 1 is a block diagram of an ideal interpolator.

[0006] FIGS. 2A, 2B, 2C and 2D are graphical views of first, second, third and fourth triangle waves, with the second, third and fourth waves having phases of 45°, 90° and 135° relative to the first wave.

[0007] FIGS. 3, 4 and 5 are graphical views of segments of weighted sum signals S(t;0;45), S(t;0;90) and S(t;0;135), respectively, where a zero crossing occurs.

[0008] FIG. 6 is a schematic view of a phase interpolator circuit suitable for practicing the invention.

[0009] FIG. 1A illustrates, in block diagram form, a first approach to an ideal interpolator 11A. Output signals from square wave generators, 13A and 15A, with relative phases of 0° and 90°, respectively, are received by respective triangle generators 17A and 19A. Output triangular waves from the triangle generators, 17A and 19A, are multiplied by the respective weight coefficients or gains A and 1−A (0≦A≦1), in multiplier modules 21A and 23A. The weighted triangular wave signals issued by the multiplier modules, 21A and 23A, are summed in a summer 25A, and the sum is further processed in a slicer 27A to provide a square wave output signal.

[0010] FIG. 1B illustrates a second approach to an ideal interpolator 1B, in which the square wave generator 15A and triangular wave generator 19A with 90° relative phases are deleted and replaced by a 90° signal phase shift module 20B, with all other components in FIG. 1B being substantially the same as the corresponding components in FIG. 1A. The amplitude of the output signal of each of the summer 25A and the summer 25B has a zero crossing point that varies linearly in time with variation of the gain parameter or weight A, as discussed in the following.

[0011] FIGS. 2A and 2B are graphical views of two-sided triangular waves, s(t;0) and s(t;45), respectively, each with a period T, where s(t;0) leads s(t;45) by a 45° relative phase so that

[0012] s(t;45)=s(t−T/8;0).  (1)

[0013] From a comparison of the graphs in FIGS. 2A and 2B, one verifies that the weighted sum signal

[0014] S(t;0;45;A)=A·s(t;0)+(1−A)·s(t;45)  (2)

[0015] has both positive and negative signums only in the time intervals TI(1) (0≦t≦t/8) and TI(2) (T/2≦t≦5T/8), and that the weighted sum signal has at most one zero crossing point in each of these time intervals. In the time intervals TI(1) and TI(2), the weighted sum signal becomes $\begin{array}{cc}\begin{array}{c}S\left(t;0;45;A\right)=A·t+\left(1-A\right)·\left(t-T/8\right)\\ =t-\left(1-A\right)T/8\left(0\le t\le T/8\right),\end{array}& \left(3\right)\\ \begin{array}{c}S\left(t;0;45;A\right)=A·(\left(T/2-t\right)+\left(1-A\right)·(\left(5T/8-t\right)\\ =\left(5-A\right)T/8-t\left(T/2\le t\le 5T/8\right).\end{array}& \left(4\right)\end{array}$

[0016] These two segments of the weighted sum signal S(t;0;45) are shown graphically in FIG. 3 and have the respective zero crossing values

[0017] t=t_z(1)=(1−A)·T/8εTI(1),  (5)

[0018] t=t_z(2)=(5−A)·T/8εTI(2).  (6)

[0019] The zero crossing value t_z(i) (i=1, 2) varies linearly with the gain parameter A from one end of the time interval TI(i) to the other end, as A varies from 0 to 1.

[0020] A weighted sum of the triangular waves s(t;0) and s(t;90), shown in FIGS. 2A and 2C,

[0021] S(t;0;90;A)=A·s(t;0)+(1−A)·s(t;90),  (7)

[0022] can also be formed, for waves that differ by a relative phase of 90°. From a comparison of the graphs in FIGS. 2A and 2C, one verifies that the weighted sum signal S(t;0;90;A) has both positive and negative signums only in the time intervals TI(3) (0≦t≦T/4) and TI(4) (T/2≦t≦3T/4), and that the weighted sum signal has at most one zero crossing point in each of these time intervals. In the time intervals TI(3) and TI(4), the weighted sum signal becomes $\begin{array}{cc}\begin{array}{c}S\left(t;0;90;A\right)=A·t+\left(1-A\right)·\left(t-T/4\right)\\ =t-\left(1-A\right)·T/4\left(0\le t\le T/4\right),\end{array}& \left(8\right)\\ \begin{array}{c}S\left(t;0;90;A\right)=A·(\left(T/2-t\right)+\left(1-A\right)·(\left(3T/4-t\right)\\ =\left(3-A\right)T/4-t\left(T/2\le t\le 3T/4\right).\end{array}& \left(9\right)\end{array}$

[0023] These two segments of the weighted sum signal S(t;0;90;A) are shown graphically in FIG. 4 and have the respective zero crossing values

[0024] t=t_z(3)=(1−A)·T/4εTI(3),  (10)

[0025] t=t_z(4)=(3−A)·T/4εTI(4).  (11)

[0026] The zero crossing value t_z(i) (i=3, 4) varies linearly with the gain parameter A from one end of the time interval TI(i) to the other end, as A varies from 0 to 1.

[0027] A weighted sum of the triangular waves s(t;0) and 2(t,135), shown in FIGS. 2A and 2D,

[0028] s(t;0;135;A)=A·s(t;0)+(1−A)·s(t;135),  (12)

[0029] can also be formed, for waves that differ by a relative phase of 135°. From a comparison of the graphs in FIGS. 2A and 2D, one verifies that the weighted sum signal S(t;0;135) has both positive and negative signums only in the time intervals TI(5) (0≦t≦3T/8) and TI(6) (T/2≦t≦7T/8). Further analysis reveals that only for times t within the sub-intervals TI′(5) (T/8≦t≦T/4) and TI′(6) (5T/8≦t≦3T/4) does the zero crossing value vary linearly with the gain parameter A. Within the time intervals TI′(5) and TI′(6), the weighted sum signal becomes $\begin{array}{cc}\begin{array}{c}S\left(t;0;135;A\right)=A·t+\left(1-A\right)·\left(t-T/4\right)\\ =t-\left(1-A\right)·T/4\left(T/8\le t\le T/4\right),\end{array}& \left(13\right)\\ \begin{array}{c}S\left(t;0;135;A\right)=A·(\left(T/2-t\right)+\left(1-A\right)·(\left(7T/8-t\right)\\ =\left(7-3A\right)T/8-t\left(5T/8\le t\le 3T/4\right).\end{array}& \left(14\right)\end{array}$

[0030] These two segments of the weighted sum signal S(t;0;135) are shown graphically in FIG. 5 and have the respective zero crossing values

[0031] t=t_z(5)=(1−A)·T/4εTI′(5),  (15)

[0032] t=t_z(6)=(7−3A)·T/8εTI′(6).  (16)

[0033] The zero crossing value t_z(i) (i=5, 6) varies linearly with the gain parameter A from one end of the time interval TI′(i) to the other end, as A varies from 0 to 1.

[0034] The particular phase differences Δφ=45°, 90° and 135°, shown in FIGS. 3, 4 and 5 were chosen for illustration purposes only. Any selected phase difference Δφ in the range 0<Δφ<180° could be used here. Each choice of a pair of values (Δφ,A) will produce a pair of zero crossing values.

[0035] FIG. 6 illustrates a practical implementation of the interpolator circuit indicated in block diagram form in FIG. 1. Two complementary clock signals, CLK(t) and CLK(t)*, are received at the gates of first and second substantially identical CMOS transistors, 61 and 63, whose drain terminals are both connected through a current generator 65 to ground. The source terminals of the first and second transistors, 61 and 63, are connected to each other through a capacitor 67 and through first and second resistors, 69 and 71, in series. An intermediate point of the first and second resistors, 69 and 71, is connected to the positive input terminal of a differential amplifier 73, whose negative input terminal receives a selected, substantially constant voltage input signal VCM. The output terminal of the diff amp 73 is connected to ground across a second capacitor 75 and is connected to the gates of third and fourth substantially identical CMOS transistors, 77 and 79. The source terminals of the third and fourth transistors, 77 and 79, are connected to a common voltage source VDD, and the drain terminals of these two transistors are connected to the source terminals of the first and second transistors, 61 and 63, to provide a common mode feedback loop for the diff amp 73.

[0036] The source terminals of the first and second transistors, 61 and 63, are connected to source terminals of fifth and sixth substantially identical transistors, 81 and 83, respectively, whose gates receive two complementary second clock signals, CLKQ(t) and CLKQ(t)*, respectively, where one of the signals CLKQ(t) and CLKQ(t)* is identical to but shifted in time relative to the signal CLK(t). The drain terminals of the fifth and sixth transistors, 81 and 83, are connected through a second current generator 85 to ground.

[0037] The source terminals of the first and second transistors, 61 and 63, are also connected to source terminals of seventh and eighth transistors, 91 and 93. The drain terminal of the seventh and eighth transistors are connected to ground. The source terminals of the seventh and eighth transistors, 91 and 93, are also connected to the positive and negative input terminals, respectively, of a slicer 95, whose two output terminals are connected to positive and negative input terminals of an amplifier 97. Two output terminals of the amplifier 97 are connected to the gates of the seventh and eighth transistors 91 and 93, and to ground across third and fourth capacitors, 99 and 101, respectively. A sub-circuit 103 including the seventh and eight transistors, 91 and 93, the amplifier 97 and the third and fourth capacitors, 99 and 101, serves as a duty cycle correction unit. Output signals from the slicer 95 provide complementary square waves, one of which appears at the slicer output terminal in FIGS. 1A and 1B.