Fast lock/self-tuning VCO based PLL

[0002] The present invention is generally related to Phase Lock Loop (PLL) circuits, and more particularly to PLL semiconductor integrated circuits having integrated voltage controlled oscillators (VCOs) such as those used in wireless communication systems.

[0003] Phase Lock Loop (PLL) integrated circuits (ICs) find practical advantages in many electronic circuits, and in particular, in wireless communications systems dealing with high-speed data transfer including receivers. In wireless systems, it is critical to achieve both fast lock and perfect tuning of a voltage controlled oscillator (VCO) comprising a portion of the PLL. In conventional PLL circuits having an integrated VCO, tuning of the VCO may take a relatively long period of time which may not be tolerable in circuit designs handling high data transfer rates. The longer an oscillator takes to tune directly impacts the lock time of the PLL. Moreover, prior art semiconductor PLL circuits require a relatively large overhead circuit and extra power dissipation which are undesirable characteristics when embodied in silicon designs, such as in wideband code division multiple access (WCDMA) chipsets.

[0004] There is desired an improved PLL having both a fast lock time and an accurate self-tuning VCO having both a reduced overhead circuit and generating less power dissipation than those presently available.

[0005] The present invention achieves technical advantages as a fast lock/self-tuning VCO based PLL whereby counters used in a divider are monitored to determine the lock condition of the PLL. A digital to analog converter (DAC) controls the course tuning of the VCO and is predistorted to lineraize the tuning of the VCO. Advantageously, the present invention merges the DAC with the VCO. The present invention allows an almost perfect tuning of the VCO and fast lock operation, which is critical in wireless systems handling high speed data transfer, such as WDCMA based communications. The present invention is preferably implemented in RFSiGe or CMOS process in a WDCMA chipset, and can be used in other systems such as GSM and EDGE. The present invention is also advantageous for use in new fractional-N PLL products.

[0006] FIG. 1 depicts a PLL loop circuit according to the present invention whereby a controller monitors the state of counters forming a divider circuit;

[0007] FIG. 2 depicts a schematic of one implementation to merge a DAC with a VCO;

[0008] FIG. 3 depicts a graph of the oscillator frequency of the VCO as a function of the reverse voltage, depicting the non-linear relationship;

[0009] FIG. 4 illustrates graphs depicting how to make the oscillator frequency of the VCO function linear by predistorting the DAC to be a non-linear voltage generator having an operating curve being opposite to the effect of the varactor shown in FIG. 3;

[0010] FIG. 5 depicts a schematic illustrating another way to make to achieve linear control of the frequency by merging the DAC with the varactor;

[0011] FIG. 6 is a schematic of a weighted array using thermometer decoding for each code increment by mixing only one varactor such that the sizing of the varactor is made to have a linear relation; and

[0012] FIG. 7 depicts a binary search technique making the residue in the counters equal to zero, whereby the DAC is programmed by the binary search technique until the counter residue is zero or negligible.

[0013] An interpolation technique of the first preferred embodiment of the present invention can be applied to both integer and fractional frequency synthesizers and is seen in FIG. 1.

[0014] Initially, a PLL loop circuit 10 shown in FIG. 1 is opened and a fine-tuning input 12 to a VCO 14 is set to some fixed reference voltage (i.e. ½ supply voltage: VCC/2) and a coarse tuning input 16 is set to a minimum frequency i.e. a digital input 18 to a digital-to-analog converter (DAC) 20 is set to a digital code 00000 by a loop controller 22. The counters A and B in divider 24 are controlled by controller 22 to then start to countdown and set the division ratio, where:

[0015] N=B(P)+A.

[0016] According to the present invention, the tuning controller 22 monitors the state of each counter A and B and its residue for some predetermined time window:

[0017] T_st=M×F_refwhere M is the number of cycles of monitoring.

[0018] Since F_inis smaller than the target output frequency, where the DAC 20 digital input is set to ∅, for every F_refcycle the counters A and B will not overflow.

[0019] For each T_sttime iteration the counters will have a residue number called N_r,:

[0020] By neglecting the residue in counter A after M cycles, it can be proved that the error Δf₀in frequency is:

[0021] Δf₀(N_R)×F_refthus,

[0022] Δf₀=ΔB×P×F_ref

[0023] Examples of this interpolation technique illustrate the advantages of the present invention.

[0024] $\mathrm{Assuming}a\mathrm{linear}\mathrm{relation}:\begin{array}{cc}\mathrm{DAC}\mathrm{input}:00000& F_{\mathrm{out}}\left(\mathrm{VCO}\right):855\mathrm{MHz}\\ ⋮& ⋮\\ \mathrm{DAC}\mathrm{input}:11111& F_{\mathrm{out}}\left(\mathrm{VCO}\right):1010\mathrm{MHz}\end{array}$

[0025] With a 5-bit DAC:

[0026] K_DAC=5 MHz/LSB where K_DACis the VCO/DAC gain

[0027] Assuming a linear relation:

[0028] Referenced clock: 10 MHz

[0029] P=8 (prescalar number)

[0030] If want target frequency=880 MHz $F_{\mathrm{ref}}=10\mathrm{MHz}{F}_0=880\mathrm{MHz}N=\frac{880\mathrm{MHz}}{10\mathrm{MHz}}=88=\left(11\times 8\right)+0=⟩\left(\frac{B=11}{A=0}\right)$

[0031] Initially, the digital input at the DAC 20 input is set at ∅, and therefore, f₀=855 MHz. Now, to determine the correction of the input to the DAC 20 to get near the target frequency of 880 MHz, the Frequency error to be corrected is determined:

[0032] Δf₀=880 MHz−855 MHz=25 MHz

[0033] since Δf₀=ΔB×P×F_ref $\Delta B=\frac{\Delta \mathrm{fo}}{P\times F_{\mathrm{ref}}}=\frac{25\mathrm{MHz}}{8\times 10\mathrm{MHz}}=0.3125$

[0034] which is difficult to detect.

[0035] If M=16 clock cycles, the monitoring time of the counter residue is 16 cycles of the reference clock.

[0036] Then: ΔB_m=M×ΔB=16×0.3125=5

[0037] The residue number in the B counter is 5, and that is exactly what is needed to correct the DAC input to get the correct desired frequency:

[0038] In summary, the DAC input=0+5=5 [00101] to get

[0039] F_out=855+5×(5 MHz/_LSB)=880 MHz

[0040] Desired target frequency: 960 MHz

[0041] Where: B=12 P=8 A=∅F_ref=10 MHz

[0042] thus, frequency error Δf₀=105 MHz $\Delta B=\frac{105\mathrm{MHz}}{10\mathrm{MHz}\times 8}=1.3125$

[0043] therefore: ΔB_m=16×1.3125=21

[0044] Thus, the DAC digital input is corrected (increased) by 21 [10101] Hence:

[0045] f₀=21×5 MHz/LSB+855=960 MHz

[0046] An example of not neglecting the residue in A in the equation N=P(B)+A, is illustrated in the next example:

[0047] Δf₀=ΔN×F_ref

[0048] for: F₀=920 MHz F_ref=10 MHz $\begin{array}{c}N=\left(11\times 8\right)+4\mathrm{where}B=11\\ A=4\end{array}$ $\Delta N=\frac{\Delta \mathrm{fo}}{F_{\mathrm{ref}}}=\frac{920-855}{10}=6.5$ $\mathrm{For}16\mathrm{clock}\mathrm{cycles}\left(M=16\right)\Delta N_M=16\times 6.5=104$ $\Delta B=\frac{\Delta N_M}{P}=\frac{104}{8}=13$

[0049] Thus, the digital input to DAC 20 has to be incremented by 13 LSBs:

[0050] F_out=855+(13×5)=920 MHz

[0051] After the coarse tuning through the DAC 20, a phase detector 26 which includes a charge pump, is enabled by controller 22, the precharge circuit to Vref is disabled, and the PLL finishes the lock through fine tuning. Most of the lock time will be phase locking, after finishing the tuning.

[0052] One circuit implementation achieving the VCO tuning is shown in FIG. 2 at 30, with the varactors depicted as diodes, but alternatively could also comprise MOS—type varactors. The oscillator frequency of the VCO function of the reverse voltage is not linear, and is shown in FIG. 3.

[0053] Advantageously, according to the present invention, one way to make the oscillator frequency of the VCO function linear and get more accurate tuning is to make the DAC 20 a non-linear voltage generator with an opposite curve to that shown in FIG. 3, with the effect of the varactor operating as shown in FIG. 4.

[0054] According to an alternative embodiment of the present invention, another way to make this linear control of the frequency through the DAC 20 is to merge the DAC with the varactor, as shown at 40 in FIG. 5

[0055] Capacitor C₀is a function of (Vmin, Vmax), where $\left[\begin{array}{c}\mathrm{Vmin}\to C_0\min \\ \mathrm{Vmax}\to C_0\max \end{array}\right]$

[0056] For code=[code_n. . . code₀]=[00 . . . 0] where the capacitance is maximum and f₀is minimum, by incrementing the code by 1 from minimum, C₀is decreased, then capacitor C₁is decreased, . . . and finally capacitor C_nis decreased. If capacitors C₀, C₁and . . . C_nare sized accordingly, then the relation:

[0057] f₀=function (code) can be made almost linear, where sizing depends on the relation C (V).

[0058] However, since the array is binary weighted, then the linearity is difficult to meet.

[0059] So, another improvement according to the present invention is based on an un-weighted array using thermometer decoding, as shown at 50 in FIG. 6. For each code increment, incrementing is achieved by mixing only one varactor. Advantageously, the sizing of the varactor can be made so to have a linear relation between f₀and code.

[0060] This technique can even be applied to other types of VCOs. The present invention derives technical advantages by using the content of the counters to easily know if the VCO 14 is tuned.

[0061] For more accurate tuning, multiple adjustments of the tuning DAC 20 can be used instead of one adjustment, to overcome the problems associated with process variations and any non-linearity effects.

[0062] An example to illustrate this, similar to Example 3, is shown below.

[0063] Target frequency F₀=920 MHz

[0064] F_ref=10 MHz

[0065] N=11 (P)+4 (P:8 prescalar modulus 8/9)

[0066] Assume that the DAC gain is slightly different than 5 MHz/LSB, and in this example 5.5 MHz/LSB (process effect). [The 5.5 MHz/LSB is a prior not known]

[0067] From Example 1, ΔB=13

[0068] Using a two-step adjustment for the DAC, so:

[0069] The DAC 20 has to be incremented by 6 LSBS $\left(\le \frac{1}{2}\Delta B\right)$

[0070] Then, using another times cycle of 13 reference cycles to measure the new ΔB:

[0071] ΔB_i=6ΔA=3

[0072] Reference cycle: $\Delta N=\frac{920-888}{10}=3.2$  ΔN_m=51.2≅51

[0073] Note, normally Δf=6 LSB=5.5=33 MHz:

[0074] In the second step, the DAC digital input is moved again by 6 LSBs. The final frequency is 921 MHz, which is around 0.1% of the target frequency. By increasing the dynamic range of the tuning DAC 20 and using more reference cycles for time, and also using ΔA information for DAC adjustment, more accuracy can be achieved.

[0075] However, the number of increments of DAC 20, the number of reference cycles of calibration, and the number of adjustment steps (phases) depends on the allowed time of the calibration. An optimum design can be found in this case. For the previous example, 2 adjustment steps, 5-bit DAC, and 16 reference cycles for adjustment, needs at least 3.2 μs without accounting overhead times due to some timing set-up.

[0076] Advantageously, the overflow of the counters can be used to detect a large ΔB during tuning because ΔB max is limited by the programmed ΔB for a targeted change.

[0077] Advantages of this approach:

[0078] 1. The VCO is tuned automatically when the PLL is powered on (or on any reset) and during the lock time.

[0079] 2. The control line is precharged to almost the final setting (including charging the filter) and hence, achieving a fast lock time when switched from tuning to locking.

[0080] 3. The tuning algorithm is very simple, and does not need a large overhead circuit and time.

[0081] 4. The DAC is merged with the VCO, saving circuit silicon space and easing the tuning.

[0082] 5. Pre-distortion of the DAC eases the tuning to almost a perfect situation.

[0083] 6. The technique can be applied to any PLL type circuit, etc.

[0084] Another preferred method of performing self-turning will now be discussed. This alternate approach is based on a binary search technique to make the residue in the counter=0. So, the DAC is programmed by binary search technique until the counter residue is 0 or negligible, as shown at 60 in FIG. 7.

[0085] This approach 60 of self-tuning is similar to a successive approximation technique used in analog-to-digital converters (ADCs). This binary search technique can also be combined with the interpolation technique described with reference to FIGS. 1—4 as an automatic tuning technique. This binary search technique 60 works very well, however, it requires at least N times the reference time to finish tuning, where N is the number of bits of the VCO DAC. To reduce the tuning time, initially, M bits out of N bits (M<N) are tuned using the binary search technique, then with the interpolation technique 10 being used to determine the rest of the bits (N−M). The partition of bits depends on the allowed PLL lock time, and the accuracy of the interpolation technique. Of course, other binary search techniques can be used.

[0086] Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.