Lock Detector and Confidence System for Multiple Frequency Range Oscillator Control

This invention relates generally to video displays and particularly to the synchronization and control of display scan systems therein.

Several different types of television broadcast formats and standards are used in different locals throughout the world. Two of the most pervasive are the system used in the United States of America known as NTSC (National Television Standards Committee) and the European system known as PAL (Phase Alternating Line). In addition, several systems for providing increased picture resolution or definition, generally referred to as HDTV (High Definition Television) have been and are continuing to be developed.

While the television receivers operating in these varied systems are equally varied, certain aspects remain generally similar. For example, most television receivers include circuitry for selecting the desired television signal from among a plurality of broadcast signals available, a signal processing system which recovers the picture and sound information from the broadcast signal, systems for sequentially scanning a display device such as a cathode ray tube in both horizontal and vertical directions, and scan synchronization systems operative upon the display to coordinate display scanning to the picture and sound information.

Despite significant differences between the signal selection and signal processing functions of television receivers operating in accordance with the above-mentioned variety of broadcast systems, the functions of display scanning and synchronization are generally quite similar. Generally, picture and sound information together with scan synchronizing signals are modulated upon a broadcast carrier at the transmitter. At the receiver, the scan synchronizing signals are separated from the remainder of the picture and sound information and used to control locally generated horizontal and vertical scan signals. The latter are used to drive the scanning circuits of the display system.

Computer monitors and many video game devices are also similar to television receivers in that they include a display system, such as a cathode ray tube, which is scanned in synchronism with picture information. In such systems, the scan signals are computer generated and are used to synchronize display scan and picture information in much the same manner as television receivers.

Because the horizontal scan oscillator control used in the variety of television receivers, computer monitors and video game displays are substantially identical in overall function, it seems logical to provide a single system which may be operated for all such uses (e.g. a "universal" system). However, attempts to do so have been frustrated largely by the broad range of scan frequencies over which such a universal scan control system would be required to operate.

As is well known, the operation of display system synchronization controlling the horizontal scan oscillator is extremely demanding. Meeting these demands is made challenging by the need for precise control of both the frequency and phase of the horizontal scan oscillator. Maintaining frequency control over a broad range of reference scan frequencies generally leads to systems which lack stable precise phase control. Conversely, highly precise stable phase locking systems usually lack the ability to accommodate a wide range of frequencies.

For example, one of the most common and pervasive horizontal scan oscillator control systems used in television receivers, computer monitors, or video games is generally referred to as a phase locked loop. While a variety of different phase locked loop systems have been developed, virtually all use a phase detector which compares an oscillator output signal to the received reference synchronizing signals to produce an error voltage indicative of the difference therebetween. This error voltage is filtered by a low pass filter and amplified by an error amplifier to produce a controlling voltage for the voltage controlled oscillator. In the event the voltage controlled oscillator is precisely synchronized to the referenced synchronizing signals, the output voltage of the phase detector is zero and the frequency of the voltage controlled oscillator remains unchanged. In practice, however, this condition seldom exists and, more typically, the frequency of the voltage controlled oscillator residually differs from that of the incoming reference signals. If the difference between the oscillator and the reference signals detected by the phase detector is a phase difference or minor frequency difference, the error voltage coupled to the oscillator is sufficient to cause the oscillator to change frequency and bring its output signal toward synchronization with the reference sync signals. It has been found that most prior art phase locked loop systems respond well enough to minor variations of oscillator phase and frequency.

In most oscillator control systems including phase locked loop systems and the like, the system characteristics utilized during the synchronizing or lock-in operation of the system differ substantially from the characteristics desired during synchronization once the frequency lock has been obtained. In addition, systems having increased sophistication and complexity such as that set forth in the above-related copending application may function differently in certain subtle aspects as the system moves between conditions of acquisition of phase and frequency lock, short term lock and synchronization, and/or the existence of long term undisturbed frequency and phase lock. Accordingly, there arises a need for oscillator control systems which may perform these subtle adjustments and thereby optimize system performance under a variety of operating conditions.

Accordingly, it is general object of the present invention to provide an improved horizontal scan oscillator control system operable in response to a broad range of scan frequencies. It is a more particular object of the present invention to provide an improved horizontal oscillator control system which responds to broad frequency signals while optimizing system performance during frequency synchronization acquisition, short term phase and frequency synchronization, and long term phase and frequency synchronization.

The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements and in which:

FIG. 1 sets forth a block diagram of a television receiver constructed in accordance with the present invention;

FIG. 2 sets forth a block diagram of an adaptive oscillator control system constructed in accordance with the present invention;

FIG. 3 sets forth a sample look-up table of oscillator ranges and frequencies in accordance with the present invention;

FIG. 4 sets forth a flow diagram of the confidence system of the present invention; and

FIG. 5 sets forth a flow diagram of the lock detection system of the present invention.

FIG. 1 sets forth a block diagram of a television receiver constructed in accordance with the present invention and generally referenced by numeral 20. Receiver 20 includes a receiving antenna 21 coupled to a tuner 22. Tuner 22 is coupled to an intermediate frequency system 23 which in turn is coupled to a synchronous detector 24. A signal processor 25 which includes conventional systems for processing picture and sound information is coupled to a display 26. A sync signal separator 30 is coupled to the output of synchronous detector 24. A vertical scan oscillator and control system 31 is coupled to sync separator 30 and a vertical output amplifier 32. The latter is coupled to display 26. A horizontal scan oscillator and control system 40 is coupled to sync separator 30 and a horizontal output amplifier 41. The latter is coupled to display 26 and a high voltage generator 42. High voltage generator 42 produces the high voltage potential required for display 26.

A horizontal oscillator range system constructed in accordance with the above-referenced copending application and referenced by numeral 43 is coupled to horizontal oscillator and control 40. A clock circuit 47 is coupled to horizontal oscillator range control system 43. A processor 44, which in its preferred form comprises a conventional microprocessor, is coupled to horizontal oscillator range system 43 and includes a processor memory 45 which in turn includes a look-up table to be described below in greater detail. A source of video-type information 46 is coupled to processor 44. A horizontal lock detector 49 constructed in accordance with the present invention is coupled to horizontal oscillator and control 40 and to horizontal oscillator range system 43. A confidence system 48 constructed in accordance with the present invention is coupled to horizontal oscillator range and control 40 and horizontal oscillator range system 43. To facilitate the discussions which follow, horizontal oscillator and control 40, horizontal oscillator range system 43, processor 44, memory 45, video-type source 46, clock circuit 47, confidence system 48 and horizontal lock detector 49 are collectively grouped within the dashed line area of FIG. 2 and will be generally referred to as adaptive horizontal scan system 27 in the discussions which follow. With the exception of adaptive horizontal scan system 27, television receiver 20 may be constructed in accordance with virtually any of the known conventional fabrication techniques.

Accordingly, antenna 21 receives one or more broadcast television signals which are applied to tuner 22. Tuner 22 includes conventional channel selection systems for selecting the desired one of the plurality of signals received by antenna 21 and for converting the selected signal to an intermediate frequency signal which is further processed by intermediate frequency processor 23. Synchronous detector 24 operates upon the intermediate frequency signal to recover the picture, sound, and scan synchronizing signals modulated thereon. The picture information is further processed by signal processor 25 to produce appropriate picture information signals to control display 26.

Sync separator 30 extracts the vertical and horizontal scan synchronizing signals from the composite signal at the output of synchronous detector 24 and applies them to vertical scan oscillator and control 31, horizontal scan oscillator and control 40 and to horizontal range system 43. In response to the applied vertical scan signals from sync separator 30, vertical oscillator and control 31 produces a synchronized vertical scan signal which is amplified by vertical scan output system 32 and applied to display 26 to produce the vertical scan thereof.

The operation of adaptive horizontal scan system 27 is best understood by bearing in mind that the system therein is capable of responding to a wide variety of television broadcast signal formats as well as a variety of non-broadcast uses such as color monitors or other display drive systems. Accordingly, as is set forth in the above-referenced copending application, the system divides the spectrum of frequencies to be encountered into a plurality of oscillator frequency ranges. Thereafter, the system examines the horizontal synchronization signals if a nonstandard signal is being processed or the known scan frequency if a standard signal is received to identify the oscillator frequency range and establish a first approximation of horizontal oscillator frequency. The oscillator frequency is then adjusted to a second frequency approximation. In accordance with an important aspect of the present invention, the confidence system monitors oscillator consistency until the horizontal oscillator has remained within the established frequency range for a predetermined period of time to establish system "confidence". Once confidence is established, the system activates a phase-locked loop and operates to achieve frequency and phase lock which is detected by a lock detector. With lock detected, the system frequency hold-in window is widened and the static phase error within the loop is minimized in a final frequency adjustment.

Returning to FIG. 1, the horizontal synchronization signals produced by sync separator 30 are applied to horizontal oscillator and control 40 and to horizontal oscillator range system 43. In addition, a video-type signal which identifies the type of signal being received (i.e. NTSC, PAL, HDTV, or Monitor) is applied to processor 44. For standard broadcast signals, the horizontal scan frequency is known and the correct oscillator range can be determined directly. However, for nonstandard or monitor-type signals, the horizontal scan frequency is not known and a known relationship between the color subcarrier and the horizontal scan does not exist. Therefore, in such case, horizontal oscillator range system 43 responds to the applied horizontal sync signals and counts the number of clock signals from clock circuit 47 which occur during the period between horizontal sync signals. This number of clock signals occurring during the sync interval provides a convenient number for referencing the synchronization signal frequency and is coupled to processor 44. As is set forth below in FIG. 3 in greater detail, the look-up table within memory 45 of processor 44 provides an organized correlation between this clock signal number and the oscillator frequency range within which the oscillator must be operated for synchronization. In addition, the memory within look-up table 45 provides a corresponding oscillator range control number for each frequency range. Thus, processor 44 examines the look-up table within memory 45 and couples the corresponding oscillator range control number to horizontal oscillator range system 43. Horizontal oscillator range system 43 converts the oscillator range control number to an analog control signal which is applied to horizontal oscillator and control 40 to establish a first frequency approximation for the system's horizontal scan oscillator.

Thereafter, the system provides a second frequency approximation by either of two different operations depending upon the type of signal applied. In the event a broadcast type signal is applied, processor 44 and horizontal range control system 43 compare the horizontal oscillator frequency to the maximum and minimum frequencies of the appropriate frequency range and implement a second frequency adjustment upon the horizontal oscillator within horizontal oscillator and control 40 until the oscillator frequency is within the appropriate frequency range.

If, on the other hand, the system is responding to a monitor signal, the second frequency approximation must be carried forward differently due to the lack of a known standard by which the frequency maximum and minimum may be known. Thus, to provide the second frequency approximation in response to monitor-type signals, horizontal oscillator range system 43 examines a sample of oscillator signals which has been frequency multiplied by some convenient multiplying factor. Different factors may be selected, however, it has been found advantageous to utilize a signal which is sixty four times the horizontal scan frequency of the system. Thus, horizontal oscillator range system 43 counts the number of frequency multiplied signals which occur between horizontal synchronization signals from sync separator 30. Thereafter, horizontal oscillator range system 43 adjusts the oscillator frequency within oscillator and control 40 until the number of frequency multiplied signals between horizontal sync signals corresponds to the predetermined multiplier (i.e. sixty four). In other words, if a frequency multiplied signal of sixty four times the horizontal scan frequency is used, the second approximation of oscillator frequency is achieved by adjusting oscillator frequency until sixty four pulses are counted between horizontal sync signals.

In either event (broadcast signal or monitor signal reception), confidence system 48 functions in accordance with an important aspect of the present invention following the second frequency approximation. While the operation of confidence system 48 is set forth below in greater detail, suffice it to note here that confidence system 48 determines whether the horizontal oscillator within oscillator and control 40 remains within the desired frequency range for a predetermined time interval to establish confidence in the second frequency approximation. Once confidence is established, confidence system 48 produces an enabling signal which is coupled to oscillator and control 40 and to horizontal oscillator range system 43 to enable phase locked loop 28 (seen in Figure and described below). As a result, the phase locked loop within horizontal oscillator and control 40 establishes frequency synchronization of the horizontal oscillator with the horizontal synchronization signals from sync separator 30. Lock detector 49 functions in the manner described below to detect the establishment of horizontal synchronization, or lock, and cause horizontal oscillator range system 43 to transfer the control of the horizontal scan oscillator entirely to oscillator and control system 40. Thereafter, oscillator and control 40 functions in the manner described below in greater detail to minimize static phase error and maintain frequency and phase synchronization between the horizontal scan oscillator and the reference horizontal synchronizing signals.

The synchronized output signals of horizontal oscillator and control 40 are further amplified by horizontal output 41 and applied to display 26 to produce the synchronized horizontal scan of display 26. In addition, high voltage system 42 responds to the output signal of horizontal output 41 to produce a high voltage operating potential for display 26.

Because of the adaptive character of the present invention system, it will be apparent to those skilled in the art that while the environment in which the present invention system is situated in FIG. 1 is that of a television receiver, it may be used with equal benefit in a variety of environments such as computer monitors and video game displays or other display systems.

FIG. 2 sets forth a block diagram of the present invention horizontal scan control system generally referenced by numeral 27. By way of overview, it should be noted that the present invention system set forth in FIG. 2 forms three basic subsystem components which are shown by dashed line markings 28, 29 and 33. The portion of the present invention system enclosed within dashed line 28 comprises a phase locked loop which is activated by the present invention confidence system and is operative to maintain the instantaneous or high speed corrections of the present invention system. The portion enclosed within dashed line reference 29 forms a static error corrector which responds to long term corrections within phase locked loop 28. In accordance with an important aspect of the present invention, the combination of phase locked loop 28, static error corrector 29, and horizontal lock detector 190 cooperate to minimize the static phase error within the system once phase locked loop 28 has achieved frequency and phase lock. The remainder of the system of FIG. 2 enclosed within dashed line 33 provides the above-described adaptive function of the present invention system which enhances the performance of phase locked loop 28 and static error corrector 29 to accommodate a broad range of synchronization frequencies and both broadcast and monitor type signals.

With respect to phase locked loop 28, a phase detector 50 which may be constructed generally in accordance with conventional fabrication techniques, includes an input 51 coupled to sync separator 30 (seen in FIG. 1), an input 52 and an output 53. A low pass filter 54 is coupled to phase detector output 53. An error amplifier 55 includes an input 56 coupled to the output of low pass filter 54, an enabling signal input 59, and a pair of outputs 57 and 58. A summing network 100 includes an input 101 coupled to output 57 of error amplifier 55, an input 102 and an output 103. A voltage controlled oscillator 104 is coupled to output 103 of summing network 100 and to a frequency divider 105. The latter is coupled to horizontal output 41 (seen in FIG. 1) and to input 52 of phase detector 50.

Static phase error corrector 29 includes threshold detector 60 coupled to output 58 of error amplifier 55 and having a pair of outputs 61 and 62. An up/down counter 63 includes an up-counting input 68 coupled to output 61 of threshold detector 60 and a down-counting input 69 coupled to output 62 of threshold detector 60. Up/down counter 63 further includes reset input 65, a clock signal input 66 and an input 64 and an output 67. A limit decoder 70 is coupled to output 67 of up/down counter 63 and includes a pair of outputs 71 and 72. A multiplexer 123 includes a pair of inputs 124 and 125 coupled to outputs 71 and 72 respectively, a pair of inputs 138 and 139, a pair of outputs 126 and 127, and a selection input 128. An up/down counter 73 includes an up-counting input 79 coupled to output 126 of multiplexer 123 and a down-counting input 78 coupled to output 127 of multiplexer 123. Up/down counter 73 further includes an output 74 coupled to a digital to analog converter 85 and a clock signal input 75. A summing network 120 includes an input 121 coupled to converter 85, an input 122, and an output 119 coupled to input 102 of summing network 100. A pulse circuit 84 is coupled to vertical oscillator and control 31 (seen in FIG. 1). The output of pulse circuit 84 is coupled to an input of multiplexer 210, the output of which is coupled to clock signal input 75 of up/down counter 73. The output of pulse circuit 84 is further coupled to a delay network 83. The output of delay network 83 is coupled to reset signal input 65 of up/down counter 63. A center number source 82 is coupled to data input 64 of up/down counter 63.

As mentioned above, the remainder of the present invention system within dashed line 33 provides the multiple frequency operation of the present invention system which includes a horizontal measuring pulse and reset generator 130. Generator 130 includes an input 131 coupled to a source of horizontal oscillator signal at frequency divider 105, an input 132 coupled to a source of horizontal synchronization signal from sync separator 30 (seen in FIG. 1), an input 137 coupled to the output of oscillator 104. In addition, generator 130 includes an input 135, input 133 and a pair of outputs 134 and 129. A horizontal measuring counter 150 includes an output 153, a reset input 152 and a clock input 151. A clock circuit 145 produces a periodic clock signal and is coupled to input 133 of generator 130 and input 151 of horizontal measuring counter 150. Output 134 of generator 130 is coupled to reset input terminal 152 of horizontal measuring counter 150. A processor circuit 154 which, in its preferred form comprises a conventional microprocessor, includes a memory and look-up table 155. In accordance with conventional fabrication techniques, processor 154 and memory 155 are coupled via a multiple line coupling 156. Processor 154 includes an input 157 coupled to output 223 of latch 220, an output 204, an output 158 coupled to input 135 of generator 130 and an output 159 which is coupled to digital to analog converter 166, the output of which is coupled to input 122 of summer 120. An OR gate 200 includes an input 202 coupled to output 204 of processor 154, an input 201 coupled to output 173 of confidence circuit 170 and an output 203 coupled to a reset input 205 of lock detector 190. A measuring window generator 160 includes an input 161 coupled to output 153 of horizontal measuring counter 150, an input 162 coupled to output 158 of processor 154 and an input 163. Measuring window generator 160 further includes a pair of outputs 164 and 165. A confidence circuit 170 includes a clock signal input 172 coupled to output 134 of generator 130 and an output 173 coupled to input 59 of error amplifier 55. Confidence circuit 170 further includes an input 171 coupled to output 183 of horizontal oscillator frequency detector 180. Frequency detector 180 includes a reset input 188 coupled to output 134 of generator 130, a pair of inputs 185 and 186 coupled to outputs 164 and 165 of measuring window generator 160, and an output 183 coupled to input 171 of confidence circuit 170 and to input 147 of AND gate 146. Horizontal oscillator frequency detector 180 further includes a pair of outputs 181 and 182 coupled to inputs 139 and 138 respectively of multiplex circuit 123 and input 187 coupled to output 129 of generator 130. A horizontal lock detector 190 includes an input 191 coupled to output 129 of generator 130, an input 194 coupled to a source of vertical blanking signals (not shown), and a pair of inputs 192 and 193 coupled to outputs 127 and 126 respectively of multiplex circuit 123. Horizontal lock detector 190 further includes an output 195 coupled to input 163 of measuring window generator 160 and to input 148 of AND gate 146. The vertical blanking pulse applied to input 194 of horizontal lock detector 190 is further coupled to a pulse circuit 84, the output of which is coupled to input 211 of multiplexer 210 and to delay network 83. Multiplexer 210 includes an input 212 coupled to the output 134 of generator 130 and a selector input 213 coupled to the output 195 of horizontal lock detector 190. Multiplexer 210 includes an output 214 coupled to clock input 75 of counter 73.

In operation and by way of overview, the function of the present invention system is believed best understood by initially noting that the adaptive portion of the system within dashed line 33 determines the appropriate frequency range for the horizontal oscillator 104 and then provides first and second frequency approximations and adjustments to bring the frequency of oscillator 104 into the appropriate frequency range and close enough to the correct frequency to achieve initial synchronization. Thereafter, confidence is established by confidence system 170 and the phase locked loop formed by combination of phase detector 50, low pass filter 54, error amplifier 55, voltage controlled oscillator 104 and frequency divider 105 is enabled and responds to changes of oscillator frequency or phase in a generally conventional manner to obtain lock which is detected by horizontal lock detector 190. In the final operation, summing network 100 and the static phase error portion of the system within dashed line 29 responds to longer duration oscillator errors to reduce or eliminate static phase error.

With this overview, the present invention system may be understood in greater detail. Upon the activation of the host television receiver or monitor type environment in which the system of FIG. 2 is operated, several initial actions take place more or less simultaneously. A succession of horizontal synchronization signals are separated from the received signal and applied to horizontal measuring pulse and reset pulse generator 130. The clock circuit 145 produces crystal controlled stable periodic high frequency clock signals. While the frequency of clock signals selected for clock circuit 145 is, to some extent, a matter of design choice, it has been found advantageous to utilize a clock signal frequency equal to four times that of the NTSC chrominance subcarrier or approximately fourteen megahertz. Thus, clock 145 produces clock signals which are applied to horizontal measuring pulse and reset pulse generator 130, and to horizontal measuring counter 150. Measuring counter 150 counts the number of clock signal pulses between resets. In addition, processor 154 produces a video-type indicative signal which is coupled to generator 130 and to measuring window generator 160. The purpose of the video-type signal is to provide an indication to the system as to the signal format being applied. Any number of conventional systems may be used to input the video-type information to processor 154, including a user switch setting. Initially, the video-type information allows the system to either go to the appropriate oscillator range for standard signals or use the following procedure for nonstandard monitor-type signals. Thus, in accordance with an important aspect of the present invention when a nonstandard signal is received, horizontal measuring counter 150 accumulates a count of input clock signal pulses which is reset at the horizontal sync signal rate by the output 134 of generator 130. Because the output signal of generator 130 is timed to the applied horizontal synchronization signals, the periodic reset of counter 150 produces a series of output counts at output 153 corresponding to the number of clock signal pulses occurring between horizontal sync signals. The horizontal measuring counter output 153, just prior to reset is latched by latch 220 and the latched output 223 is therefor indicative of the horizontal sync signal frequency and is coupled to processor 154 which utilizes a look-up table within memory 155 to convert the output count of counter 150 to the corresponding oscillator range code number for nonstandard or monitor-type signals.

A typical look-up table may be seen in the table of FIG. 3 showing the spectrum of frequencies to which the present invention system is intended to respond divided into sixteen oscillator frequency ranges. In further accordance with the present invention, each frequency range has an assigned oscillator range code number which, in the embodiment of FIG. 2, comprises a four-bit digitally encoded number. Thus, processor 154 is able to convert the number of clock signals of a nonstandard signal occurring between horizontal sync pulses and counted by counter 150 to a four-bit digitally encoded number indicative of the frequency range within which the horizontal synchronization signals are found. As mentioned, the oscillator range code of a standard signal is known and may be selected by processor 154 in response to video type. Processor 154 thereafter couples the four-bit digitally encoded oscillator range code number to digital-to-analog converter 166 which, in accordance with conventional fabrication techniques, converts the oscillator range code number to a corresponding analog signal which is applied to summing network 120. The analog signal produced by digital-to-analog converter 166 is coupled to oscillator 104 via summing networks 120 and 100 to produce an initial control signal and establish the first frequency approximation for voltage controlled oscillator 104.

With the initial frequency approximation performed, oscillator 104 produces an output signal which is approximately sixty four times the desired horizontal oscillator output signal to be utilized by the remainder of the system. Frequency divider 105 converts the output of oscillator 104 to a horizontal oscillator output signal which is coupled to horizontal measuring pulse and reset pulse generator 130 and to phase detector 150. At this point, an initial frequency approximation for oscillator 104 has been performed by the present invention system in establishing an initial oscillator range and applying a first approximation current to oscillator 104.

With the appropriate oscillator frequency range established and the first approximation of oscillator frequency applied, the second frequency approximation is carried forward by the present invention system. It should be noted that this second approximation involves a "finer" or more narrow frequency adjustment than provided by the first frequency approximation. It should also be noted that the second frequency approximation uses either of two processes which are determined by the type of signal being processed. As mentioned above, processor 154 produces an output signal indicative of the video-type or type of signal format being applied (e.g. NTSC, PAL, HDTV or Monitor). This video-type signal is applied to horizontal measuring pulse and reset pulse generator 130 which produces the appropriate horizontal sync measuring pulse and horizontal measuring counter reset pulse. In addition, the output of horizontal measuring counter 150 together with the video-type signal are coupled to measuring window generator 160. Measuring window generator 160 responds to the video-type signal and to the output count of measuring counter 150 to produce a pair of output signals at outputs 164 and 165 which correspond to the frequency maximum and frequency minimum of the oscillator frequency range determined by the output count of counter 150. These frequency maxima and frequency minima signals are applied to horizontal frequency detector 180.

Frequency detector 180 also receives the horizontal sync measuring pulse at input 187 and the output of oscillator 104 at input 184. The horizontal sync measuring pulse applied to input 187 comprises a signal corresponding in frequency and phase to the frequency divided horizontal output signal of oscillator 104 having a pulse width determined in accordance with the type of signal format being processed. It should be noted that oscillator 104 operates at a frequency which is sixty four times the desired horizontal output signal. As mentioned above, the second frequency approximation is also carried forward using one process in response to television broadcast signals such as NTSC, PAL, or HDTV or in an alternative process in the event a monitor type or non-standard input signal is applied.

In response to a broadcast type signal, the frequency maxima and frequency minima signals produced by measuring window generator 160 provide a pair of timing signals which are used by oscillator frequency detector 180 to determine the frequency relationship between the horizontal sync measuring pulse and the desired oscillator frequency range. This determination is carried forward by examining the timing relationshop between the horizontal sync measuring pulse at input 187 and the frequency maxima and minima signals at inputs 185 and 186 respectively. Thus, in the event the horizontal sync measuring pulse occurs earlier than the frequency maxima signal at input 185, detector 180 determines that the frequency of oscillator 104 is above the desired frequency range and thus oscillator 104 leads the desired frequency range. Conversely, if the horizontal sync measuring pulse occurs after the frequency minima signal at input 186, detector 180 determines that the frequency of oscillator 104 is below the desired frequency range and thus lags the desired range. Finally, if the horizontal sync measuring pulse occurs between the frequency maxima and minima signals, oscillator 104 is within the desired frequency range, or simply, in range. Thus, horizontal oscillator frequency detector 180 compares the timing of the horizontal sync measuring pulse to the frequency maxima and frequency minima signals produced by measuring window generator 160 and provides output signals indicating whether oscillator 104 leads, lags, or is within the desired frequency range. An output signal at output 181 of frequency detector 180 indicates oscillator 104 is leading or above the desired frequency range while an output signal at output 182 indicates that oscillator 104 is lagging or below the desired frequency range. An output signal at output 183 indicates that oscillator 104 is within the desired frequency range and is applied to confidence system 170 and is used thereby to enable error amplifier 55 as described above.

The oscillator leading or oscillator lagging signals of frequency detector 180 are coupled to inputs 138 and 139 of a multiplex circuit 123. The oscillator in range output signal is coupled to input 147 of AND gate 146. The remaining input 148 of AND gate 146 is coupled to output 195 of horizontal lock detector 190. The operation of horizontal lock detector 190 is described below in greater detail. However, suffice it to note here that output 195 of lock detector 190 produces an output signal when oscillator 104 is locked or in sync. AND gate 146 includes an output 149 which is coupled to selection input 128 of multiplex circuit 123. Multiplex circuit 123 is constructed in accordance with conventional fabrication techniques and is, in essence, a switch which alternatively couples either inputs 138 and 139 or inputs 124 and 125 to outputs 126 and 127 respectively. In the absence of a signal at selection input 128, multiplex circuit 123 couples inputs 138 and 139 to outputs 126 and 127 which in turn are coupled to up-counting input 79 and down-counting input 78 of counter 73.

Thus, frequency detector 180 examines the timing of successive horizontal sync measuring pulses and produces output signals at either outputs 181 or 182 indicative of the frequency relationship between oscillator 104 and the desired frequency range. If, for example, oscillator 104 is too high in frequency, the comparison of horizontal sync measuring pulse and the frequency maxima signal input to detector 180 described above produces an output signal at output 181 which is coupled to down-counting input 78 of counter 73 through multiplex circuit 123. In response, counter 73 decreases its output count so long as a down-counting signal is applied to terminal 78. Conversely, in the event oscillator 104 is lower in frequency than desired, detector 180 produces an output signal at output 182 which is coupled by multiplex 123 to up-counting input 79 of counter 73 causing its output count to be increased. The output count of counter 73 is applied to digital to analog converter 85 which produces a corresponding analog control signal which is combined with the control signal from digital-to-analog converter 166 within summer 120. The output of summer 120 which now includes both the first frequency approximation control current produced by digital-to-analog converter 166 and an adjusting current corresponding to the output count of counter 73 is applied to oscillator 104 via summing network 100 to produce a further frequency correction. This process continues as frequency detector 180 continues to examine the horizontal sync measuring pulse timing and alter the output count of counter 73 accordingly to produce a further correction current. At some point in this process, equilibrium is reached and the frequency of oscillator 104 is found to be within the desired frequency range causing detector 180 to produce an oscillator in range signal at output 183. This oscillator in range signal causes confidence circuit 170 to initiate the confidence examination process described below. In addition, the oscillator in range signal produces one of the necessary inputs to activate AND gate 146. The remaining input, however, remains unavailable until horizontal synchronization or lock is detected in the manner described below. At this point, however, no selection signal is applied to selection input 128 of multiplex circuit 123 and thus inputs 138 and 139 remain coupled to outputs 126 and 127. So long as frequency detector 180 continues to determine that the frequency of oscillator 104 is within range, no further correction signals are produced or applied to counter 73. Thus, so long as oscillator 104 remains in range, the output count of counter 73 remains unchanged and the control signal applied to input 121 of summer 120 remains similarly unchanged. At this point, the second frequency approximation for oscillator 104 is complete and the frequency of oscillator 104 is determined by the combined control signals produced by digital-to-analog converters 166 (first approximation) and digital-to-analog converter 85 (second approximation).

In accordance with an important aspect of the present invention, phase lock loop 28 has remained inoperative during the first and second frequency approximations and will continue to remain inoperative until confidence circuit 170 produces an enabling signal at output 173 which is applied to enabling input 59 of error amplifier 55. The operation of confidence circuit 170 is described below in FIG. 4, however suffice it to note here that the essential function of confidence circuit 170 is to provide an indication that the above-described first and second frequency approximations have correctly placed the frequency of oscillator 104 within the appropriate oscillator frequency range. In the circuit shown in FIG. 2, confidence circuit 170 utilizes the horizontal rate reset signal of measuring counter 150 to establish a predetermined interval during which the oscillator in range signal at input 171 must be continuously maintained in order for confidence circuit 170 to produce an output signal at output 173. This output signal then enables error amplifier 55 of phase lock loop 28 once sufficient confidence has been established.

The operation of measuring window generator 160 and horizontal oscillator frequency detector 180 is carried forward in a different manner in response to a monitor-type input signal. This alternative operation is required because of the absence of a known standard for monitor-type signals. Thus, upon completion of the above-described determination of the appropriate oscillator frequency range and the establishment of the initial control current by converting the corresponding oscillator control range number to an appropriate control current by digital-to-analog converter 166, frequency detector 180 performs the second frequency approximation for monitor-type signals by counting the number of input pulses applied to input 184 between the occurrence of horizontal sync measuring pulses at input 187. It is desired that the frequency of oscillator 104 be sixty four times that of the incoming horizontal sync signals. Thus, in the event frequency detector 180 counts more than sixty four input pulses at input 184 between horizontal sync measuring pulse inputs at input 187, an oscillator leading condition has been detected and a correcting signal is produced at output 181. Conversely, in the event frequency detector 180 counts fewer than sixty four input pulses at input 184 between horizontal sync measuring pulses, an oscillator lagging or too slow condition has been detected and a corresponding correction signal is applied to output 182. The operation of multiplex circuit 123 and up/down counter 73 in response to the output signals of frequency detector 180 in the monitor mode of operation is identical to that set forth above and thus the output count of counter 73 is adjusted until the control signal resulting from the conversion of the output count of counter 73 and applied to oscillator 104 alters the frequency of oscillator 104 to produce approximately sixty four pulse signals at input 184 between horizontal sync measuring pulses. At this point, frequency detector 180 produces an oscillator in range signal at output 183 which is processed by confidence circuit 170 in the manner described above until a predetermined confidence is established and phase lock loop 28 is activated by enabling amplifier 55. Once confidence has been established and phase lock loop 28 has been enabled, the system again performs in the same manner regardless of which type of signal input is provided. Thus, the enabling of error amplifier 55 by the confidence signal at input 59 closes the operational loop of phase lock loop 28.

Phase detector 50 responds to the simultaneous application of reference horizontal sync signals from sync separator 30 (seen in FIG. 1) and a sample of the frequency divided output of oscillator 104. In accordance with conventional fabrication techniques, phase detector 50 produces an error signal at output 53 which is coupled by low pass filter 54 to the input of error amplifier 55. Amplifier 55 imposes a predetermined signal gain upon the applied error signal which is operative upon voltage controlled oscillator 104 to shift the frequency of oscillation thereof. In further accordance with conventional fabrication techniques, voltage controlled oscillator 104 operates at a predetermined multiple (in this case sixty four) of the desired horizontal scan frequency. Thus, to produce the desired horizontal output signal, the output signal of voltage controlled oscillator 104 is frequency divided by this predetermined frequency multiple. The output signal is coupled to phase detector input 52 and to horizontal output system 41 (seen in FIG. 1). Frequency or phase errors between the sample of frequency divided oscillator output signal at input 52 of phase detector 50 and reference synchronizing signals at input 51 produce appropriate error voltages at output 53 which are amplified and applied to oscillator 104 to adjust the frequency of oscillator 104 until the frequency divided oscillator signal again corresponds in frequency and phase to the reference sync pulses.

Horizontal lock detector 190 includes a pair of inputs 192 and 193 which are coupled to inputs 78 and 79 respectively of counter 73. Lock detector 190 is also coupled to a source of vertical blanking signal at input 194 and a source of horizontal sync measuring pulse at input 191. In the manner set forth in FIG. 5, horizontal lock detector 190 monitors the input signals to counter 73 and, upon establishing the absence of correcting signal inputs to counter 73 for a predetermined period of time, produces a horizontal lock output signal at output 195. As mentioned above, this horizontal lock signal forms the second input at input 148 of AND gate 146. Thus, with input signals to gate 146 which simultaneously indicate an oscillator in range condition and the attainment of horizontal lock by phase lock loop 28, AND gate 146 produces an output signal at output 149 which is applied to selection input 128 of multiplex 123. In response, multiplex 123 switches the coupling to outputs 126 and 127 away from inputs 138 and 139 respectively to inputs 124 and 125. This switching of multiplexer 123 causes counter 73 to be decoupled from inputs 138 and 139 and further control of counter 73 is provided by the static phase error correction portion of the present invention system enclosed within dashed line 29. Processor 154 produces a high output signal at output 204 in the absence of incoming horizontal sync signals. OR gate 200 resets horizontal lock detector 190 if horizontal sync is absent or if a frequency adjustment is required. In addition, the horizontal lock signal of horizontal lock detector 190 is applied to measuring window generator 160 to widen the frequency window therein once lock is obtained.

At this point, the present invention system has determined the appropriate frequency range for oscillator 104, completed first and second frequency approximations to place the oscillator within the desired range, established confidence and activated phase locked loop 28 to achieve synchronization. The objective of the remainder of the present invention system is to reduce any static phase error occurring by ignoring short duration or small magnitude frequency and phase correction and instead responding solely to large magnitude frequency corrections having an extended duration. As is set forth in the above identified related application, threshold detector 60 and counter 63 respond to detect large frequency corrections and to average such changes over a vertical scan interval. Limit decoder 70 responds to the occurrence of substantial count changes of counter 63 to produce up-counting or down-counting signals which are coupled by multiplexer 123 to counter 73 changing its output count and the control signal applied to oscillator 104 which, in effect, shifts the static or free-running frequency of oscillator 104 to remove the need for the large magnitude long duration corrections and avoid objectionable static phase error.

More specifically, the output of threshold detector 60 is unresponsive to the phase locked loop error signal unless and until it rises above or drops below a predetermined upper and lower signal amplitude limit. However, in the event the error signal exceeds a predetermined upper threshold or drops below a lower threshold, an output signal is produced at output 61 or 62 of threshold detector 60.

Up/down counter 63 comprises a conventional up/down counter which responds to an up-counting signal at input 68 to increase its count or to a down-counting signal at input 69 to decrease its count. The clock input of up/down counter 63 is coupled to the output of frequency divider 105. Thus, up/down counter 63 counts upwardly at the horizontal output signal rate whenever input 68 is energized or downwardly whenever input 69 is energized and remains unchanged in the absence of both. In addition, a vertical rate reset pulse is produced by pulse circuit 84 in response to an input vertical blanking signal from vertical oscillator and control 31. This vertical rate reset pulse is delayed by a delay network 83 and applied to reset terminal 65. Also, a predetermined center count number stored in center number circuit 82 is applied to the data input of counter 63 each time a reset pulse is applied to reset input 65. Thus, in normal operation and in the absence of an input signal from threshold detector 60, counter 63 is reset at the vertical scan rate to produce an output count at terminal 67 which corresponds to the predetermined center number stored in circuit 82. This process continues and the output of counter 63 at output terminal 67 remains constant at the predetermined center number so long as no signal is applied to up-counting terminal 68 or down-counting terminal 69. If however, the amplitude of error signal produced by phase detector 50 exceeds either limit, indicating of a large frequency correction of oscillator 104, the output count of counter 63 is changed accordingly.

Limit detector 70 responds to the output count of counter 63 and compares the output count to predetermined high and low count limits. In the event an increased count beyond the upper limit is decoded, output 71 which is coupled to up-counting terminal 79 of counter 73 by multiplexer 123 is energized. Conversely, output counts of counter 63 below the lower limit result in an output signal at terminal 72 which is also coupled to down-counting terminal 78 of counter 73 by multiplexer 123. In the absence of output counts from counter 63 exceeding either count limit, limit decoder 70 does not energize either up-counting terminal 79 or down-counting terminal 78.

Because the output count of counter 73 is converted to a corresponding analog signal by digital to analog converter 85 in the manner described above and applied to input 102 of summer 100, changes of the output count of counter 73 produce corresponding changes of the control signal applied to input 102 of summer 100. The control signal applied to voltage controlled oscillator 104 is the combination of inputs 101 and 102 and therefore, changes at input 102 causes corresponding changes of frequency of voltage controlled oscillator 104.

The output count of counter 73 continues to be adjusted by threshold detector 60, counter 63 and limit decoder 70 until the frequency of oscillator 104 is established at the correct free-running frequency as indicated by the ab sence of error signals within phase lock loop 28 sufficient to activate threshold detector 60. Thereafter, the control signal provided by counter 73 and digital-to-analog converter 85 together with the oscillator range control derived control signal provided by digital-to-analog converter 166 remain constant and minor frequency and phase corrections are made by phase lock loop 28 to maintain the synchronization of oscillator 104.

FIG. 3 sets forth an exemplary look-up table used by the present invention system and generally referenced by numeral 175. Table 175 includes a first column 176 headed ORC and a pair of numeric columns 177 and 178. Column 176 displays the oscillator range control numbers corresponding to the sixteen frequency ranges within which the overall frequency spectrum of the present invention system is required to perform. It will be apparent to those skilled in the art that the frequency spectrum of any given system may be divided into different numbers of oscillator ranges without departing from the spirit and scope of the present invention. Columns 177 and 178 set forth numbers corresponding to the accumulated clock signal counts derived by horizontal measuring counter 150 (seen in FIG. 2) which occurred between horizontal synchronization signals in the manner described above. Column 177 sets forth numbers corresponding to the upper frequency limit of each corresponding oscillator range while the numbers set forth in column 178 correspond to the lower limits of each corresponding oscillator frequency range. Examination of table 175 reveals that each oscillator frequency range overlaps the adjacent range. This has been found advantageous in that it provides a hysteresis effect for the present invention system which is necessary to assure that the occurrence of synchronization frequencies at or near the limit of an oscillator frequency range will not cause the system to become unstable and oscillate between ranges. While any number of priority systems may be used to resolve this overlap, it has been found advantageous to configure memory 155 and processor 154 (seen in FIG. 2) to select the oscillator frequency range which initially is encountered.

FIG. 4 sets forth a flow diagram of the operation of confidence circuit 170 (seen in FIG. 2) generally referenced by numeral 300. Beginning at a starting point 301, the system moves to a decision step 302 in which a determination is made as to whether standard video signal is applied. In the event a nonstandard signal is applied, the system moves to a decision step 303 in which a determination is made as to whether a frequency adjustment is required (i.e. a flag FA is set). In the event flag FA is set, the system moves to a decision step 304 in which a determination is made as to whether the horizontal scan oscillator is within the selected oscillator frequency range. If the scan oscillator is found at step 304 to be within range, the system moves to a decision step 305 in which a determination is made as to whether the confidence number is fifteen. It should be noted at this point that the confidence number referred to in FIG. 4 represents the output count of a confidence counter and provides a numeric indication of the consistency with which the system oscillator has remained within the selected range. The counter used provides outputs from zero to fifteen with zero representing no confidence and fifteen representing maximum confidence. It will be apparent to those skilled in the art that other counters having different output count numbers may be used without departing from the spirit and scope of the present invention. Thus, once again, with a determination at step 305 that confidence has not reached fifteen, the system moves to a step 306 in which the confidence number is incremented or changed upwardly by one number. Thereafter, the system returns to start 301 and once again proceeds. Thus, each time the system recycles through steps 302, 303, 304, 305 and 306, the condition exists in which flag FA continues to be set while the oscillator has remained within range through successive examinations.

Accordingly, as the system cycles through steps 302 through 306, the confidence number is incrementally increased indicating a growing "confidence" in the consistency of the first and second frequency approximations described above. With this process continuing, eventually the confidence number is incremented to fifteen and the next cycle arriving at step 305 results in a determination that confidence has achieved fifteen. In response, the system moves to step 307 in which flag FA within the system is reset to indicate that frequency adjustment is no longer required. This in effect indicates to the system that confidence is present and that the first and second frequency adjustments have proven to be correct. As is described above, further refinements or finer adjustments and control of the system oscillator frequency will continue to be carried forward as described above, however so long as the frequency adjust flag FA within the system is reset to indicate that no adjustment is needed (FA=0), the basic first and second frequency approximations will remain unchanged. This condition is, in essence, the definition of system confidence and, as is described above in FIG. 2, results in the output by confidence circuit 100 at output 173 of an enabling signal applied to input 59 of error amplifier 55 which, as is also described above, activates phase locked loop 28.

Returning to FIG. 4, the system leaves step 307 after resetting the frequency adjust flag FA and then proceeds to step 301 and thereafter to step 302. If the video remains a nonstandard video, the system then moves to step 303 in which a determination is made that frequency adjustment is not required. Since no frequency adjust is needed, the system moves to a step 314 in which a determination is made as to whether horizontal lock exists. The manner in which horizontal lock is determined will be set forth in FIG. 5 below in greater detail. However, suffice it to note here that step 314 refers to the operation of horizontal lock detector 190 seen in FIG. 5 and described below. In the event a horizontal lock condition exists, the system moves to step 315 in which a system loop is created which in essence requires the system to respond to vertical blanking signals to provide more long term correction. The system in either case moves to a decision step 316 in which a determination is made as to whether the horizontal oscillator is within range. If the oscillator is within range, the system moves to a step 317 in which the confidence count is set to fifteen and thereafter to a decision step 318 in which a determination is made as to whether the frequency of the system oscillator is below a predetermined frequency with the prescribed range. If the oscillator is found at step 318 to be low, the system moves to a step 311 in which the horizontal oscillator tuning counter (counter 73 in FIG. 2) is incremented afterwhich the system returns to step 301.

If, however, the indication at step 318 shows the oscillator is not low, the system moves to a step 319 in which a determination is made as to whether the oscillator is greater than a predetermined frequency within a prescribed range. If the oscillator is not too high, the system returns directly to step 301. If however, the oscillator is found to be high at step 319, the system moves to a step 312 in which the horizontal oscillator tuning counter 73 is decremented one count after which the system returns to step 301.

Thus, so long as frequency adjustment is not required (FA=0), the system continues to cycle through the loop formed by steps 303, steps 314 through 319, and steps 311 or 312 in which confidence of the system in the first and second frequency approximations remains and in which the above-described static phase error or long term corrections continue to take place as required.

It should be noted that at steps 304 and 316 a determination is made as to whether the oscillator frequency is within the selected frequency range. It should be recalled that step 304 is part of the confidence establishing loop while step 316 is part of the long term static phase error correction operation of the system. In both loops, upon a determination at either step 304 or 316 that the system oscillator is no longer in range, the system moves to a step 308 in which a determination is made as to whether the confidence number is zero. If the confidence number is zero, the system moves to a step 309 in which flag FA is set within the system to indicate a frequency adjustment is required. If, however, confidence at 308 is not zero, the system moves to a step 313 which the confidence number is decremented. Thereafter, the system moves to step 310 in which a determination is made as to whether the oscillator is leading (frequency too high) and, if found to be leading, the system moves to a step 312 in which the horizontal oscillator counter is decremented after which the system returns to step 301. If, however, it is found at step 310 that the oscillator is not leading, the system moves to a step 311 in which the horizontal oscillator counter is incremented after which the system returns to step 301.

Thus, once the system has received an indication in steps 304 or 316 that the oscillator is not in range, the system cycles through steps 308 through 312 and 313 in which the oscillator counter is appropriately incremented or decremented to place the oscillator within range. Once the appropriate count is reached, a determination is made that the oscillator is within range and the system returns to the loop formed by steps 302 through 307 to again establish confidence. Once confidence is established, the system is given an indication that no further frequency adjustment is required and will return to the path within flow diagram 300 through steps 314 through 319 to again maintain long term frequency maintenance and static phase error correction.

FIG. 5 sets forth a flow diagram of the operation of lock detector 190 (seen in FIG. 2) generally referenced by numeral 350. At the outset, it should be noted that the operation of lock detector 190 shown in FIG. 5 corresponds to step number 314 in the confidence system flow diagram shown in FIG. 4. It should also be recalled that the operation of lock detector 190 in FIG. 2 produces a horizontal lock indicating signal HL which operates multiplexer 210 to reduce the clock rate of counter 73. The signal HL also enables AND gate 146 so that when the oscillator is in range, multiplexer 123 shifts the system to its long term or static phase error correction mode.

The system begins at step 351 from which it moves to a step 370 in which it checks that the video sync is present. If sync in not present, the lock counter is reset to zero and flag HL is reset. The system then returns to step 351. If sync is present, then the system moves to step 352 in which a determination is made as to whether frequency adjustment is required. It should be recalled as described above, the existence of an indicator within the system that frequency adjustment is not required is interpreted by the system as established confidence in the first and second frequency approximations. Thus, if at step 352, it is determined that no frequency adjustment is required (FA=0), system confidence is present and the system moves to step 353 in which a determination is made as to whether the horizontal oscillator tuning counter (counter 73 in FIG. 2) is being incremented. In the event the horizontal oscillator tuning counter is being incremented, the system moves to step 360. If, however, no counter incrementing is occurring, the system moves to step 354 in which a determination is made as to whether the horizontal oscillator tuning counter is being decremented. If the horizontal oscillator tuning counter is being decremented, the system moves to step 360. If not, however, the system proceeds to a decision step 355 in which a determination is made as to whether horizontal lock is present (HL=1). If horizontal lock is present, the system moves to a step 356 in which the horizontal lock counter is set to thirty one. It should be noted that the horizontal lock counter comprises a counter within the system having an output count from zero to thirty one. The output count provided by the horizontal lock counter is utilized to determine the existence of horizontal lock in the manner described below. Suffice it to note here, however, that an output count of thirty one of the horizontal lock counter indicates the existence of a lock condition to the remainder of the system and counts below thirty one indicate its absence. Thus, following the setting of the horizontal lock counter to thirty one at step 356, the system returns to step 351. Once again, the system determines at step 352 whether a frequency adjustment is required. If no frequency adjustment is required, the system again moves to steps 353 and 354 in which a determination is made as to whether the horizontal oscillator tuning counter is being incremented or decremented. So long as no frequency adjustment is required and the horizontal counter is not being incremented or decremented, the system will return to step 355. If a determination is made at step 355 that horizontal lock is not present, the system moves to a decision step 357 in which a determination is made as to whether the lock counter number is thirty one. If the lock counter number is thirty one, the system moves to a step 358 and flag HL is set so as to provide to the remainder of the system an indication that horizontal lock is present. If, however, the lock number found at step 357 is not thirty one, the system moves to a step 359 in which the lock counter is incremented. In either event, the system again returns to step 351 and continues. Thus, so long as frequency adjustment is not required and so long as the horizontal oscillator tuning counter is not being incremented or decremented, the system will repeatedly cycle through steps 352 through 359 and accumulate a lock counter output sufficient to set a horizontal lock indicator HL within the system. Thus, it will be apparent to those skilled in the art that the present invention system detects a horizontal lock condition upon the prolonged absence of horizontal oscillator tuning counter adjustment signals and the presence of a confidence indication from the confidence system for a predetermined time interval.

If, however, the system upon returning to step 352 determines that frequency adjustment is required (FA=1), the system moves to a step 365 in which the lock counter is reset to zero and flag HL is reset. Thereafter, the system returns to step 352. Thus, the lock counter will continue to be reset to zero and no progress toward an indication of horizontal lock will take place until a determination is made at step 352 that frequency adjustment is not required. This is consistent with the system function which requires the establishment of confidence in the first and second frequency approximations before the phase locked loop is enabled and horizontal lock is obtained. Once a determination is made at step 352 that frequency adjustment is not required, the system moves to steps 353 and 354 to determine the existence of incrementing or decrementing signals at the horizontal oscillator tuning counter. If an indication is found in either steps 353 or 354 that counter adjustment is taking place, the system moves to step 360 in which a determination is made as to whether horizontal lock has been detected. In the event horizontal lock has not been detected, the system moves to a step 361 in which the lock counter is reset to zero after which the system returns to step 351. If, however, a determination is made at step 360 that a horizontal lock condition is indicated (HL=1), the system moves to a step 362 in which a determination is made as to whether the lock counter number is zero. If the lock counter number is zero, the system moves to a step 364 in which flag HL is reset to zero and thereafter returns to step 351. If, however, a determination is made at step 362 that the lock number is not zero, the system moves to a step 363 in which the lock number is decremented after which the system returns to step 351. It should be noted that the function of steps 360 through 364 is to permit the system to distinguish between actual loss of horizontal lock and temporary disturbances which are not indicative of a loss of horizontal lock. Thus, the time interval required to cycle through steps 360 through 364, prevents the system from overreacting to such temporary disturbances. If, however, the loss of horizontal lock indicator remains, the system resets to indicate the loss of horizontal lock and recycles to reestablish the lock condition once it returns.

What has been shown is an adaptive multiple frequency range oscillator and control system which includes confidence and horizontal lock detection systems for establishing confidence in the frequency synchronization and reliable phase and frequency lock. As a result, the system is able to accommodate a wide spectrum of scan frequencies within a single oscillator and control system by dividing the spectrum of oscillator frequencies into a plurality of oscillator ranges and places the oscillator frequency within a selected range based upon examination of the horizontal synchronization signals of the incoming signal. System operation is altered once confidence is established and lock is detected to accommodate virtually any standard broadcast system as well as a great variety of auxiliary or monitor type signal sources such as personal computers or the like. The system provides both the accommodation of a broad spectrum of scan frequencies without sacrificing the frequency and phase stability of the system.

While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects. Therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.