US 6,486,703 B2Grant
Programmable logic array with vertical transistors
Issue Date:2002-11-26
•67 Claims
•12 Drawing Sheets
Abstract
A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
Metadata
Assignee
- Micron Technology, Inc.
Inventors
- Wendell P. Noble
- Leonard Forbes
Application Information
Application Number:US 09/756,099
Filing Date:2001-01-08
Priority Date:1998-08-04
Art Unit:7
Classifications
IPC:
H03K 1977
Patent Drawings (12 sheets)
Description
[0002] This application is a Divisional of U.S. patent application Ser. No. 09/129,047, filed Aug. 4, 1998.
Technical Field of the Invention
[0003] This invention relates generally to integrated circuits and in particular to a programmable logic array with vertical transistors.
Background of the Invention
[0004] Logic circuits are an integral part of digital systems, such as computers. Essentially, a logic circuit processes a number of inputs to produce a number of outputs for use by the digital system. The inputs and outputs are generally electronic signals that take on one of two “binary” values, a “high” logic value or a “low” logic value. The logic circuit manipulates the inputs using binary logic which describes, in a mathematical way, a given or desired relationship between the inputs and the outputs of the logic circuit.
[0005] Logic circuits that are tailored to the specific needs of a particular customer can be very expensive to fabricate on a commercial basis. Thus, general purpose very large scale integration (VLSI) circuits are defined. VLSI circuits serve as many logic roles as possible, which helps to consolidate desired logic functions. However, random logic circuits are still required to tie the various elements of a digital system together.
[0006] Several schemes are used to implement these random logic circuits. One solution is standard logic, such as transistor-transistor logic (TTL). TTL integrated circuits are versatile because they integrate only a relatively small number of commonly used logic functions. The drawback is that large numbers of TTL integrated circuits are typically required for a specific application. This increases the consumption of power and board space, and drives up the overall cost of the digital system.
[0007] One alternative to standard logic is fully custom logic integrated circuits. Custom logic circuits are precisely tailored to the needs of a specific application. This allows the implementation of specific circuit architectures that dramatically reduces the number of parts required for a system. However, custom logic devices require significantly greater engineering time and effort, which increases the cost to develop these circuits and may also delay the production of the end system.
[0008] A less expensive alternative to custom logic is the “programmable logic array.” Programmable logic arrays take advantage of the fact that complex combinational logic functions can be reduced and simplified into various standard forms. For example, logical functions can be manipulated and reduced down to traditional Sum of Products (SOP) form. In SOP form, a logical function uses just two types of logic functions that are implemented sequentially. This is referred to as two-level logic and can be implemented with various conventional logic functions, e.g., AND-OR, NAND-NAND, NOR-NOR.
[0009] One benefit of the programmable logic array is that it provides a regular, systematic approach to the design of random, combinational logic circuits. A multitude of logical functions can be created from a common building block, e.g., an array of transistors. The logic array is customized or “programmed” by creating a specific metallization pattern to interconnect the various transistors in the array to implement the desired function.
[0010] Programmable logic arrays are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focused through lenses and masks to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the “critical dimension” (CD) or minimum “feature size” (F) of the photolithographic process. The minimum feature size imposes one constraint on the size of the components of a programmable logic array. In order to keep up with the demands for larger programmable logic arrays, designers search for ways to reduce the size of the components of the array.
[0011] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a programmable logic array that uses less surface area of a semiconductor wafer as compared to conventional arrays.
Summary of the Invention
[0012] The above mentioned problems with programmable logic arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A programmable logic array is described which is formed with vertical transistors.
[0013] In one embodiment, a programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
Brief Description of the Drawings
[0014] FIG. 1 is a simplified block diagram of a high-level organization of a digital computer including one or more programmable logic arrays formed with vertical transistors according to the teachings of the present invention.
[0015] FIG. 2 is a simplified block diagram of an embodiment of a programmable logic array according to the teachings of the present invention.
[0016] FIG. 3 is a schematic diagram of one embodiment of a programmable logic array according to the teachings of the present invention.
[0017] FIGS. 4 through 11 are top and front views that illustrate a number of embodiments of a logic plane according to the teachings of the present invention.
[0018] FIGS. 12, 13A, 13B, 14, 15, 16, 17, 18, 19, 20, and 21 illustrate generally various stages of one embodiment of a method of forming an array of logic cells according to the teachings of the invention.
Detailed Description of the Invention
[0019] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
[0020] The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense.
[0021] The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or the substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on,” “side,” (as in sidewall), “higher,” “lower,” “over,” and under are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
[0022] Throughout this specification the designation “n+” refers to semiconductor material that is heavily doped n-type semiconductor material, e.g., monocrystalline silicon or polycrystalline silicon. Similarly, the designation “p+” refers to semiconductor material that is heavily doped p-type semiconductor material. The designations “n−” and “p−” refer to lightly doped n and p-type semiconductor materials, respectively.
[0023] FIG. 1 is a simplified block diagram of a high-level organization of a digital computer 10. A digital computer 10 is a system whose functional elements consist of an arithmetic/logic unit (ALUs) 20, a control unit 30, a memory unit 40 and an input/output (I/O) device 50. Every computer system has a native set of instructions that specify operations to be performed on data by the ALU 20 and other interactions between the ALU 20, the memory unit 40 and the I/O devices 50. The memory units 40 contain the data plus a stored list of instructions.
[0024] The control unit 30 coordinates all operations of the ALU 20, the memory unit 40 and the I/O devices 50 by continuously cycling through a set of operations that cause instructions to be fetched from the memory unit 40 and executed. Many of the logic functions performed by these components can include a programmable logic array with vertical transistors according to the teachings of the present invention. With respect to the ALU 20, the control unit 30 and the I/O devices 50, arbitrary logic functions may be realized in the “sum-of-products” form. A logic function sum-of-products may be implemented using any of the equivalent two-level logic configurations: AND-OR, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, NAND-AND or OR-AND.
[0025] FIG. 2 is a simplified diagram of a programmable logic array (PLA), indicated generally at 100, and constructed according to the teachings of the present invention. PLA 100 includes two major constituents: a first logic plane 120 and a second logic plane 130. The first and second logic planes 120 and 130 are formed using an array of vertical transistors. In one embodiment, the first and second logic planes 120 and 130 each comprise NOR logic circuits such that PLA 100 implements NOR-NOR logic. In other embodiments, first and second logic planes 120 and 130 are constructed from arrays of vertical transistors that are configured to implement AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND logic.
[0026] Input lines 125 are coupled to receive a number of input signals. Inverter/drivers 150 are coupled to the input lines 125 such that first logic plane 120 is capable of receiving each of the input signals and their complements. First logic plane 120 produces a number of output signals that are logical combinations of the signals from inverters/drivers 150. The output signals from first logic plane 120 are provided to second logic plane 130 via interconnection lines 122. Second logic plane 130 produces a number of output signals that are logical combinations of the signals from interconnection lines 122.
[0027] In addition, various control circuits and signals not detailed herein initiate and synchronize the PLA 100 operation as known to those skilled in the art. The PLA 100 implementation described with respect to FIG. 2 is illustrative only and is not intended to be exclusive or limiting.
[0028] FIG. 3 is a schematic diagram illustrating generally an architecture of one embodiment of a programmable logic array (PLA), indicated generally at 300, and constructed according to the teachings of the present invention. PLA 300 implements an illustrative logical function using a two level logic approach. Specifically, PLA 300 includes first and second logic planes 310 and 320. In this example, the logic function is implemented using NOR-NOR logic. First and second logic planes 310 and 320 each include an array of vertical transistors that are configured to implement the logical function of PLA 300.
[0029] It is noted that the configuration of FIG. 3 is provided by way of example and not by way of limitation. Specifically, the teachings of the present application are not limited to programmable logic arrays in the NOR-NOR approach. Further, the teachings of the present application are not limited to the specific logical function shown in FIG. 3. Other logical functions can be implemented in a programmable logic array with vertical transistors using any one of the various two level logic approaches.
[0030] First logic plane 310 receives a number of input signals at input lines 312. In this example, no inverters are provided for generating complements of the input signals. However, first logic plane 310 can include inverters to produce the complementary signals when needed in a specific application.
[0031] First logic plane 310 includes a number of vertical transistors that form an array. The transistors are located at the intersection of input lines 312 and interconnect lines 314. Not all of the transistors are operatively connected in the first logic plane. Rather, the transistors are selectively coupled to the input and interconnection lines so as to implement a desired logic function. Thus, some transistors are left unconnected. This selective interconnection is referred to as “mask programming” since the logical function implemented by the programmable logic array is “programmed” into the array by masking steps that are used in the generation of the conductors that interconnect the transistors in the array.
[0032] In this embodiment, each of the interconnect lines 314 acts as a NOR gate for the input lines 312 that are connected to the interconnect lines 314 through the transistors of the array. For example, interconnection line 314aacts as a NOR gate for the signals on input lines 312band 312c. That is, p-channel pull up transistor 316amaintains interconnect line 314aat a high potential unless one or more of the transistors that are coupled to interconnect line 314aare turned on by a high logic level signal on an input line.
[0033] In a similar manner, second logic plane 320 comprises a second array of transistors that are selectively interconnected to provide the second level of the two level logic needed to implement a specific logical function. In this embodiment, the array of transistors is also configured such that the output lines 318 comprise a logical NOR function of the signals from the interconnection lines 314 that are coupled to particular output lines through the vertical transistors of the second logic plane 320.
[0034] FIGS. 4 through 11 illustrate a number of embodiments for implementing a logic plane with vertical transistors for use in a programmable logic array. FIGS. 4 and 5, 6 and 7, 8 and 9, and 10 and 11 are top and side views, respectively, of the various embodiments. For purposes of clarity, only a portion of each logic plane is shown in each Figure.
[0035] Generally, the logic planes of the illustrated embodiments include a number of pillars of monocrystalline semiconductor material. These pillars form the basis for the vertical transistors of a logic plane. For example, logic plane 350aof FIGS. 4 and 5 includes pillars 352a, 354a, 356a, and 358a. The pillars are separated from adjacent pillars by a number of orthogonal trenches.
[0036] Each pillar includes at least three vertically aligned regions extending from a semiconductor substrate or insulator layer. Again, with reference to FIGS. 5, pillar 352aincludes first source/drain region 360a, body region 362a, and second source/drain region 364a. As indicated by the Figures, the body regions are lightly doped, e.g., p-semiconductor material, such that the pillar can provide a fully depleted transistor structure with channels formed along a side surface of the body region between the first and second source/drain regions.
[0037] The embodiments illustrated in FIGS. 6 through 11 also include this basic architecture for a programmable logic array: an array of monocrystalline semiconductor pillars separated by orthogonal trenches and each having at least three vertically aligned regions.
[0038] In each embodiment, the array of pillars can be “programmed” to implement a particular logic function by the selective formation of conductive lines in the trenches that separate adjacent rows of pillars. The conductive lines can be formed by chemical vapor deposition of, for example, metal or polysilicon as described in more detail below. Trenches separating rows of adjacent pillars can house one or two conductive lines. Further, these conductive lines can either form transistor gates or body contacts. In embodiments supporting body contacts, a particular conductive line can provide an input signal to transistors, e.g., a signal to a gate, in the programable logic array while other conductive lines provide a body bias (fixed or synchronous with a conductive line in a trench on the opposite side of the pillar) for transistors of the array.
[0039] With conductive lines passing on each side of a pillar, gates can be formed on both sides of each pillar. Thus, by selectively forming the conductive lines, a single pillar can implement the function of either one transistor, two transistors or half of a transistor, e.g., one conductive line forms gates for pillars that are on opposite sides of the trench. The layout of the conductive lines of each embodiment is described in turn below.
[0040] FIGS. 4 and 5 illustrate a “split gate” embodiment In this embodiment, two conductive lines are formed in each trench that separates adjacent rows of pillars. For example, conductive lines 366aand 368aare formed in trench 370a. With this architecture, gates can be formed on two, opposite sides of a pillar. For example, conductive lines 368aand 372aform gates on opposite sides of pillar 358a. This allows pillar 358ato house two transistors; each with a channel region along one of the sides of pillar 358a. Alternatively, pillar 358acan implement a single transistor by coupling conductive lines 368aand 372ato the same input signal. When a pillar implements the functionality of two transistors, this provides the advantage of increasing the density of the array. However, when a pillar of this embodiment implements a single transistor this provides redundancy on the input signals provided to the transistor.
[0041] FIGS. 6 and 7 illustrate an embodiment of a logic plane 350bwith a single conductive line formed between adjacent rows of pillars. The conductive lines in this embodiment form gates for selected pillars to implement a desired logic function for the logic plane. Conductive lines 366band 368bform gates on either sides of pillar 354b.
[0042] FIGS. 8 and 9 illustrate another embodiment of a logic plane 350c. In this logic plane, two conductive lines are formed in trenches that separate adjacent rows of pillars. Conductive lines 372cand 368cform body contacts for pillars 352cand 354c, and 356cand 358c, respectively. These conductive lines can provide a synchronous or fixed body bias. Conductive lines 366cand 374care formed so as to provide gates for selected pillars of the logic plane. For example, conductive line 366cforms a gate for pillar 354cand conductive line 374cforms a gate for pillar 358c.
[0043] FIGS. 10 and 11 illustrate another embodiment of a logic plane 350d. In this logic plane, a single conductive line is formed in each trench that separates adjacent rows of pillars. Conductive lines 368dand 372dprovide a body contact for pillars 352dand 354d, and 356dand 358d, respectively. Conductive line 366dselectively gates the pillars on either side of trench 370dso as to implement a desired logic function for logic plane 350d.
[0044] FIGS. 12, 13A, 13B, 14, 15, 16, 17, 18, 19, 20, and 21 illustrate generally one embodiment of a method of forming a logic plane for a programmable logic array according to the teachings of the present invention. In this embodiment, a portion of the logic plane, indicated generally at 400 is formed using bulk silicon processing techniques and is described, by way of example, with respect to a particular technology having a minimum lithographic “feature size,” F, which is also sometimes referred to as a “critical dimension” (CD), of 0.4 microns. However, the process steps described below can be scaled accordingly for other minimum feature sizes without departing from the scope of the invention.
[0045] In FIG. 12, a P+ silicon starting material is used for substrate 305. A first source/drain layer 500, of approximate thickness of 0.2 microns is formed at a working surface of substrate 305. In one embodiment, first source/drain layer 500 is N+ silicon formed by ion-implantation of donor dopants into substrate 305. In another embodiment, first source/drain layer 500 is N+ silicon formed by epitaxial growth of silicon upon substrate 305. On the first source/drain layer 500, a semiconductor epitaxial layer 505, such as P− silicon of 0.4 micron approximate thickness, is formed, such as by epitaxial growth. Layer 505 is referred to as body layer 505.
[0046] A second source/drain layer 510, such as N+ silicon of 0.1 to 0.2 microns approximate thickness, is formed at a surface of the epitaxial layer 505, such as by ion-implantation of donor dopants into P− epitaxial layer 505 or by epitaxial growth of N+ silicon on P− epitaxial layer 505. A thin layer of silicon dioxide (SiO2), referred to as pad oxide 515, is deposited on the second source/drain layer 510. Pad oxide 515 has a thickness of approximately 10 nanometers. A layer of silicon nitride (Si3N4), referred to as pad nitride 520, is deposited on pad oxide 515. Pad nitride 520 has a thickness of approximately 100 nanometers.
[0047] A photoresist layer is deposited outwardly from pad nitride 520. The photoresist layer is exposed through a mask to define parallel minimum dimension stripes in the Y-direction. In the embodiment of FIG. 13A, trenches 402 are formed through the stripe pattern in the photoresist layer. Trenches 402 extend through pad nitride 520, second source/drain layer 510, body layer 505 and into first source/drain layer 500. In this case, first source/drain layer 500 is maintained at ground potential to act as a ground plane for logic plane 400. In the embodiment of FIG. 13B, trenches 402bextend through pad nitride 520, second source/drain layer 510, body layer 505, first source/drain layer 500 and into substrate 305. In this embodiment, the ground plane is divided into a number of separate ground lines for the logic plane.
[0048] The remaining steps are described in terms of the embodiment of FIG. 13A although similar steps can be applied to complete the embodiment of FIG. 13B. The photoresist is removed by conventional photoresist stripping techniques.
[0049] Next, a second set of trenches is formed so as to create an array of semiconductor pillars. Existing trenches 402 are filled with an insulator by, for example, chemical vapor deposition of oxide layer 404. Oxide layer 404 is planarized with nitride pad 520 such as by chemical mechanical polishing (CMP) or other suitable planarization technique. Another photoresist layer is deposited and masked to define a second set of minimum dimension stripes that are orthogonal to trenches 402, i.e., in the X-direction. A nitride etchant is used to etch through pad 520. Next, a selective silicon etchant is used to etch exposed silicon to a depth approximately equal to trenches 402. A top view of this portion of decoder 400 is shown in FIG. 14.
[0050] With the photoresist layer still in place, exposed portions of oxide layer 404 are removed stopping on the silicon material at the bottom of trenches 402. The photoresist layer is then removed by conventional photoresist stripping techniques. This leaves the structure as shown in FIG. 15 with trenches 406 separating rows of semiconductor pillars. FIG. 15 explicitly shows pillars 408, 410 ,412 and 414. However, it is understood that logic plane 400 includes a large number of pillars that are formed in a number of rows and columns defined by trenches 402 and 406.
[0051] Next, conductive lines and gates are selectively formed in trenches 406. The gates are formed adjacent to selected pillars such that logic plane 400 implements a desired function. Nitride (Si3N4) is deposited by, for example, chemical vapor deposition with a thickness on the order of 10 nanometers. The nitride layer is directionally etched to leave on vertical walls only of trench 406. Thermal oxide layer 416 is grown on the bottom of trenches 406 to a thickness of approximately 100 nanometers and the nitride layer is stripped from the vertical sidewalls.
[0052] Protective oxide layer 418 is formed, for example, by growing a thin thermal oxide layer of approximately 10 nanometers on the side walls of trenches 406. Intrinsic polysilicon layer 420 is deposited by, for example, chemical vapor deposition with a thickness of approximately 50 nanometers. Layer 420 is etched by, for example, reactive ion etching (RIE) techniques to leave layer 420 on vertical sidewalls only. This structure is shown in FIG. 16.
[0053] Next, logic plane 400 is mask programmed by selectively removing portions of polysilicon layer 420 adjacent to pillars where a transistor is needed to implement a desired logic function. A gate is then formed adjacent to these pillars. As for the remaining pillars, polysilicon layer 420 acts as a spacer that prevents an address line or inverse address line from being formed sufficiently close to the pillar so as to form a gate of a transistor.
[0054] A photoresist layer is applied and selectively exposed through a mask to uncover the sidewalls, and adjacent layer 420, of selected pillars to implement the desired logical function. The exposed portions of layer 420 are etched from the vertical sidewalls in trenches 406. The resist is removed and gate insulator 422, e.g., silicon dioxide, is grown or deposited on the exposed vertical sidewalls. N+ polysilicon is deposited by chemical vapor deposition with a thickness of approximately 50 nanometers. The polysilicon layer is directionally etched to leave layer 424 on vertical surfaces only and to expose the tops of layer 420 as shown in FIG. 17.
[0055] At this point, the process can take one of two paths depending on whether the embodiment incorporates body contacts. If no body contacts are included, all remaining nitride is selectively stripped. Techniques known in the art are used to remove the remaining portions of layer 420 selectively to doped silicon. Oxide is deposited by chemical vapor deposition to fill the recesses in logic plane 400 and to cover the semiconductor pillars. Contacts and wiring are formed using conventional processing techniques to connect columns of pillars.
[0056] In the described embodiment, split address lines are shown. It is understood that once the gate oxide is in place, the trench can be filled with N+ polysilicon to create a single address line between the rows of pillars in a non-split address line embodiment
[0057] If body contacts are included in the embodiment, the process proceeds with the formation of these contacts as shown in FIGS. 18 through 21.
[0058] Nitride layer 430 is deposited using, for example, chemical vapor deposition to a level approximately 20 nanometers above nitride pads 520. Photoresist layer 432 is deposited and exposed through a mask to form a stripe pattern in the X-direction. Nitride layer 430 is etched briefly to expose alternate polysilicon layers 424 located in the openings of photoresist layer 432 as shown in FIG. 18.
[0059] Exposed polysilicon layers 424 are removed using an etching technique and photoresist layer 432 is removed. An oxide material is deposited in the space vacated by the polysilicon. The oxide material is planarized to the level of nitride layer 430. The oxide material is directionally etched with a reactive ion etch sufficiently to expose P− layer 505 of the pillars leaving oxide layer 434 at the bottom of trenches 406 as shown in FIG. 19.
[0060] P+ polysilicon 436 is deposited on layer 434 using chemical vapor deposition and planarized with nitride layer 430. The P+ polysilicon is etched back to below the junction of layers 510 and 505 to form body contacts as shown in FIGS. 20 and 21.
Conclusion
[0061] Embodiments of the present invention provide a programmable logic array with an increased density with respect to conventional arrays. Specifically, vertical transistors are used with conductive lines formed in trenches that separate adjacent rows of semiconductor pillars. The vertical transistors are selectively coupled by mask programming to form these lines so as to implement a desired logical function. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. For example, the logical function implemented by the programmable logic array can be varied without departing from the scope of the present invention. Further, the size of the array, the number of inputs, the number of interconnects, and the number of outputs can similarly be varied.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A programmable logic array, comprising:
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the conductive lines is a gate extending in one of the trenches adjacent the body region of at least one pillar, the gate only extending along one side of the at least one pillar;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function.
2. The array of claim 1, wherein a single conductive line is formed in each trench.
3. The array of claim 1, wherein at least two conductive lines are formed in each trench.
4. The array of claim 1, wherein a number of the conductive lines are formed in contact with the body region of pillars in their row.
5. The programmable logic array according to claim 1, wherein a first of the conductive lines contacts the body region of at least one of the pillars.
6. A programmable logic array, comprising:
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function; and
wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed.
7. The programmable logic array according to claim 6, the second conductive line is an input line into the first logic plane.
8. The programmable logic array according to claim 6, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.
9. The programmable logic array according to claim 6, wherein the array of monocrystalline semiconductor pillars include pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.
10. The programmable logic array according to claim 9, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.
11. The programmable logic array according to claim 6, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.
12. A programmable logic array, comprising:
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function; and
wherein a first of the conductive lines contacts the body region of at least one of the pillars, and the first conductive line is maintained at a constant voltage.
13. The programmable logic array according to claim 12, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.
14. The programmable logic array according to claim 12, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.
15. The programmable logic array according to claim 14, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.
16. The programmable logic array according to claim 12, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.
17. A programmable logic array, comprising:
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars, a first of the conductive lines forming a gate of one of the pillars, a second of the conductive lines contacting the body region, the body region being pulsed in synchronization with the gate; and
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function.
18. The programmable logic array according to claim 17, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.
19. The programmable logic array according to claim 17, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.
20. The programmable logic array according to claim 19, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.
21. The programmable logic array according to claim 17, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.
22. The programmable logic array according to claim 17, wherein the first source/drain regions of pillars in the first logic plane are coupled together.
23. A programmable logic array, comprising:
a substrate of a semiconductor material;
an array of monocrystalline semiconductor pillars formed on the substrate, each pillar extending in a first direction from the substrate and including a first source/drain region, a body region, and a second source/drain region that are aligned in the first direction, the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;
a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the number of conductive lines is a gate in one of the trenches adjacent the body region of at least one of the pillars, the gate extending along only one side of the pillar facing the one trench; and
an electrical connection beneath the pillars of the first logic plane electrically connecting the first source/drain region of each of the pillars of the first logic plane together.
24. The programmable logic array according to claim 23, wherein the electrical interconnection is a layer formed on the substrate beneath the pillars.
25. The programmable logic array according to claim 24, wherein the electrical interconnection layer is an N+ region.
26. The programmable logic array according to claim 25, wherein N+ interconnection layer is integral with the first source/drain regions of the pillars of the first logic plane.
27. The programmable logic array according to claim 23, wherein the first direction is generally perpendicular to the surface of the substrate.
28. An IC logic array, comprising:
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors; and
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor of the first row.
29. The logic array according to claim 28, wherein the trenches include a third trench on a side of the second row of transistors opposite the second trench, the third trench includes third conductive line defining a third gate which is connected to the at least one transistor of the second row.
30. An IC logic array, comprising:
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row;
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor; and
wherein the first and second conductive lines receive the same input signal such that the at least one transistor operates as a single transistor.
31. The logic array according to claim 30, wherein the second trench includes a third conductive line that is connected to at least one transistor of a second row of the transistors.
32. The logic array according to claim 31, wherein a third trench is on a side of the second row of transistors opposite the second trench, and the third trench includes a fourth conductive line connected to at least one transistor of the second row of transistors.
33. The logic array according to claim 32, wherein the third and fourth conductive lines are connected to the same transistor.
34. The logic array according to claim 33, wherein the first, second, third, and fourth conductive lines all extend in a same direction.
35. The logic array according to claim 34, wherein the at least one transistor of the first row and the at least one transistor of the second row are positioned in different columns in the array.
36. The logic array according to claim 32, wherein the fourth conductive line is connected to all transistors in the second row.
37. An IC logic array, comprising:
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row; and
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor.
38. The logic array according to claim 37, wherein the second conductive line is connected to all of the transistors in the first row.
39. The logic array of claim 37, wherein the first gate is connected to only one side of the at least one of the transistors in the first row.
40. The logic array of claim 39, wherein the second gate is connected to only a second side of the at least one of the transistors in the first row.
41. An IC logic array, comprising:
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors;
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor of the first row; and
wherein the second conductive line through the second and third gates controls formation of a conducting region in the at least one transistors of both the first and second rows of transistors.
42. The logic array of claim 41, wherein the substrate includes a conductive layer on which the first source/drain regions are formed.
43. The logic array of claim 41, wherein the substrate includes a conductive layer, and wherein the first source/drain regions of the first logic plane are integrally formed with the conductive layer.
44. The logic array of claim 42, wherein the substrate includes a conductive layer, and wherein the first source/drain regions of the first logic plane are doped the same as the conductive layer.
45. An IC logic array, comprising:
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors;
wherein the trenches include a third trench on a side of the second row of transistors opposite the second trench, the third trench includes third conductive line defining a third gate which is connected to the at least one transistor of the second row; and
wherein the first conductive line applies a first input signal to the first gate and the second conductive lines applies a second input signal to the second gate such that the at least one transistor of the first row operates as two transistors with one channel region on each side of the at least one transistor of the first row.
46. The logic array according to claim 45, wherein the second conductive line applies the second input signal to the third gate and the third conductive line applies a third input signal to the third gate such that the at least one transistor of the second row operates as two transistors with one channel region on each side of the at least one transistor of the second row.
47. A method of forming an IC logic array, comprising:
forming a first source\drain layer on a substrate;
forming a body layer on the first source\drain layer;
forming a second source\drain layer on the body layer;
removing a plurality of portions of the second source\drain layer, the body layer, and the first source\drain layer so as to form a first plurality of trenches extending in a first direction;
filling the first trenches with an insulator;
removing a plurality of portions of the second source\drain layer, the body layer, and the first source\drain layer so as to form a second plurality of trenches extending in a second direction;
removing the insulator from the first trenches so as to form an array of pillars each of which include the second source\drain layer, the body layer and at least a portion of the first source\drain layer;
selectively forming a first conductive line in the first trench connected to at least one of the body layer to form a gate; and
selectively forming a second conductive line in the second trench connected to the at least one of the body layer to form a body layer contact, wherein the second conductive line is formed separate from the first conductive line.
48. The method according to claim 47, wherein forming the conductive line includes forming an insulative layer on the sides of the pillars in the one of the first and second trenches, selectively removing the insulative layer from the sides of the select pillars, forming a conductive line in the one of the first and second trenches which contacts the select pillars with the insulative layer removed and is spaced from the non-select pillars on which the insulative layer remains such that gates are formed on the select pillars but not on the non-select pillars.
49. The method according to claim 47, wherein forming the conductive lines includes only removing a portion of the first source\drain layer such that the pillars are electrically connected by the first source\drain layer.
50. The method according to claim 47, wherein forming the conductive lines includes forming body contacts in trenches connected to select pillars.
51. A programmable logic array, comprising:
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;
wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed; and
wherein the first source/drain regions of pillars in the first logic plane are coupled together.
52. The programmable logic array according to claim 51, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.
53. The programmable logic array according to claim 51, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.
54. The programmable logic array according to claim 53, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.
55. The programmable logic array according to claim 51, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.
56. An IC programmable logic array comprising:
substrate;
a conductive layer on the substrate;
an array of monocrystalline semiconductor pillars on the conductive layer, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;
wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed.
57. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are coupled together.
58. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are formed on the conductive layer.
59. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are integrally formed with the conductive layer.
60. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are doped the same as the conductive layer.
61. The IC programmable logic array according to claim 56, wherein the substrate is a bulk semiconductor.
62. The IC programmable logic array according to claim 56, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.
63. The IC programmable logic array according to claim 62, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.
64. The programmable logic array according to claim 56, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.
65. An IC logic array, comprising:
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row;
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor; and
wherein the first conductive line applies a first input signal to the first gate and the second conductive lines applies a second input signal to the second gate such that the at least one transistor operates as two transistors with one channel region on each side of the at least one vertical transistor.
66. The logic array of claim 65, wherein the first gate is connected to only a first side of the transistor.
67. The logic array of claim 65, wherein the first gate is connected to only a first side of the transistor, wherein the second gate is only to a second side of the transistor, and wherein the first side is separated from the second side.
Patent Citations (178)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3657575(A) | 1972-04-01 | Taniguchi et al. | Applicant |
| US3806741(A) | 1974-04-01 | Smith | Applicant |
| US3931617(A) | 1976-01-01 | Russell | Applicant |
| US4020364(A) | 1977-04-01 | Kuijk | Applicant |
| US4051354(A) | 1977-09-01 | Choate | Applicant |
| US4252579(A) | 1981-02-01 | Ho et al. | Applicant |
| US4313106(A) | 1982-01-01 | Hsu | Applicant |
| US4604162(A) | 1986-08-01 | Sobczak | Applicant |
| US4617649(A) | 1986-10-01 | Kyomasu et al. | Applicant |
| US4630088(A) | 1986-12-01 | Ogura et al. | Applicant |
| US4663831(A) | 1987-05-01 | Birrittella et al. | Applicant |
| US4673962(A) | 1987-06-01 | Chatterjee et al. | Applicant |
| US4677589(A) | 1987-06-01 | Haskell et al. | Applicant |
| US4701423(A) | 1987-10-01 | Szluk | Applicant |
| US4716314(A) | 1987-12-01 | Mulder et al. | Applicant |
| US4740826(A) | 1988-04-01 | Chatterjee | Applicant |
| US4761385(A) | 1988-08-01 | Pfiester | Applicant |
| US4761768(A) | 1988-08-01 | Turner et al. | Applicant |
| US4766569(A) | 1988-08-01 | Turner et al. | Applicant |
| US4845537(A) | 1989-07-01 | Nishimura et al. | Applicant |
| US4888735(A) | 1989-12-01 | Lee et al. | Applicant |
| US4906590(A) | 1990-03-01 | Kanetaki et al. | Applicant |
| US4920065(A) | 1990-04-01 | Chin et al. | Applicant |
| US4920515(A) | 1990-04-01 | Obata | Applicant |
| US4929988(A) | 1990-05-01 | Yoshikawa | Applicant |
| US4949138(A) | 1990-08-01 | Nishimura | Applicant |
| US4958318(A) | 1990-09-01 | Harari | Applicant |
| US4965651(A) | 1990-10-01 | Wagner | Applicant |
| US4987089(A) | 1991-01-01 | Roberts | Applicant |
| US5001526(A) | 1991-03-01 | Gotou | Applicant |
| US5006909(A) | 1991-04-01 | Kosa | Applicant |
| US5010386(A) | 1991-04-01 | Groover, III | Applicant |
| US5017504(A) | 1991-05-01 | Nishimura et al. | Applicant |
| US5021355(A) | 1991-06-01 | Dhong et al. | Applicant |
| US5028977(A) | 1991-07-01 | Kenneth et al. | Applicant |
| US5057896(A) | 1991-10-01 | Gotou | Applicant |
| US5072269(A) | 1991-12-01 | Hieda | Applicant |
| US5083047(A) | 1992-01-01 | Horie et al. | Applicant |
| US5087581(A) | 1992-02-01 | Rodder | Applicant |
| US5102817(A) | 1992-04-01 | Chatterjee et al. | Applicant |
| US5107459(A) | 1992-04-01 | Chu et al. | Applicant |
| US5110752(A) | 1992-05-01 | Lu | Applicant |
| US5128831(A) | 1992-07-01 | Fox, III et al. | Applicant |
| US5140388(A) | 1992-08-01 | Bartelink | Applicant |
| US5156987(A) | 1992-10-01 | Sandhu et al. | Applicant |
| US5177028(A) | 1993-01-01 | Manning | Applicant |
| US5177576(A) | 1993-01-01 | Kimura et al. | Applicant |
| US5181089(A) | 1993-01-01 | Matsuo et al. | Applicant |
| US5191509(A) | 1993-03-01 | Wen | Applicant |
| US5202278(A) | 1993-04-01 | Mathews et al. | Applicant |
| US5208657(A) | 1993-05-01 | Chatterjee et al. | Applicant |
| US5216266(A) | 1993-06-01 | Ozaki | Applicant |
| US5221867(A) | 1993-06-01 | Mitra et al. | Applicant |
| US5223081(A) | 1993-06-01 | Doan | Applicant |
| US5266514(A) | 1993-11-01 | Tuan et al. | Applicant |
| US5276343(A) | 1994-01-01 | Kumagai et al. | Applicant |
| US5292676(A) | 1994-03-01 | Manning | Applicant |
| US5308782(A) | 1994-05-01 | Mazure et al. | Applicant |
| US5316962(A) | 1994-05-01 | Matsuo et al. | Applicant |
| US5320880(A) | 1994-06-01 | Sandhu et al. | Applicant |
| US5327380(A) | 1994-07-01 | Kersh, III et al. | Applicant |
| US5329481(A) | 1994-07-01 | Seevinck et al. | Applicant |
| US5341331(A) | 1994-08-01 | Jeon | Applicant |
| US5376575(A) | 1994-12-01 | Kim et al. | Applicant |
| US5378914(A) | 1995-01-01 | Ohzu et al. | Applicant |
| US5379255(A) | 1995-01-01 | Shah | Applicant |
| US5382540(A) | 1995-01-01 | Sharma et al. | Applicant |
| US5385853(A) | 1995-01-01 | Mohammad | Applicant |
| US5385854(A) | 1995-01-01 | Batra et al. | Applicant |
| US5391911(A) | 1995-02-01 | Beyer et al. | Applicant |
| US5392245(A) | 1995-02-01 | Manning | Applicant |
| US5393704(A) | 1995-02-01 | Huang et al. | Applicant |
| US5396093(A) | 1995-03-01 | Lu | Applicant |
| US5396452(A) | 1995-03-01 | Wahlstrom | Applicant |
| US5409563(A) | 1995-04-01 | Cathey | Applicant |
| US5410169(A) | 1995-04-01 | Yamamoto et al. | Applicant |
| US5414287(A) | 1995-05-01 | Hong | Applicant |
| US5414288(A) | 1995-05-01 | Fitch et al. | Applicant |
| US5416350(A) | 1995-05-01 | Watanabe | Applicant |
| US5416736(A) | 1995-05-01 | Kosa et al. | Applicant |
| US5422296(A) | 1995-06-01 | Lage | Applicant |
| US5422499(A) | 1995-06-01 | Manning | Applicant |
| US5427972(A) | 1995-06-01 | Shimizu et al. | Applicant |
| US5432739(A) | 1995-07-01 | Pein | Applicant |
| US5438009(A) | 1995-08-01 | Yang et al. | Applicant |
| US5440158(A) | 1995-08-01 | Sung-Mu | Applicant |
| US5443992(A) | 1995-08-01 | Risch et al. | Applicant |
| US5445986(A) | 1995-08-01 | Hirota | Applicant |
| US5451538(A) | 1995-09-01 | Fitch et al. | Applicant |
| US5451889(A) | 1995-09-01 | Heim et al. | Applicant |
| US5460316(A) | 1995-10-01 | Hefele | Applicant |
| US5460988(A) | 1995-10-01 | Hong | Applicant |
| US5466625(A) | 1995-11-01 | Hsieh et al. | Applicant |
| US5483094(A) | 1996-01-01 | Sharma et al. | Applicant |
| US5483487(A) | 1996-01-01 | Sung-Mu | Applicant |
| US5492853(A) | 1996-02-01 | Jeng et al. | Applicant |
| US5495441(A) | 1996-02-01 | Hong | Applicant |
| US5497017(A) | 1996-03-01 | Gonzales | Applicant |
| US5502629(A) | 1996-03-01 | Ito et al. | Applicant |
| US5504357(A) | 1996-04-01 | Kim et al. | Applicant |
| US5508219(A) | 1996-04-01 | Bronner et al. | Applicant |
| US5508542(A) | 1996-04-01 | Geiss et al. | Applicant |
| US5519236(A) | 1996-05-01 | Ozaki | Applicant |
| US5528062(A) | 1996-06-01 | Hsieh et al. | Applicant |
| US5528173(A) | 1996-06-01 | Merritt et al. | Applicant |
| US5563083(A) | 1996-10-01 | Pein | Applicant |
| US5574299(A) | 1996-11-01 | Kim | Applicant |
| US5576238(A) | 1996-11-01 | Fu | Applicant |
| US5581101(A) | 1996-12-01 | Ning et al. | Applicant |
| US5593912(A) | 1997-01-01 | Rajeevakumar | Applicant |
| US5612559(A) | 1997-03-01 | Park et al. | Applicant |
| US5616934(A) | 1997-04-01 | Dennison et al. | Applicant |
| US5627097(A) | 1997-05-01 | Venkatesan et al. | Applicant |
| US5627390(A) | 1997-05-01 | Maeda et al. | Applicant |
| US5637898(A) | 1997-06-01 | Baliga | Applicant |
| US5640342(A) | 1997-06-01 | Gonzales | Applicant |
| US5641545(A) | 1997-06-01 | Sandhu | Applicant |
| US5644540(A) | 1997-07-01 | Manning | Applicant |
| US5646900(A) | 1997-07-01 | Tsukude et al. | Applicant |
| US5674769(A) | 1997-10-01 | Alsmeier et al. | Applicant |
| US5691230(A) | 1997-11-01 | Forbes | Applicant |
| US5696011(A) | 1997-12-01 | Yamazaki et al. | Applicant |
| US5705415(A) | 1998-01-01 | Orlowski et al. | Applicant |
| US5707885(A) | 1998-01-01 | Lim | Applicant |
| US5719409(A) | 1998-02-01 | Singh et al. | Applicant |
| US5753947(A) | 1998-05-01 | Gonzales | Applicant |
| US5760434(A) | 1998-06-01 | Zahurak et al. | Applicant |
| US5780888(A) | 1998-07-01 | Maeda et al. | Applicant |
| US5789967(A) | 1998-08-01 | Katoh | Applicant |
| US5801413(A) | 1998-09-01 | Pan | Applicant |
| US5818084(A) | 1998-10-01 | Williams et al. | Applicant |
| US5821578(A) | 1998-10-01 | Shimoji | Applicant |
| US5821796(A) | 1998-10-01 | Yaklin et al. | Applicant |
| US5827765(A) | 1998-10-01 | Stengl et al. | Applicant |
| US5834814(A) | 1998-11-01 | Ito | Applicant |
| US5852375(A) | 1998-12-01 | Byrne et al. | Applicant |
| US5864158(A) | 1999-01-01 | Liu et al. | Applicant |
| US5874760(A) | 1999-02-01 | Burns, Jr. et al. | Applicant |
| US5877061(A) | 1999-03-01 | Halle et al. | Applicant |
| US5879971(A) | 1999-03-01 | Witek | Applicant |
| US5907170(A) | 1999-05-01 | Forbes et al. | Applicant |
| US5909400(A) | 1999-06-01 | Bertin et al. | Applicant |
| US5909618(A) | 1999-06-01 | Forbes et al. | Applicant |
| US5914511(A) | 1999-06-01 | Noble et al. | Applicant |
| US5917342(A) | 1999-06-01 | Okamura | Applicant |
| US5920088(A) | 1999-07-01 | Augusto | Examiner |
| US5926412(A) | 1999-07-01 | Evans, Jr. et al. | Applicant |
| US5936274(A) | 1999-08-01 | Forbes et al | Applicant |
| US5943267(A) | 1999-08-01 | Sekariapuram et al. | Applicant |
| US5946472(A) | 1999-08-01 | Graves et al. | Applicant |
| US5963469(A) | 1999-10-01 | Forbes | Applicant |
| US5973352(A) | 1999-10-01 | Noble | Applicant |
| US5973356(A) | 1999-10-01 | Noble et al. | Applicant |
| US5981995(A) | 1999-11-01 | Selcuk | Applicant |
| US5991225(A) | 1999-11-01 | Forbes et al. | Applicant |
| US6006166(A) | 1999-12-01 | Meyer | Applicant |
| US6025225(A) | 2000-02-01 | Forbes et al. | Applicant |
| US6040210(A) | 2000-03-01 | Burns, Jr. et al. | Applicant |
| US6040218(A) | 2000-03-01 | Lam | Applicant |
| US6043527(A) | 2000-03-01 | Forbes | Applicant |
| US6066869(A) | 2000-05-01 | Noble et al. | Applicant |
| US6072209(A) | 2000-06-01 | Noble et al. | Applicant |
| US6100123(A) | 2000-08-01 | Bracchitta et al. | Applicant |
| US6121084(A) | 2000-09-01 | Coursey | Applicant |
| US6134175(A) | 2000-10-01 | Forbes et al. | Applicant |
| US6143636(A) | 2000-11-01 | Forbes et al. | Applicant |
| US6150687(A) | 2000-11-01 | Noble et al. | Applicant |
| US6153468(A) | 2000-11-01 | Forbes et al. | Applicant |
| US6156607(A) | 2000-12-01 | Noble et al. | Applicant |
| US6165836(A) | 2000-12-01 | Forbes et al. | Applicant |
| US9156604 | 2000-12-01 | Forbes et al. | Applicant |
| US6172391(B1) | 2001-01-01 | Goebel | Applicant |
| US6208164(B1) | 2001-03-01 | Noble et al. | Applicant |
| JP61-140170 | 1986-06-01 | Applicant | |
| JP63-066963 | 1988-03-01 | Applicant | |
| JP5226661 | 1993-09-01 | Applicant | |
| JP11-135757 | 1999-05-01 | Applicant | |
| JP2000-164883 | 2000-06-01 | Applicant |
Non-Patent Literature (109)
- Adler, E., et al., “The Evolution of IBM CMOS DRAM Technology”, IBM J. Res. Develop., 39(1/2), 167-188, (1995).Applicant
- Asai, S., et al., “Technology Challenges for Integration Near and Below 0.1 micrometer”, Proceedings of the IEEE, 85(4), Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).Applicant
- Askin, H.O., et al., “Fet Device Parameters Compensation Circuit”, IBM Technical Disclosure Bulletin, 14, 2088-2098, (Dec. 1971).Applicant
- Banerjee, S.K., et al., “Characterization of Trench Transistors for 3-D Memories”, 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA, 79-80, (May 1986).Applicant
- Blalock, T.N., et al., “A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier”, IEEE Journal of Solid-State Circuits, 27(4), pp. 618-624, (Apr. 1992).Applicant
- Bomchil, G., et al., “Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies”, Applied Surface Science, 41/42, 604-613, (1989).Applicant
- Burnett, D., et al., “Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits”, 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 1994).Applicant
- Burnett, D., et al., “Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling”, Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, 83-90, (1995).Applicant
- Chen, M., et al., “Back-Gate Forward Bias Method for Low Voltage CMOS Digital Cicuits”, IEEE Transactions on Electron Devices, 43, 904-909, (1996).Applicant
- Chen, M.J., et al., “Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Cicuits”, IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1996).Applicant
- Chen, M.J., et al., “Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action”, IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).Applicant
- Chung, I.Y., et al., “A New SOI Inverter for Low Power Applications”, Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (1996).Applicant
- Clemen, R., et al., “VT-compensated TTL-Compatible Mos Amplifier”, IBM Technical Disclosure Bulletin, 21, 2874-2875, (1978).Applicant
- De, V.K., et al., “Random MOSEFT Parameter Fluctuation Limits to Gigascale Integration (GSI)”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996).Applicant
- De, V.K., et al., “Random Mosfet Parameter Fluctuation Limits to Gigascale Integration (GST)”, Symposium on VLSI Technology Digest of Technical Papers, 198-199, (1996).Applicant
- DeBar, D.E., “Dynamic Substrate Bias to Achieve Radiation Hardening”, IBM Technical Disclosure Bulletin, 25, 5829-5830, (1983).Applicant
- Denton, J.P., et al., “Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate”, IEEE Electron Device Letters, 17(11), 509-511, (Nov. 1996).Applicant
- Fong, Y., et al., “Oxides Grown on Textured Single-Crystal Silicon—Dependence on Process and Application in EEPROMs”, IEEE Transactions on Electron Devices, 37(3), pp. 583-590, (Mar. 1990).Applicant
- Forbes, L., “Automatic On-clip Threshold Voltage Compensation”, IBM Technical Discolure Bulletin, 14, 2894-2895, (1972).Applicant
- Forbes, L., et al., “Resonat Forward-Biased Guard-Ring Diodes for Suppression of Substrate Noise in Mixed-Mode CMOS Circuits”, Electronics Letters, 31, 720-721, (Apr. 1995).Applicant
- Foster, R., et al., “High Rate Low-Temperature Selective Tungsten”, In: Tungsten and Other Refractory Metals for VLSI Applications III, V.A. Wells, ed., Materials Res. Soc., Pittsburgh, PA, 69-72, (1988).Applicant
- Frantz, H., et al., “Mosfet Substrate Bias-Voltage Generator”, IBM Technical Disclosure Bulletin, 11, 1219-1220, (Mar. 1969).Applicant
- Fuse, T., et al., “A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).Applicant
- Gong, S., et al., “Techniques for Reducing Switching Noise in High Speed Digital Systems”, Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, Austin, TX, 21-24, (1995).Applicant
- Hao, M.Y., et al., “Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon”, Appl. Phys. Lett., 60, 445-447, (Jan. 1992).Applicant
- Harada, M., et al., “Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 96-97, (Jun. 11-13, 1996).Applicant
- Heavens, O., Optical Properties of Thin Solid Films, Dover Pubs. Inc., New York, 155-206, (1965).Applicant
- Hisamoto, D., et al., “A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs”, 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 959-961, (Dec. 8-11, 1991).Applicant
- Hodges, D.A., et al., “MOS Decoders”, In: Analysis and Design of Digital Integrated Circuits, 2nd Edition, Section: 9.1.3, 354-357, (1988).Applicant
- Holman, W.T., et al., “A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology”, IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).Applicant
- Horie, H., et al., “Novel High Aspect Ration Aluminum Plug for Logic/DRAM LSI's Using Polysilicon-Aluminum Substitute”, Technical Digest: IEEE International Electron Devices Meeting, San Francisco, CA, 946-948, (1996).Applicant
- Hu, G., et al., “Will Flash Memory Replace Hard Disk Drive?”, 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline, 2 pages, (Dec. 1994).Applicant
- Huang, W.L., et al., “TFSOI Complementary BiCMOS Technology for Low Power Applications”, IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).Applicant
- Jun, Y.L., et al., “The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications”, IEEE Electron Device Letters, 13, 430-432, (Aug. 1992).Applicant
- Jung, T.S., et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits, 31, 1575-1583, (Nov. 1996).Applicant
- Kang, H.K., et al., “Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMs”, IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 635-638, (Dec. 11-14, 1994).Applicant
- Kim, Y.S., et al., “A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum”, In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R. C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA, 675-680, (1996).Applicant
- Kishimoto, T., et al., “Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Random Access Memories (DRAMs)”, Japanese Journal of Applied Physics, 34, 6899-6902, (Dec. 1995).Applicant
- Klaus, et al., “Atomic Layer Controlled Growth of SiO2 Films Using Binary Reaction Sequence Chemistry”, Applied Physics Lett. 70(9), 1092-94, (Mar. 3, 1997).Applicant
- Kohyama, Y., et al., “Buried Bit-Line Cell for 64MB DRAMs”, 1990 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 17-18, (Jun. 4-7, 1990).Applicant
- Koshida, N., et al., “Efficient Visible Photoluminescence from Porous Silicon”, Japanese Journal of Applied Physics, 30, L1221-L1233, (Jul. 1991).Applicant
- Kuge, S., et al., “SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories”, IEEE Journal of Solid-State Circuits, 31(4), pp. 586-591, (Apr. 1996).Applicant
- Lantz, II, L., “Soft Errors Induced By Alpha Particles”, IEEE Transactions on Reliability, 45, 174-179, (Jun. 1996).Applicant
- Lehmann, et al., “A Novel Capacitor Technology Based on Porous Silicon”, Thin Solid Films 276, Elsevier Science, 138-42, (1996).Applicant
- Lehmann, V., “The Physics of Macropore Formation in Low Doped n-Type Silicon”, Journal of the Electrochemical Society, 140(10), 2836-2843, (Oct. 1993).Applicant
- Lu, N., et al., “The SPT Cell—A New Substrate-Plate Trench Cell for DRAMs”, 1985 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 771-772, (Dec. 1-4, 1985).Applicant
- MacSweeney, D., et al., “Modelling of Lateral Bipolar Devices in a CMOS Process”, IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, 27-30, (Sep. 1996).Applicant
- Maeda, S., et al., “A Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond”, 1994 Symposium of VLSI Technology, Digest of Technical Papers, Honolulu, HI, 133-134, (Jun. 7-9, 1994).Applicant
- Maeda, S., et al., “Impact of a Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond”, IEEE Transactions on Electron Devices, 42, 2117-2123, (Dec. 1995).Applicant
- Malaviya, S., IBM TBD, 15, p. 42, (Jul. 1972).Applicant
- Masu, K., et al., “Multilevel Metallization Based on Al CVD”, 1996 IEEE Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 44-45, (Jun. 11-13, 1996).Applicant
- McCredie, B.D., et al., “Modeling, Measurement, and Simulation of Simultaneous Switching Noise”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, 19, 461-472, (Aug. 1996).Applicant
- Muller, K., et al., “Trench Storage Node Technology for Gigabit DRAM Generations”, Digest IEEE International Electron Devices Meeting, San Francisco, CA, 507-510, (Dec. 1996).Applicant
- Nitayama, A., et al., “High Speed and Compact CMOS Circuits with Multipillar Surrounding Gate Transistors”, IEEE Transcations on Electron Devices, 36, 2605-2606, (Nov. 1989).Applicant
- Ohba, T., et al., “Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature”, In: Tungsten and Other Refractory Metals for VLSI Applications II, Materials Research Society, Pittsburgh, PA, 59-66, (1987).Applicant
- Ohba, T., et al., “Selective Chemical Vapor Deposition of Tungsten Using Silane and Polysilane Reductions”, In: Tungsten and Other Refractory Metals for VLSI Applications IV, Materials Research Society, Pittsburgh, PA, 17-25, (1989).Applicant
- Ohno, Y., et al., “Estimation of the Charge Collection for the Soft-Error Immunity by the 3D-Device Simulation and the Quantitative Investigation”, Simulation of Semiconductor Devices and Processes, 6, 302-305, (Sep. 1995).Applicant
- Oowaki, Y., et al., “New alpha-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell”IEICE Transactions on Electronics, 78-C, 845-851, (Jul. 1995).Applicant
- Oshida, S., et al., “Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation”, IEICE Transactions on Electronics, 76-C, 1604-1610, (Nov. 1993).Applicant
- Ott, A.W., et al., “Al303 Thin Film Growth on Si(100) Using Binary Reaction Sequence Chemistry”, Thin Solid Films, vol. 292, 135-44, (1997).Applicant
- Ozaki, T., et al., “A Surrounding Isolation-Merged Plate Electrode (Simple) Cell with Checkered Layout for 256Mbit DRAMs and Beyond”, 1991 IEEE International Electron Devices Meeting, Washington, D.C., 469-472, (Dec. 8-11, 1991).Applicant
- Parke, S.A., et al., “A High-Performance Lateral Bipolar Transistor Fabricated on SIMOX”, IEEE Electron Device Letters, 14, 33-35, (Jan. 1993).Applicant
- Pein, H., et al., “A 3-D Sidewall Flash EPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, 40, 2126-2127, (Nov. 1993).Applicant
- Pein, H., et al., “Performance of the 3-D Pencil Flash EPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, 42, 1982-1991, (Nov., 1995).Applicant
- Pein, H.B., et al., “Performance of the 3-D Sidewall Flash EPROM Cell”, IEEE International Electron Devices Meeting, Technical Digest, 11-14, (1993).Applicant
- Puri, Y., “Substrate Voltage Bounce in NMOS Self-biased Substrates”, IEEE Journal of Solid-State Circuits, SC-13, 515-519, (Aug. 1978).Applicant
- Ramo, S., et al., Fields and Waves in Communication Electronics, Third Edition, John Wiley & Sons, Inc., pp. 428-433, (1994).Applicant
- Rao, K.V., et al., “Trench Capacitor Design Issues in VLSI DRAM Cells”, 1986 IEEE International Electron Devices Meeting, Technical Digest, Los Angeles, CA, 140-143, (Dec. 7-10, 1986).Applicant
- Richardson, W.F., et al., “A Trench Transistor Cross-Point DRAM Cell”, IEEE International Electron Devices Meeting, Washington, D.C., 714-717, (Dec. 1-4, 1985).Applicant
- Sagara, K., et al., “A 0.72 micro-meter2 Recessed STC (RSTC) Technology for 256Mbit DRAMs using Quarter-Micron Phase-Shift Lithography”, 1992 Symposium on VLSI Technology, Digest of Technical Papers, Seattle, WA, 10-11, (Jun. 2-4, 1992).Applicant
- Saito, M., et al., “Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier”, 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996).Applicant
- Seevinck, E., et al., “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's ”, IEEE Journal of Solid State Circuits, 26(4), pp. 525-536, (Apr. 1991).Applicant
- Senthinathan, R., et al., “Reference Plane Parasitics Modeling and Their Contribution to the Power and Ground Path “Effective” Inductance as Seen by the Output Drivers”, IEEE Transactions on Microwave Theory and Techniques, 42, 1765-1773, (Sep. 1994).Applicant
- Shah, A.H., et al., “A 4-Mbit DRAM with Trench-Transistor Cell”, IEEE Journal of Solid-State Circuits, SC-21, 618-625, (Oct. 1986).Applicant
- Shah, A.H., et al., “A 4Mb DRAM with Cross-Point Trench Transistor Cell”, 1986 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 268-269, (Feb. 21, 1986).Applicant
- Sherony, M.J., et al., “Reduction of Threshold Voltage Sensitivity in SOI MOSFET's”, IEEE Electron Device Letters, 16, 100-102, (Mar. 1995).Applicant
- Shimomura, K., et al., “A 1V 46ns 16Mb SOI-DRAM with Body Control Techniques”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).Applicant
- Stanisic, B.R., et al., “Addressing Noise Decoupling in Mixed-Signal IC's: Power Distribution Design and Cell Customization”, IEEE Journal of Solid-State Circuits, 30, 321-326, (Mar. 1995).Applicant
- Stellwag, T.B., et al., “A Vertically-Integrated GaAs Bipolar DRAM Cell”, IEEE Transactions on Electron Devices, 38, 2704-2705, (Dec. 1991).Applicant
- Su, D.K., et al., “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, IEEE Journal of Solid-State Circuits, 28(4), 420-430, (Apr. 1993).Applicant
- Suma, K., et al., “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”, IEEE Journal of Solid-State Circuits, 29(11), pp. 1323-1329, (Nov. 1994).Applicant
- Sun, J., “CMOS Technology for 1.8V and Beyond”, Int'l Symp. on VLSI Technology, Systems and Applications: Digest of Technical Papers, 293-297, (1997).Applicant
- Sunouchi, K., et al., “A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs”, 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 23-26, (Dec. 3-6, 1989).Applicant
- Sunouchi, K., et al., “Process Integration for 64M DRAM Using an Asymmetrical Stacked Trench Capacitor (AST) Cell”, 1990 IEEE International Electron Devices Meeting, San Francisco, CA, 647-650, (Dec. 9-12, 1990).Applicant
- Suntola, T., “Atomic Layer Epitaxy”, Handbook of Crystal Growth 3, Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Elsevier, Amsterdam, 601-63, (1994).Applicant
- Sze, S.M., VLSI Technology, 2nd Edition, Mc Graw-Hill, NY, 90, (1988).Applicant
- Takai, M., et al., “Direct Measurement and Improvement of Local Soft Error Susceptibility in Dynamic Random Access Memories”, Nuclear Instruments & Methods in Physics Research, B-99, 562-565, (Nov. 7-10, 1994).Applicant
- Takao, Y., et al., “A 4-um(2) Full-CMOS SRAM Cell Technology for 0.2-um High Performance Logic LSIs”, 1997 Symp. on VLSI Technology: Digest of Technical Papers, Kyoto, Japan, 11-12, (1997).Applicant
- Takato, H., et al., “High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs”, IEEE International Electron Devices Meeting, Technical Digest, 222-225, (1988).Applicant
- Takato, H., et al., “Impact of Surrounding Gate Transistor (SGT) for Ultra-High Density LSI's”, IEEE Transactions on Electron Devices, 38, 573-578, (Mar. 1991).Applicant
- Tanabe, N., et al., “A Ferroelectric Capacitor Over Bit-Line (F-COB) Cell for High Density Nonvolatile Ferroelectric Memories”, 1995 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 123-124, (Jun. 6-8, 1995).Applicant
- Temmler, D., “Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMs”, 1991 Symposium on VLSI Technology, Digest of Technical Papers, Oiso, 13-14, (May 28-30, 1991).Applicant
- Terauchi, M., et al., “A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs”, 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 21-22, (1993).Applicant
- Tsui, P.G., et al., “A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications”, IEEE Transactions on Electron Devices, 42, 564-570, (Mar. 1995).Applicant
- Verdonckt-Vandebroek, S., et al., “High-Gain Lateral Bipolar Action in a MOSFET Structure”, IEEE Transactions on Electron Devices 38, 2487-2496, (Nov. 1991).Applicant
- Vittal, A., et al., “Clock Skew Optimization for Ground Bounce Control”, 1996 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, San Jose, CA, 395-399, (Nov. 10-14, 1996).Applicant
- Wang, N., Digital MOS Integrated Circuits, Prentice Hall, Inc. , Englewood Cliffs, NJ, pp. 328-333, (1989).Applicant
- Wang, P.W., et al., “Excellent Emission Characteristics of Tunneling Oxides Formed Using Ultrathin Silicon Films for Flash Memory Devices”, Japanese Journal of Applied Physics, 35, 3369-3373, (Jun. 1996).Applicant
- Watanabe, H., et al., “A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs”, IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 259-262, (Dec. 13-16, 1992).Applicant
- Watanabe, H., et al., “A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs”, 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 17-18, (1993).Applicant
- Watanabe, H., et al., “An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes”, Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, Japan, 478-480, (1991).Applicant
- Watanabe, H., et al., “Device Application and Structure Observation for Hemishperical-Grained Si”, J. Appl. Phys., 71, 3538-3543, (Apr. 1992).Applicant
- Watanabe, H., et al., “Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Seeding Method”, Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Japan, 422-424, (1992).Applicant
- Watanabe, S., et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE Journal of Solid-State Circuits, 30, 960-971, (Sep. 1995).Applicant
- Wooley, et al., “Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits”, IEEE Journal of Solid State Circuits, vol. SC-28, 420-30, (1993).Applicant
- Yamada, T., et al., “A New Cell Structure with a Spread Source/Drain (SSD) MOSFET and a Cylindrical Capacitor for 64-Mb DRAM's” IEEE Transactions on Electron Devices, 38, 2481-2486, (Nov. 1991).Applicant
- Yamada, T., et al., “Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs”, 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 35-38, (Dec. 3-6, 1989).Applicant
- Yoshikawa, K., “Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 240-241, (Jun. 11-13, 1996).Applicant
- Su, et al., “Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits”, IEEE Journal of Solid State Circuits, SC-28, (1993), pp. 420-430.Applicant