Power feedback power factor correction scheme for multiple lamp operation

[0002] 1. Field of the Invention

[0003] This invention relates to power feedback circuits. More particularly, the invention relates to a double path type power feedback circuit for multiple lamp parallel operation.

[0004] 2. Description of the Background of the Invention

[0005] The low power factor (PF) of conventional electromagnetic compact fluorescent lamps (CFLS) is due to the fact that their voltage and current are not in phase and/or to the higher harmonic content in the current waveform. Electronics in the electronic CFLs, as well as in all other electronic equipment, generate harmonic currents. Harmonic currents are closely related to a reduced PF and can disturb other equipment. Furthermore, a very high harmonic distortion on a utility network may reduce the performance of the transformers and could ultimately damage them.

[0006] An electronic CFL has a typical power factor of between 0.5 and 0.6, but the current cannot be simply compensated for with a capacitor. Instead, a filter has to be introduced, either in the ballast of the lamp itself or somewhere in the electricity network. In countries where the International Electroctechnical Commission (IEC) standards are adopted, the lighting equipment must have a power factor better than 0.96 and a Total Harmonic Distortion (THD) below 33%. However an exception is made in the IEC lighting standards for equipment with a rated power of less than 25W.

[0007] The single stage electronic ballast based on the power feedback principles has been disclosed and described in numerous patents, including U.S. Pat. No. 5,404,082 in the names of A. F. Hernandez and G. W. Bruning, and entitled “High Frequency Inverter with Power-line-controlled Frequency Modulation,” and U.S. Pat. No. 5,410,221 in the names of C. B. Mattas and J. R Bergervoet, and entitled “Lamp Ballast with Frequency Modulated Lamp Frequency”. The type of ballast described in these patents has a lower parts count due to a modulation scheme imbedded in a power conversion process. These patents describe the conversion of a low frequency alternating current (AC) voltage source to a high frequency AC voltage source via a properly designed power feedback scheme. These patents further describe how the harmonic content of an input current can be limited within the International Electrotechnical Commission (IEC) specification while the output current crest factor remains acceptable. Topologically, the single stage power factor correction is achieved based on the power feedback to the node between the full-bridge rectifier output and the DC electrolytic capacitor.

[0008] To date, all of the power feedback schemes are used for a single lamp and a two lamp series configuration, with and without dimming. It is important to point out that in such a class of applications the value of the resonant converter parameters L and C are fixed, even though the load current can be changed during the dimming process. Technically, this implies that the circuit resonant frequency is fixed while the quality factor (Q) is changed with the load. The quality factor Q may be described as the ratio of the resonant frequency to bandwidth.

[0009] In the multiple lamp operation circuit 10, shown in FIG. 1, lamps R_lpare connected in parallel, via ballast capacitors C_1p, respectively, due to the. independent lamp operation (ILO) requirements. Lamps R_lpand ballast capacitors C_lpare then connected in parallel to a transformer T₁, which in turn is connected in parallel to a capacitor C₃. Capacitor C₃is connected to diodes D₃, D₄of the full-bridge rectifier represented by diodes D₁-D₄, and diodes D₁, D₂are connected to a resonant inductor L₁, which in turn is connected to a diode D₅. Diode D₅is further connected to a drain terminal of a positive-negative-positive (PNP) transistor Q₂, and the source terminal of transistor Q₂is connected to a drain of a PNP transistor Q₃. Gates of both transistors Q₁and Q_2gare connected to a high voltage control integrated circuit 12.

[0010] A first terminal of a resistor R, is connected to the source terminal of the transistor Q₃and a second terminal of this resistor is connected to a first terminal of the capacitor C₃, a resistor R₂and diodes D₃and D₄. The high voltage control integrated circuit 12 further connects to the connection of the source terminal of the transistor Q₃and a first terminal of the resistor R_l, individually to a capacitor C₂, and to the interconnection of the inductor L₂and capacitor C₃. The capacitor C₂and the inductor L₂are serially interconnected. The inductor L₂is further connected to the capacitor C₃.

[0011] A capacitor C₁is on a first side connected between a diode D₅and the drain terminal of transistor Q₂, and on the second side between diodes D₃, D₄and the resistor R₁. A drain terminal of the PNP transistor Q₁is connected to the junction of the inductor L₁and the diode D₅and the source terminal of the transistor Q₁is connected to a resistor R₂, which is also connected diodes D₃and D₄, and the capacitor C₁. A power factor controller unit 14 is connected to the inductor L₁, the gate of the transistor Q₁, to the connection of the source terminal of transistor Q₁and resistor R₂, and to the connection of diode D₅and capacitor C₁.

[0012] In this configuration the resonant capacitance is strongly load dependent. This dependence with respect to 0 to 4 lamp combinations is shown in FIG. 2a, where five distinct resonant frequency curves are charted on a voltage/frequency chart. Here, the zero lamp curve 20 represents a scenario in which no lamps are connected, the one lamp curve 22 represents a scenario in which one lamp is connected, the two lamp curve 24 represents a scenario in which two lamps are connected, the three lamp curve 26 represents a scenario in which three lamps are connected, and finally the four lamp curve 28 represents a scenario in which four lamps are connected. The respective frequency peaks of the curves 22, 24, 26 and 28 are 9.554215×10⁴, 7.52929×10⁴, 6.503028×10⁴, and 5.843909×10⁴.

[0013] FIG. 2bshows the same five distinct resonant frequency curves, charted on a primary side resonant tank input phase/frequency chart. In this graph, the zero lamp curve 30 reaches a low phase point of −90, the one lamp curve 32 reaches a low phase point of −23.360583, the two lamp curve 34 reaches a low phase point of −14.71952, and the three lamp curve 36 reaches a low phase point of −5.566823.

[0014] Traditionally, the power feedback power factor correction circuits are limited to a fixed load operation. When the load changes, the input line power factor and current THD performance drop. Even more severe situation is that the DC bus voltage increases dramatically as the load decreases. Such DC bus as voltage over boost usually leads to the damage of power switches if they are not substantially over designed. This problem is encountered during the development of a power feedback circuit for four lamp ballast circuits.

[0015] In view of those variables and the sinusoidal input voltage, it would be advantageous to have a simple single stage electronic ballast circuit based on the power feedback scheme for multiple lamp operation.

[0016] The ballast circuit of the invention is designed for a single or multiple lamp parallel operation, where at each lamp a condition may be controlled such that the amplitude (e.g. the switching frequency of the power transistors) output voltage is almost constant in the steady state. The present invention uses fewer high ripple current rated capacitors than the prior art while providing galvanic isolation. Furthermore, in addition to using smaller input filter sizes, the inventive circuit uses fewer fast reverse recovery diodes necessary for the prior art circuit schemes.

[0017] In order for the inventive power feedback circuit to work with multiple lamp combinations under variable load conditions and without severe DC bus voltage over boost, the resonant tank is designed with an LLC type resonant circuit instead of the previously used LC type. Accordingly, the circuit switching frequency is changed for each lamp number condition. When a lamp number condition is settled, the circuit operates at a selected frequency without line frequency modulation content.

[0018] The circuit of the invention comprises a DC storage capacitor, a DC blocking capacitor, a half-bridge of power transistors which alternately switch on and off and have a 50% duty ratio, and an LLC resonant converter having a resonant inductor, a output transformer, and one or more effective resonant capacitors. The circuit comprises an output transformer, which provides galvanic isolation for a double path type power feedback scheme. The output transformer produces magnetizing inductance utilized for power feedback circuit optimization and is inserted right after the resonant inductor of the half-bridge circuit.

[0019] Furthermore, the circuit of the invention comprises an input line filter having an inductor and a capacitor for bringing an input current close to a sinusoidal waveform with low THD, a current rectifier comprising a plurality of diodes, a plurality of fast reverse recovery diodes, and a plurality of ballasting capacitors that contribute to a resonant capacitance and allows the use of fewer capacitors in the half-bridge circuit.

[0020] The foregoing objects and advantages of the present invention may be more readily understood by one skilled in the art with reference being had to the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings wherein like elements are designated by identical reference numerals throughout the several views, and in which:

[0021] FIG. 1 is a schematic representation of parallel connection of multiple lamps via ballasting capacitors of the prior art, where resonant capacitance is strongly load dependent.

[0022] FIG. 2ais a chart showing voltage/frequency dependence for each of zero to four lamp combinations.

[0023] FIG. 2bis a primary side resonant tank input phase/frequency chart showing the dependence with respect to zero to four lamp combinations.

[0024] FIG. 3 is a schematic representation of the inventive ballast circuit.

[0025] FIG. 4 is a schematic representation of a simplified version of the inventive ballast circuit adapted for equivalent circuit load.

[0026] FIG. 5 is a schematic representation of a prior art circuit adapted for a single lamp application.

[0027] FIG. 6 is a schematic representation of another prior art circuit adapted for a single lamp application.

[0028] FIGS. 7a, band care each a schematic representation of an equivalent inventive circuit where the amplitude of the resonant inductor current and the output voltage are almost constant in the steady state.

[0029] FIGS. 8(a, b), 9(a, b), 10(a, b) and 11(a, b) are input and output voltage/frequency oscilloscope waveform charts for a typical inventive circuit, showing the dependence with respect to one, two, three and four lamps.

[0030] FIGS. 12(a, b) are voltage, current/time oscilloscope waveform charts showing a set of switching waveforms of the inventive circuit shown in FIG. 4 with respect to eight intervals depicted in FIGS. 13a-h.

[0031] FIGS. 13a-hare each a schematic representation of an equivalent inventive circuit where the amplitude of the resonant inductor current and the output voltage vary in accordance with time intervals.

[0032] FIG. 3 shows the ballast circuit 40 of the present invention. The input terminal 44 of the circuit 40 is connected to a resonant inductor L₁, which is connected between diodes D₃and D₁of the full-bridge rectifier, represented by diodes D₁-D₄. A capacitor C₁is connected between the resonant inductor L₁and that inductor's connection to diodes D₃and D₁, and to the input terminal 44. The input terminal 44 further connects between diodes D₄and D₂. Diodes D₁, D₂are connected to a diode D₅, which is connected to a diode D₆. The diode D₆is in turn connected to a capacitor C₁₀that is connected to a resonant sink circuit 42.

[0033] The resonant sink circuit 42 comprises the transformer T₁connected on one side to inductor L₂, which in turn is connected to a capacitor C₃, which is connected to the transistor Q₂. The transistor Q₂connects to the diode D₇, which connects to the second terminal of the transformer T₁. A capacitor C₂is connected between diodes D₅and D₆on one side and between the transformer T₁and the inductor L₂on the other side. A transistor Q₁is connected to the diode D₆and the capacitor C₁₀on one side and to the capacitor C₃and the transistor Q₂on the other side. A capacitor C₈is connected to each terminal of the diode D₇. Each lamp R_lpof the multi lamp unit 46 is connected in series to a respective one of the capacitors C₄-C₇, and the lamp unit is then connected to the transformer T₁. Finally, the terminal of the transformer T₁that is connected to the diode D₇is also connected to diodes D₃₁, D₄.

[0034] The simplified version of the circuit 40 adapted for the single lamp application is shown in FIG. 4 and will be described below. The circuit 40 of the present invention uses fewer high ripple current rated capacitors than the prior art circuits shown in FIGS. 5 and 6, while providing galvanic isolation. One resonant inductor is contributed by the magnetizing inductance of the output transformer. By doing so, there is no need for an additional resonant inductor other than L₂(FIG. 3). With a properly designed LLC type resonant tank, the lamp current crest factor is improved without using the capacitor C_yl(FIG. 5) which must be used in the prior art circuit 17 (FIG. 5). Because the lamp ballasting capacitor C_lmay also act as a part of resonant capacitor, capacitor C_p(FIG. 5) can also be removed. Furthermore, in addition to using smaller input filter sizes, the inventive circuit uses fewer fast reverse recovery diodes 18 (FIG. 6) necessary for the prior art circuit schemes, e.g., circuit 16 (FIG. 6). More importantly, the inventive circuit may be used for 4-lamp operation.

[0035] With reference to FIG. 3, to achieve the above benefits the inverter circuit 40 includes a half-bridge with a LLC resonant converter. The half-bridge includes two power Metal-Oxide-Silicon Field-Effect Transistors (MOSFETS) Q₁and Q₂, the DC storage capacitor C₁₀and the DC blocking capacitor C₃. One resonant inductor is L₂. The resonant capacitors include capacitors C₂, C₈, and the equivalent reffected capacitance of the load capacitors C₄-C₇. The galvanic isolation transformer T₁is disposed between the resonant inductor L₂and the diode D₇to create a proper load matching.

[0036] Additionally, the magnetizing inductance of the isolation transformer contributes additional inductance to the resonant tank. The difference between a single path type power feedback scheme and a double path type power feedback scheme is that in each high frequency switching cycle the full-bridge rectifier, represented by diodes D₁-D₄, conducts once for the single path type and twice for the double path type power feedback scheme. For the same power delivery capability, the double path type power feedback scheme has fewer current stresses in the resonant tank circuit 42.

[0037] The resonant components are designed to set the resonant frequencies under certain operation conditions for each of the load cases. In order to achieve ILO, the voltage gain curves should reach and exceed certain required voltage levels, which are preferred to be kept almost constant at the output terminal 46 via proper control. The invention further employs fast reverse recovery diodes D₅-D₇.

[0038] FIG. 8ashows a square waveform curve 80 of voltage V_gs(FIG. 3) used to drive the lower power switch Q₂(FIG. 3). By alternatively switching power switches Q₁(FIG. 3) and Q₂(FIG. 3) on and off with a 50% duty ratio, the voltage V_s(FIG. 3) has a peak-to-peak amplitude V_dc(FIG. 3). Such voltage excites the resonant tank circuit 42 (FIG. 3) and results in the input current i_Lr(t) 15 (FIG. 3) represented by the i_Lrcurve 82. Due to the resonant tank circuit 42 (FIG. 3), the V_pcurve 84 of voltage V_p(FIG. 3) at point p (FIG. 3) and the V_ncurve 86 of voltage V_n(FIG. 3) at point n (FIG. 3) are close to the sinusoidal waveform. Furthermore at each of the plurality of lamps, e.g., 1, 2, 3 and 4, a condition, e.g. the circuit operating frequency may be controlled such that the amplitude of the resonant inductor current i_Lr(t) and the output voltage V_o(t) (FIG. 3) are almost constant in the steady state.

[0039] With this condition, the high frequency operation of the inventive circuit may be described by components of an equivalent circuit as shown in FIGS. 7a. In that circuit the resonant inductor current is modeled as an ideal current source I_Lrand the output voltage is reflected to the primary side and modeled as an ideal voltage source V_pnFurther, the power feedback circuit 70 can be decomposed into two simpler power feedback circuits 72 and 74 (FIGS. 7b, c). In the first, high frequency circuit 72 (FIG. 7b), as compared to the input line frequency, the voltage source V_pnmodulates the voltage at point m via the charging capacitor C₂. This modulation causes the input current i_in(t) (FIG. 7b) to be sinusoidaly shaped as represented by the curve 88 (FIG. 8b).

[0040] In the second circuit 74 (FIG. 6c), the current source I_lrcharges/discharges the capacitor C₈and shares the input current accordingly. It is important to note that there is a phase difference between the signals V_pn(t) and I_Lr(t). It is this phase difference that allows the rectifier circuit D₁-D₄to conduct current twice, makes the circuit 70 the double path type power feedback circuit. In each high frequency cycle, the double path type power feedback circuit 70 generates two small current pulses in the input line. The envelope of these small pulses follows a pseudo-sinusoidal shape. By using proper input line filter, for example the inductor L₁and the capacitor C₁, the input current will become close to the sinusoidal waveform with a low THD, as represented by the curve 88 (FIG. 8b).

[0041] FIGS. 8-11 show the high frequency oscilloscope waveform curves representing voltages at different points in the circuit 40 (FIG. 3). Specifically, FIGS. 8a,9a,10a,and 11ashow the following waveform curves for the one, two, three, and four lamp configurations respectively:

[0042] 1. The gate drive waveform curve 80 showing V_gs2(t) for the switch Q₂(FIG. 3);

[0043] 2. The resonant inductor current curve 82 for the current i_Lr(t) (FIG. 3);

[0044] 3. The voltage waveform curve 84 for voltage V_p(t) at point p (FIG. 3), and

[0045] 4. The voltage waveform curve 86 for voltage V_n(t) at point n (FIG. 3)

[0046] Similarly, FIGS. 8b,9b, 10b, and 11bshow the waveform curves 88 for the input line current I_in(FIG. 3); 90 for the output lamp current I_lamp(FIG. 3); 94 for the input voltage V_in(FIG. 3); and 92 for the voltage V_dc(FIG. 3), in a low frequency scale for the one, two, three, and four lamp configurations respectively.

[0047] As a further explanation, with reference to FIG. 4, please consider the following functional description of a specific simplified embodiment circuit 50 of the present invention. By varying values of R_land C_l, all four lamp load states may be accounted for. For example, if R_land C_ldenote the equivalent impedance of one lamp and its associated ballast capacitance, then for n-number of lamps the equivalent impedance becomes R_l/n and the equivalent series ballasting capacitance becomes nC_l.

[0048] The input line voltage V_inis a rectified sinusoidal waveform. Because the line frequency, e.g., 60 Hz, is much lower than the circuit switching frequency, e.g., 43 kHz, the input line voltage V_inis assumed to be constant in high frequency cycles. Furthermore, a DC bus voltage ripple may be ignored due to the large capacitance of C₁₀. In the case of a 60 Hz, 120 V, AC input voltage, the DC bus voltage, V_dc, is kept under 220 volts. With the above assumptions, eight equivalent topological stages in each high frequency switching cycle may now be identified.

[0049] Switching waveforms of the circuit 50 having eight equivalent topological stages corresponding to time intervals [t_j, t_(j+1)], where j=0, . . . , 7, are presented in FIG. 12. These equivalent topological stages are discussed below with the aid of FIGS. 13a-h. FIG. 13ashows the equivalent circuit during the first interval [t₀, t₁]. Starting from t₀, both diodes D₅and D₆conduct current I_d5and I_d6, as shown by graphs 122 and 124 (FIG. 12) respectively, however no charging current reaches the capacitor C₁₀(FIG. 4) because diode D₇(FIG. 4) is off. Moreover, the capacitor C₈(FIG. 4) is prevented from being further charged. During that interval, the line voltage source V_indelivers power directly to the load via loop II 100, while the resonant tank circuit 42 operates in a free wheeling mode in loop I 102. The current in the capacitor C₂is the difference between the resonant tank 42 current i_Lin loop I 102 shown as a graph 128 (FIG. 12) and the input line current i_D5in loop II 100 shown as a grapl 122 (FIG. 12).

[0050] While the current i_Lis still in free wheeling state with the current direction indicated by loop I 102, the MOSFET Q₁is turned off 120 (FIG. 12a), as shown in FIG. 13b,during the interval [t₁, t₂], and the current is diverted to the MOSFET Q₂. Please note that the MOSFET Q₂may be turned on with zero voltage switching. With the charging of the DC bulk capacitor C₁₀via loop I 104, the current i_Lin the resonant inductor L₂, shown as the graph 128 (FIG. 12), gradually diminishes to zero. When the zero point is reached, diode D₆is naturally turned off 124 (FIG. 12) and the second interval [t₁, t₂] terminates.

[0051] Following the switch off 124 (FIG. 12) of the diode D₆during the third interval [t₂, t₃] shown in FIG. 13c,the resonant inductor current i_L, shown as the graph 128 (FIG. 12), indicated by loop I 106, reverses direction and increases with the discharging of the capacitor C₈. During this interval, along with further discharging of the capacitor C₈, the voltage V_pcontinuously drops, as shown by a graph 140 (FIG. 12). This drop is followed by continuous charging of the capacitor C₂while the line voltage source V_indelivers power directly to the load.

[0052] After the voltage V_inacross the capacitor C₈drops to zero 128 (FIG. 12), as is shown in FIG. 13d,the diode D₇begins conducting current. During this fourth interval [t₃, t₄], the resonant tank 42 current I_L, shown as the graph 128 (FIG. 12), in loop I 108 is further increased with the resonant frequency being determined by the inductor L₂, the capacitor C₈(FIG. 4), the capacitor C_l, and the resistor R_l, turns ratio n and the magnetizing inductance L_mof the output transformer. In the meantime, the current in the diode D₅starts decreasing from its peak value, that is because voltage V_pfalls below zero, as shown in the graph 140 (FIG. 12) and goes in to a negative swing.

[0053] FIG. 13eshows the resonant tank current I_Lflowing in loop I 110 during the fifth interval [t₄, t₅]. At t₄, the MOSFET Q₂is switched off. During this interval, the MOSFET Q₁is turned on, as shown by graph 120 (FIG. 12a), which may be achieved with zero voltage switching (ZVS). As time reaches t₅, the voltage V_preaches its minimum value, as shown in the graph 140 (FIG. 12b) and the input current I_D5approaches zero, as shown in a graph 122 (FIG. 12a). With the upswing of the voltage V_p, as shown in the graph 140 (FIG. 12b), the voltage V_mincreases correspondingly, as shown in the graph 132 (FIG. 12b), because C₂is not being charged or discharged. At the same, as shown in FIG. 13f,during the sixth time interval [t₅, t₆], the resonant inductor current I_Lis reduced to zero, as shown in the graph 128 (FIG. 12a),and the diode D₇stops conducting.

[0054] When the voltage V_m, as shown in the graph 132 (FIG. 12b), is greater than the voltage V_dc, during the seventh interval [t₆, t₇] as shown in FIG. 13g,the diode D₆begins conducting current, as shown in the graph 124 (FIG. 12a). Momentarily, the diode D₇is switched on to help the voltage V_mcharge the capacitor C₁₀via loop I 112. At the same time the capacitor C₂begins discharging to transfer the energy stored in the capacitor C₂into the resonant inductor current i_L, i.e., the electromagnetic energy. The current i_Lis then gradually built up from zero, as shown in the graph 128 (FIG. 12a).

[0055] While the capacitor C₂is continuously discharging via loop II 114, during eighth interval [t₇, t₈], shown in FIG. 13h, the capacitor C₈begins to charge via the loop I 112 with the DC bus capacitor C₁₀providing the charging current through a load branch. As a result, the voltage V_pincreases, as shown in the graph 140 (FIG. 12b), and the voltage V_mis kept greater than V_dc, as shown in the graph 132 (FIG. 12b).

[0056] While the equivalent circuit 50 (FIG. 4) holds true for each operating point of the sinusoidal input line voltage, the waveforms in FIGS. 12a, 12band operating intervals in FIGS. 13a-hare shown for one typical operating point which may be around 80% of the input line peak voltage. At other operating points, the duration of each interval and even the number of intervals may vary; however, the circuit operating principles will remain the same. In each high frequency switching cycle from t₀to t₈, there are two sections [t₀, t₂] and [t₂, t₅], where the circuit draws two current pulses from the line. The peak value of the pulses is low compared with a single pulse case of single path power feedback schemes. As a result, the resonant tank current is smaller and the associated losses are also smaller.

[0057] While the invention has been particularly shown and described with respect to illustrative and preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention that should be limited only by the scope of the appended claims.