Circuit for recovering digital clock signal and method thereof

[0002] This application claims the benefit of Korean Application No. 99-19020, filed May 26, 1999, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.

[0003] 1. Field of the Invention

[0004] The present invention relates to the field of clock signal recovery, and more particularly, to a circuit for recovering a digital clock signal in a recording and/or reproducing apparatus of an optical disc and a method thereof.

[0005] 2. Description of the Related Art

[0006] In the apparatus for recording data on and/or reproducing data from an optical disc such as a compact disc (CD) or a digital versatile disc (DVD), it is necessary to synchronize a reproduction signal with a system clock signal. A circuit which performs the synchronization process is a phase locked loop (PLL) circuit.

[0007] A PLL circuit locks a phase by generating a system clock signal through a voltage controlled oscillator (VCO). The VCO oscillates with a certain frequency with respect to a received signal, varying the frequency of the system clock signal, and locking the received signal to the varied system clock signal. In general, phase locking starts by determining whether the difference between the oscillation frequency of the VCO and the frequency of the received signal is within a predetermined range, and if not, performing frequency locking.

[0008] The conventional clock recovery circuit 90 used in an optical disc drives a PLL circuit shown in FIG. 1. The PLL circuit includes a binarization circuit 110, a frequency detector 120, a phase error detector 130, a low pass filter (LPF) 140, and a VCO 150. The analog signal read from an optical disc 100 is received by a binarization circuit 110, which compares the received signal with a binarization level, and provides a binarized signal. The binarization circuit 110 can be, for example, a comparator.

[0009] When the frequency difference received by the frequency error detector 120 is within a first predetermined range, the frequency error detector 120 receives the binarized signal and detects the difference between the frequency of the binarized signal and the frequency of the system clock signal generated by the VCO 150. The frequency error detector 120 provides the difference to the LPF 140. The LPF 140 provides a control voltage corresponding to the frequency difference to the VCO 150.

[0010] When the frequency difference is within a second predetermined range, the frequency error detector 120 does not operate. Instead, the phase error detector 130 detects the phase difference between the binarized signal and the system clock signal, and the detected phase difference is provided to the LPF 140. The LPF 140 provides the control voltage corresponding to both the frequency difference and the phase difference to the VCO 150.

[0011] The VCO 150 generates a system clock signal synchronized with the received signal according to the control voltage signal provided by the LPF 140. While not shown in FIG. 1, the VCO 150 provides the system clock signal as a driving clock signal to the frequency error detector 120 and the phase error detector 130.

[0012] Using a conventional PLL circuit, the binarization circuit 110 and the LPF 140 are both analog circuits. Since they are analog, the performance of the PLL circuit deteriorates due to noise passing through the LPF 140. In addition, it is difficult to correct the binarization level corresponding to the received signal using the binarization circuit 110. Also, using a conventional analog filter, it is difficult to properly adjust the LPF 140 to account for a multiple-speed mode. Basically, in order to correctly utilize the binarized signal, the LPF 140 must include a circuit which traces the center value of the received analog signal. Since the LPF 140 is analog, it is not possible to freely change the frequency band to account for this center value, and noise is mixed in the signal no matter how fine the filter is.

[0013] One solution has been having the binarization circuit 110 that incorporates a partial response maximum likelihood (PRML) method. Such a binarization circuit 110 has a structure that outputs a binary signal that is adjusted to the statistical characteristic of the received signal using sampled data. This sampled data is obtained by converting the analog signal into a digital signal, correcting the center value of the analog signal using the sampling value obtained by the analog-to-digital (A/D) conversion, and synchronizing the sampled data with a system clock signal using the center value of the received analog signal. However, these functions are difficult to realize using an analog structure.

[0014] In addition, when an analog LPF 140 is used to provide both the frequency error and the phase error as the control voltage of the VCO 150, it is not possible to freely change the frequency band, which mixes the noise in the signal. Therefore, an analog LPF is difficult to apply to newer optical disc products which have a high multiple speed mode.

[0015] Accordingly, it is an object of the present invention to provide a digital clock recovery circuit having a digital binarization circuit and low pass filter (LPF).

[0016] It is another object of the present invention to provide a method of correcting asymmetry of an analog signal read from an optical disc, binarizing the corrected analog signal, digital signal processing the corrected binarized signal, and recovering a system clock signal.

[0017] Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

[0018] To achieve the first and other objects of the present invention, there is provided a digital clock recovery circuit for recovering a system clock signal locked to a received analog signal, comprising an analog-to-digital (A/D) converter and asymmetry corrector which corrects a received signal into digital data and provides corrected digital data that is corrected by a binarization level which traces the center value of the received analog signal, a frequency error detector which detects a frequency error from the corrected digital data, a phase error detector which detects a phase error from the corrected digital data, a digital low pass filter (LPF) which provides the frequency error and the phase error as a control voltage, and a clock generator which generates a system clock signal whose frequency and phase are varied according to the control voltage and provides the system clock signal as driving clock signals of the respective elements.

[0019] To achieve the second and other objects of the present invention, there is provided a method of recovering a system clock signal locked to a received signal by a phase locked loop (PLL), comprising converting a received analog signal into digital data and providing digital data corrected by a binarization level which traces the center value of the received analog signal, detecting a frequency error from the corrected digital data, detecting a phase error from the corrected digital data, and low pass filtering the phase error and providing the low pass filtered phase error to a control voltage of the PLL together with the frequency error.

[0020] The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

[0021] FIG. 1 is a block diagram of a conventional clock recovery circuit;

[0022] FIG. 2 is a block diagram according to an embodiment of a digital clock recovery circuit according to the present invention;

[0023] FIG. 3 is a detailed block diagram of an asymmetry corrector shown in FIG. 2;

[0024] FIG. 4 explains the phase error detection principle according to the present invention;

[0025] FIG. 5 is a detailed block diagram of the phase error detector shown in FIG. 2; and

[0026] FIG. 6 is a detailed circuit diagram of the digital low pass filter (LPF) shown in FIG. 2.

[0027] Reference will now made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.

[0028] FIG. 2 shows a block diagram of a digital clock recovery circuit 190 according to an embodiment of the present invention. The digital clock recovery circuit 190 has an analog-to-digital (A/D) converter 210 that converts an analog signal read from an optical disc 200 into digital data. The A/D converter 210 provides the digital data to an asymmetry corrector 220 that generates a corrected binarization level according to the statistical characteristic of the received analog signal so as to binarize the received analog signal in an optimal state, corrects the binarization level of the digital data according to the corrected binarization level, and provides the resulting corrected digital data to a frequency error detector 230, and a phase error detector 240.

[0029] When the frequency difference is within a first predetermined range, the frequency error detector 230 obtains the frequency difference between the received corrected digital data provided by the asymmetry corrector 220 and the system clock signal generated by the VCO 270 and provides a frequency error signal. However, when the frequency difference is in a narrower second predetermined range, the frequency error detector does not operate and, instead, the phase error detector 240 provides a phase error signal. The phase error detector 240 obtains the phase difference between the system clock signal and the received analog signal, which for frequency errors within the second predetermined range is already roughly locked to the system clock, and then correctly locks the system clock signal to the received analog signal. Basically, the frequency error signal is provided by the frequency error detector 230 to a digital low pass filter (LPF) 250 when the frequency error is in the first predetermined range, and the phase error detector 240 provides the phase error signal to the digital LPF 250 in order to lock the received analog signal to the system clock signal for those frequency errors that are within the second predetermined range.

[0030] The digital LPF 250 converts the frequency and phase error signals into digital voltage data. The digital-to-analog (D/A) converter 260 converts the digital voltage data into an analog voltage signal and provides the analog voltage signal as a control voltage signal to the VCO 270. The VCO 270 generates a system clock signal of a reference frequency locked to the received control voltage signal. While not shown in FIGS. 2, 3, 5, and 6, the VCO 270 provides the system clock signal to the A/D converter 210, the asymmetry corrector 220, the frequency error detector 230, the phase error detector 240, and the digital LPF 250 as a driving clock signal.

[0031] FIG. 3 shows a detailed circuit diagram of the asymmetry corrector 220. The asymmetry corrector 220 includes a sign determiner 221, an up/down counter 222, a comparator 223, a binarization level generator 224, and an adder 225. The sign determiner 221 determines whether the sign of the digital data provided by the A/D converter 210 shown in FIG. 2 is positive or negative, and provides the sign determination result to the up/down counter 222. The up/down counter 222 increases the count value when the sign determination result of the sign determiner 221 is positive, and decreases the count value when the sign determination result is negative. The count value of the up/down counter 222 increases or decreases according to the asymmetry of the received signal, which provides an indication of the statistical characteristics of the received analog signal. Basically, the more positive or negative signs detected by the up/down counter 222, the more that the binarization level will have to be adjusted positively or negatively to re-zero the digital data.

[0032] To make this adjustment, the comparator 223 compares the count value with a threshold value, determines whether the count value of the up/down counter 222 increases more than or decreases less than the threshold value, and provides an increment value or a decrement value to the binarization level generator 224. The binarization level generator 224 then corrects the binarization level for a sign determination level according to the increment value or the decrement value provided by the comparator 223, and generates a corrected binarization level. The corrected binarization level adjusts the sign determination level positively or negatively so as to trace the center of the received analog signal.

[0033] Finally, the adder 225 adds the corrected binarization level to the digital data provided by the A/D converter 210, and provides the corrected digital data to the frequency detector 230 and the phase error detector 240. Thus, using the asymmetry corrector 220, the asymmetry of the received digital data signal is corrected. While not shown, it is understood that adder 225 can also be a corrector. In addition, it is understood that the comparator 223 can be located inside the binarization level generator 224.

[0034] In order to detect the phase error, the digital clock recovery circuit 190 uses the phase error detector 240 in FIG. 5. In general, the phase error indicates the difference between the phase of the system clock signal, and the phase of the received analog signal. For the phase error detection principle employed by this embodiment, if the received analog signal is correctly locked to the system clock signal, the received corrected digital data is sampled at the point in time when the received corrected digital data is transitioning between signs, which results in the corrected digital data being precisely 0 at this point. However, as shown in FIG. 4, when there is a phase error, the corrected digital data is not sampled at the point in time when the sign of the corrected digital data is changed, which means that the corrected digital data is not 0. Therefore, when there is a phase error, corrected digital data points before and after the point in time when the sign changed are received, the absolute values of these corrected digital data points are obtained, and the corrected digital data point having the smaller absolute value is considered the phase error. Thus, the corrected digital data value having the smaller absolute value at the two points in time when the sign changed becomes the phase error.

[0035] A graphical representation of the phase error principle is shown in FIG. 4. In FIG. 4, the phase error value is actually the value corresponding to b′. It is not possible to directly determine the value of b′. However, the values of a, and a′ are the known values of corrected digital data for different times before and after the sign change, and the total of b+b′ is known to be one clock cycle. As such, by assuming that the corrected digital data is linear at the point in time when the sign is changed, the shape of the triangle a-b-c is similar to that of the triangle a′-b′-c′. As a result, b′ can be expressed as a function of known values a, a′, and b+b′. As a further simplification, however, in the present embodiment, since a′ is smaller than a, the value of a′ can be used to approximate the value of the phase error b′ with acceptable error.

[0036] Based on this assumption, the phase error detector 240 is constructed as shown in FIG. 5. The phase error detector 240 includes first and second absolute value circuits 241 and 243, a delay 242, a comparator 244, an inverter 245, and a selector 246. The first absolute value circuit 241 receives corrected digital data, A(N), at the point in time when a sign change is detected, and provides the absolute value of A(N) as first sampling data. The second absolute value circuit 243 receives the previous corrected digital data, A(N−1), at the point in time just prior to when the sign is changed. The previous corrected digital data is provided from the delay 242 such that it is one clock cycle behind A(N). The delay 242 provides the absolute value of the previous corrected digital data A(N−1) as second sampling data. The delay 242 can be any delay mechanism, but in this embodiment, the delay 242 is a D flip-flop.

[0037] The comparator 244 compares the first sampling data provided by the first absolute value circuit 241 with the second sampling data provided by the second absolute value circuit 243, and provides a selection control signal to the selector 246 so that a signal having the smaller absolute value is selected. In this embodiment, when the first sampling data is smaller, the comparator 244 generates a logic “low” selection control signal. Conversely, when the second sampling data is smaller, the comparator 244 generates a logic “high” selection control signal.

[0038] The inverter 245 receives the first sampling data from the first absolute value circuit 241, and changes the sign to negative. The inverter 245 is used to ensure that the first sampling data is always negative when received by the selector 246. The inverter 245 can be any mechanism that provides a negative sign to a signal, which in this embodiment is a multiplier for multiplying the first sampling data by “−1”.

[0039] When the comparator 244 provides a logic “low” selection control signal to the selector 246, the selector 246 outputs the negative of the first sampling data provided by the inverter 245 as the phase error. When the comparator provides a logic “high” selection control signal to the selector 246, the selector 246 outputs the second sampling data as the phase error.

[0040] The sign of the phase error signal is included in order to indicate whether the phase of corrected digital data leads the system clock signal, or lags the system clock signal. If the phase error value is detected from the sampling data A(N), the negative sign indicates that the phase of the received analog signal leads the phase of the system clock signal. As such, the VCO 270 lengthens the period of system signal clock to account for the phase error having a magnitude of A(N). Conversely, if the phase error value is detected from the sampling data A(N−1), the positive sign indicates that the phase of the received analog signal lags the phase of the system clock signal. As such, the VCO 270 shortens the period of the system clock signal to account for the phase error having a magnitude of A(N−1). In this way, both the magnitude of the phase error is passed to the VCO 270, as well as the lead/lag relationship of this value to the system clock signal.

[0041] FIG. 6 shows the digital LPF 250. The digital LPF 250 includes first and second digital filters 251 and 255, first, second, and third D flip-flops (D F/Fs) 252, 256, and 259, first and second multipliers 253 and 257, and first and second adders 254 and 258. The phase error signal provided by the phase error detector 240 is provided to the first and second digital filters 251 and 255. The frequency error signal provided by the frequency error detector 230 is provided to the first input port of the first adder 254.

[0042] The phase error signal passes through the first and second digital filters 251 and 255. The first digital filter 251 has a first digital filter adder 300 that receives the phase error at one input port, a first digital filter multiplier 320 that multiplies the output of the first digital filter adder 300 by a predetermined time constant, k, and a first digital filter D F/F 310 that delays the output of the first digital filter multiplier 320 by one clock cycle, and then provides this delayed output to the other input port of the first digital filter adder 300. In addition, the second digital filter 255 has a second digital filter adder 350 that receives the phase error at one input port, a second digital filter multiplier 370 that multiplies the output of the second digital filter adder 350 by a predetermined time constant, k2, and a second digital filter D F/F 360 that delays the output of the second digital filter multiplier 370 by one clock cycle, and provides this delayed output to the other input port of the second digital filter adder 350. The digital filters 251 and 255, which are LPFs, filter the phase error signal and smooth the waveform of the phase error signal. In general, the first and second digital filters 251 and 255 each have the form of a first order infinite impulse response (IIR) filter.

[0043] The first digital filter 251 affects the stability of the digital clock recovery circuit 190. This is apparent since, if the phase error signal is provided to the VCO 270 through the D/A converter 260 without being subjected to the low pass filtering by the first digital filter 251, the VCO 270 reacts so sensitively to its inputted signals, that the entire digital clock recovery circuit 190 destabilizes. Therefore, it is possible to control the stability and minimize the phase error of the system by adjusting the time constant value of k of the first digital filter multiplier 320. In general, the value of the time constant k used for the first digital filter 251 is determined using k=1½^M, where M is a positive integer.

[0044] According to the present embodiment, the entire gain of the combined first digital filter 251, the first D F/F 252, and the first multiplier 253 is 1. The output signal of the first digital filter 251 is provided to the first D F/F 252, which delays the output delaying one clock cycle. The delayed output is then multiplied in the first multiplier 253 by the time constant k1. In order to meet the above gain restriction for the present embodiment, the time constant k1 is determined by k1=½^M(where M is the same positive integer used to calculate k). The output of the first multiplier 253 is provided to the second input port of the first adder 254.

[0045] The second digital filter 255 operates as the LPF like the first digital filter 251. However, since the second digital filter 255 outputs to a structure that adds the output of the second digital filter 255 thereof to a previous output, the phase error signal accumulates with the passing of time. The output of the second digital filter 255 is provided to the second D F/F 256, which delays the output for one clock cycle. Then, the delayed output is provided to the second multiplier 257, which multiples the delayed output by the time constant k3 and the multiplication result is received by one input port of the second adder 258.

[0046] The second adder 258 adds the output of the second multiplier 257 to the output of the third D F/F 259, to perform an accumulative operation. The second adder 258 provides this accumulative result to the to a third input port of the first adder 254 and the third D F/F 259. The third D F/F 259 delays the accumulative result for one clock cycle, and then provides this result to the second adder 258. Using this structure, the phase error is accumulated over time.

[0047] In the present embodiment, the time constant K2 of the second digital filter 255 has the form of 1½^Mlike the time constant k of the first digital filter 251. The time constant k3 used by the second multiplier 257 has the form of ½^Mlike the time constant k1 used by the first multiplier 253. However, since the time constant k3 must be used for correcting offset, the time constant k3 is set to be much smaller than k1.

[0048] The offset controller 400 includes the second digital filter 255, the second D F/F 256, the second multiplier 257, the second adder 258, and the third D F/F 259. The offset controller 400 finely traces a direct current (DC) offset voltage change using the received phase error signal, and adjusts the DC offset voltage of the entire digital clock recovery circuit 190.

[0049] While not shown, instead of the circuit shown in FIG. 6, the digital LPF 250 can be realized by any filter which has the filter characteristic of Equation (1). Basically, the digital LPF 250 can be created using a digital filter which has the form of a general infinite impulse response (IIR). $\begin{array}{cc}H\left(z\right)=\frac{Y\left(z\right)}{X\left(z\right)}=\frac{\sum _{i=0}^r{L}_i{z}^{-i}}{1+\sum _{j=1}^m{K}_j{z}^{-j}}& \left(1\right)\end{array}$

[0050] wherein, X(z) represents a z transform of a received signal, which in the present invention is the frequency error signal and the phase error signal, Y(z) represents a z transform of an output signal, which in the present invention is the output the first multiplier 253 and the second adder 258, and H(z) represents a transfer function by z transform. K and L are time constants, and r and m are positive integers.

[0051] The present invention can be widely applied to the clock recovery circuits of digital devices which use the PLL as well as the clock recovery circuit of the optical disc system.

[0052] According to the present invention, it is possible to trace the asymmetry of the received analog signal more sensitively than in the conventional technology, while correcting the asymmetry of the digital data which has undergone the analog-to-digital (A/D) conversion and generating the system clock signal, thereby improving the reliability of the system by stably generating the system clock signal corresponding to various discs.

[0053] The digital clock recovery circuit 190 according to the present invention greatly reduces noise and prevents miscalculations by digitizing the binarization level of the received signal and the phase error detection. Also, in the digital clock recovery circuit 190 according to the present invention, the structure of the filter does not need to be changed due to a change of a multiple-speed mode of the optical disc since a self corrected digital LPF is used.

[0054] Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.