Data recovery apparatus and method for optical disk reproduction systems

[0002] In a contemporary compact disk (CD) system, a photodiode senses light transmitted to a disk by an optical pickup and converts the sensed, reflected optical signal into an analog RF signal. The analog RF signal output of the photodiode is provided to a data slice unit, where asymmetry in the signal is corrected. The asymmetry-corrected signal is provided to a peak detector, where it is converted into a rectangular signal on the basis of a predetermined bias level. An edge detector detects edges in the rectangular signal, and outputs pulses generated at the detected edges to an eight-to-fourteen demodulator (EFDM). The EFDM receives, in units of 14 bits, the pulse train generated at the detected edges, converts each 14-bit signal into an 8-bit signal, and outputs the converted 8-bit signal to an error corrector.

[0003] With ever-increasing optical disk recording density, digital video disk (DVD) systems have recently appeared. A DVD system recovers data from an analog RF signal for the EFDM, in a manner similar to the aforementioned CD system. However, data recorded at such high density must be recovered digitally, to minimize data loss, since analog recovery is unsuitable for adaptive recovery of data for the EFDM, due to variances in the type of optical disk and differences in manufacturing processes. Additionally, with an increase in demand for high-speed transmission and high density recording, when data is recovered according to the analog technique, data quality is adversely affected due to interference between signals.

[0004] To address the aforementioned problems, the present invention is directed to a data recovery apparatus in an optical disk reproduction system, for digital recovery of data for an EFDM from an analog radio-frequency (RF) signal. The present invention further relates to a data recovery method for such a system.

[0005] It is therefore an object of the present invention to provide a data recovery apparatus and method for an optical disk reproduction system, adapted to digitally recover data from an analog RF signal to be provided to an EFDM.

[0006] The apparatus of the present invention is directed to a data recovery system in an optical disk reproduction system including a photodiode and an eight to fourteen demodulator (EFDM) for converting the pattern of a bit train, the data recovery system comprising: an analog-to-digital converter for converting an analog radio frequency (RF) signal input from the photodiode into a digital signal in response to a reference clock signal, and outputting the converted signal as a digital RF signal; a first adder for adding an asymmetry error amount of the digital RF signal to the digital RF signal; an adaptive digital equalizer for digitally controlling the level of the result added by the first adder, in response to a control signal; a digital level detector for calculating the asymmetry error amount using the result added by the first adder, and outputting the control signal according to the output of the adaptive digital equalizer and predetermined coefficients; a viterbi decoder for viterbi-decoding the output of the adaptive digital equalizer into the bit train and outputting the decoded bit train to the EFDM; a digital edge detector for calculating accuracy of sampling by the analog-to-digital converter, using the result added by the first adder, and outputting phase and frequency control signals according to the calculated accuracy; and a reference signal generator for outputting the reference clock signal having a frequency which varies in response to the phase and frequency control signals.

[0007] The method of the present invention is directed to a data recovery method operable in an optical disk reproduction system including a photodiode for outputting an analog RF signal and an eight to fourteen demodulator (EFDM) for converting the pattern of a bit train, the method comprising the steps of: (a) obtaining a digital RF signal by converting the analog RF signal into a digital signal by sampling corresponding to a reference clock signal; (b) determining whether an asymmetry error exists, using the digital RF signal; (c) correcting the asymmetry error with including the asymmetry error amount in the digital RF signal, if the asymmetry error exists, and returning to the step (b); (d) determining whether sampling was performed accurately, if no asymmetry error exists; (e) obtaining frequency and phase errors using the digital RF signal in which the asymmetry error was corrected, if the sampling was not accurately performed; (f) oscillating a frequency according to the frequency and phase errors, obtaining the reference clock signal having an oscillated frequency, and proceeding to the step (d); (g) digitally adjusting a quantized level of the digital RF signal whose asymmetry error was corrected and which was converted by accurate sampling, using the reference clock signal, if the sampling was performed accurately; (h) determining whether a quantized level arbitrarily extracted within a positive or negative 3T section is an estimated quantized level corresponding to the 3T, where T is the period of the reference clock signal, and proceeding to the step (g); and (i) obtaining the bit train by viterbi-decoding the digital RF signal having the adjust quantized level, if the quantized level is not the same as the estimated quantized level.

[0008] The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

[0009] FIG. 1 is a block diagram of a data recovery apparatus for an optical disk reproduction system according to the present invention.

[0010] FIG. 2 is a block diagram of the digital level detector shown in FIG. 1, according to a preferred embodiment of the present invention.

[0011] FIGS. 3A and 3B are exemplary wave forms of an RF signal without asymmetry error and an RF signal having asymmetry error, respectively.

[0012] FIG. 4 is a block diagram of the digital edge detector shown in FIG. 1, according to an alternative embodiment of the present invention.

[0013] FIG. 5 is a block diagram of the reference signal generator shown in FIG. 1, according to the present invention.

[0014] FIG. 6 is a flow diagram illustrating a data recovery method according to the present invention, performed, for example in the apparatus shown in FIG. 1.

[0015] FIG. 7 is a flow diagram illustrating the asymmetry error compensation method of step 152 shown in FIG. 6, according to the present invention.

[0016] FIG. 8 is a flow diagram illustrating a method for controlling the frequency and the phase of the PCLK of step 152 shown in FIG. 6, according to the present invention.

[0017] FIG. 9 is a flow diagram illustrating the details of steps 160 and 162 shown in FIG. 8, according to the present invention.

[0018] Referring to FIG. 1, a data recovery apparatus for an optical disk reproduction system according to the present invention comprises an analog-to-digital converter 10, a first adder 12, a first lowpass filter 14, an adaptive digital equalizer 16, a digital level detector 18, a viterbi decoder 20, a digital edge detector 22 and a reference signal generator 24.

[0019] The analog-to-digital converter 10 receives an analog RF signal generated by a photodiode (not shown) via an input port IN1, converts the analog RF signal into a digital RF signal in response to a reference clock signal PCLK generated by the reference signal generator 24, and outputs the converted digital RF signal to the first adder 12. The first adder 12 combines an error signal E representing the degree of asymmetry error provided by the digital level detector 18 with the digital RF signal provided by the analog-to-digital converter 10, and outputs a sum signal as an asymmetry error-corrected digital RE signal. The sum is provided to the digital level detector 18, the first lowpass filter 14 and the digital edge detector 22.

[0020] The first lowpass filter 14 allows the lowpass component of the output of the first adder 12 to pass, and moves noise from the digital RF signal received from the first adder 12. The filtered lowpass component of the sum signal is provided to the adaptive digital equalizer 16.

[0021] The digital level detector 18 provides two functions: first it compensates for the asymmetry error in the RF signal, and second, it controls the gain of the adaptive digital equalizer 16 to compensate for attenuation of the RF signal according to the type of disk. In order to perform the first function, the digital level detector 18 calculates an asymmetry error amount E as a function of the sum signal output of the first adder 12 and in further response to a selection signal S, and outputs the calculated asymmetry error amount E to the first adder 12. To accomplish the second function, the digital level detector 18 controls the gain of the adaptive digital equalizer 16 on the basis of whether a signal level with a minimum period, determined by the viterbi decoder 20 and prestored in the digital level detector 18, conforms to the level of a signal output from the adaptive digital equalizer 16. That is, the digital level detector generates a control signal C using the output of the adaptive digital equalizer 16. Here the control signal C controls the coefficients of, for example, a highpass filter capable of being implemented as the adaptive digital equalizer 16. The coefficients are input from a controller (not shown) via an input port IN2, and the digital level detector 18 transmits the signal C to the adaptive digital equalizer 16.

[0022] The adaptive digital equalizer 16 digitally regulates the level of the signal output from the first lowpass filter 16 in response to the control signal C output from the digital level detector 18, and outputs the level-regulated signal to the digital level detector 18 and the viterbi decoder 20. The adaptive digital equalizer 16 can be implemented, for example, as a digital highpass filter, having coefficients controlled by control signal C. However, the control signal C itself can become the coefficients, as described later.

[0023] The viterbi decoder 20 decodes the signal output from the adaptive digital equalizer 16 into a bit train composed of digital signals, for example ‘0’ and ‘1’, according to a viterbi decoding technique, and outputs the decoded bit train to the EFDM via an output port OUT. The viterbi decoding method is widely known, and has been disclosed by Roger W. Wood and David A. Petersen, “TRANSACTION DETECTION OF CLASS 4 PARTIAL RESPONSE ON A MAGNETIC RECORDING CHANNEL” Vol. 34, pp. 454-461 (May, 1986).

[0024] The digital edge detector 22 calculates the degree of sampling accuracy by the analog-to-digital converter 10 using the sum signal generated by the first adder 12, and outputs a phase-control signal PC and a frequency-control signal FC to the reference signal generator 24 according to the calculated accuracy. The reference signal generator 24 in turn generates a reference clock signal PCLK having a frequency which varies in response to the phase control signal PC and frequency control signal FC output from the digital edge detector 22. The reference clock signal is provided externally, as well as internally to the analog-to-digital converter 10.

[0025] FIG. 2 is a block diagram of the digital level detector 18 shown in FIG. 1, including: an asymmetry correction unit 40 having a first-plus-Tmin detector 50, a first-minus-Tmin detector 52, a second adder 54, a sign determiner 56, an up/down counter 58, a first comparator 60, a divider 62 and a switch 64; and an adaptive coefficient control unit 42 having a second-plusTmin detector 80, a second-minus-Tmin detector 82, a second comparator 84 and a coefficient converter 86.

[0026] FIG. 3A shows an exemplary waveform of an RF signal 92 which does not have asymmetry error. FIG. 3B shows an exemplary waveform of an RF signal 96 which has asymmetry error.

[0027] Referring to FIGS. 1, 3A and 3B, the analog-to-digital converter 10 quantizes to 2^Nlevels, the level between peaks of the analog RF signal 92 or 96, respectively, shown in FIGS. 3A or 3B, presented at input IN1. Then, the quantized levels 2^Nare output to the adder 12 as the converted digital RF signal. If the analog RF signal 92 does not have asymmetry error, then the reference level 90 corresponds to a mid level among the levels between peaks as shown in FIG. 3A. However, if the analog RF signal 96 has asymmetry error, the reference level 94 may be at the level shown in FIG. 3B.

[0028] The asymmetry correction unit 40 shown in FIG. 2 performs the first of the two functions of the digital level detector 18 stated above. That is, the asymmetry correction unit 40 calculates the degree of asymmetry error E in the output of the first adder 12 (see FIG. 1) input via an input port IN3.

[0029] For this, the first-plus-Tmin detector 50 receives the output of the first adder 12 via the input port IN3, and adds two quantized levels, for example, a and b, or a′ and b′ as shown in FIGS. 3A or 3B, at the center among a first predetermined number of quantized levels existing within a positive 3T section (here, T represents the period of the reference clock signal PCLK). The positive 3T section refers to the section in which the quantized levels greater than the reference level 90 or 94 in the 3T exist. The first-minus-Tmin detector 52 receives the output of the first adder 12 via the input port IN3, and adds the two quantized levels, for example, c and d, or c′ and d′ as shown in FIGS. 3A or 3B, at the center among the second predetermined number of quanitzed levels existing within a negative 3T section. Here, the negative 3T section refers to the section in which the quantized levels smaller than the reference levels 90 or 94 in the 3T exist. For example, each of the first and second predetermined numbers can be 2^N-195 or 97 as shown in FIG. 3A, if the RF signal has no asymmetry error. However, the first of second predetermined number can be less than 2^N-198 or greater than 2^N-199 as shown in FIG. 3B, if the RF signal has the asymmetry error. Finally, the first-plus-Tmin detector 50 outputs the addition result, for example, a+b or a′+b′, and first-minus-Tmin detector 52 outputs the addition result, for example, c+d or c′+d′.

[0030] Returning to FIG. 2, the second adder 54 combines the output of the first-plus-Tmin detector 50 and the output of the first-minus-Tmin detector 52, and transmits the result, for example a+b+c+d or a′+b′+c′+d′, of the addition to the sign determiner 56 and the divider 62.

[0031] The sign determiner 56 determines whether the sign of the output of the second adder 54 is positive or negative, and outputs the result of the determination to the up/down counter 58. The up/down counter 58 performs upward or downward counting according to the result determined by the sign determiner 56. For example, if the sign is positive and not zero, the count is increased and if the sign is negative or zero, the count is decreased. The first comparator 60 compares the value counted by the up/down counter 58 with a first predetermined value, and outputs a voltage level corresponding to +1 or −1 to a switch 64 according to the result of the comparison. The first predetermined value may represent an offset value empirically determined by a user. If the counted value is equal to the first predetermined value, the first comparator 60 outputs a voltage level of +1 or −1 to the switch 64.

[0032] The divider 62 divides the result of the addition of the second adder 54 by 2, and outputs the divided value to the switch 64. The switch 64 selectively outputs the output of the divider 62 or the output of the first comparator 60 as the asymmetry error amount E in response to a selection signal S. Here, the selection signal S is generated so that the output of the first comparator 60 can be output as the asymmetry error amount E in the case when asymmetry can be corrected according to how many times the asymmetry occurs, and the output of the divider 62 can be output as the asymmetry error amount E in the case where asymmetry is to be corrected regardless of how many times the asymmetry occurs.

[0033] The adaptive coefficient control unit 42 performs the second function of the digital level detector 18. That is, the adaptive coefficient control unit 42 generates a control signal C corresponding to the output level of the adaptive digital equalizer 16 (see FIG. 1) input via an input port IN4. For this, the second-plus-Tmin detector 80 receives a signal output from the adaptive digital equalizer 16, via the input port IN4, and selects a quantized level, from among the first predetermined number of quantized levels existing within the positive 3T section. The second-minus-Tmin detector 82 receives a signal output from the adaptive digital equalizer 16, via the input port IN4, and selects a quantized level, corresponding to the quantized level selected by the second-plus-Tmin detector 80, from among the second predetermined number of quantized levels existing within the negative 3T section. For example, when quantized levels 0, 8, 9 and 0 exist in the positive 3T section and quantized levels 0, −13, −15 and 0 exist in the negative 3T section, if the second-plus-Tmin detector 80 selects ‘8’, the second-minus-Tmin detector 82 will select ‘−13’.

[0034] The second comparator 84 compares the absolute value of the quantized level selected by the second-plus-Tmin detector 80 or the second-minus-Tmin detector 82 with an empirically-estimated quantized level, i.e., a signal level with the aforementioned minimum period, and outputs the result of the comparison to the coefficient converter 86. The coefficient converter 86, in an initial state, outputs a control signal C corresponding to highpass filter coefficients input from the microcomputer via the input port IN2. Following the initial state, the coefficient converter 86 adjusts the highpass filter coefficients according to the result of the comparison by the second comparator 84, and outputs the adjusted result as the control signal C. For example, the coefficient converter 86, following the initial state, reduces the absolute values of coefficients input via the input port IN2 and outputs the reduced result as the control signal C if the absolute value of the quantized level selected by the second-minus-Tmin detector 82 is greater than an estimated quantized level.

[0035] FIG. 4 is a block diagram of the digital edge detector 22 shown in FIG. 1, which includes first, second and third delays 100, 102 and 114, first and second bit checkers 104 and 106, a third adder 108, a counter 110, a sign comparator 112 and a charge pump controller 116.

[0036] The first delay 100 shown in FIG. 4 receives an asymmetry error-corrected digital RF signal output from the first adder 12, via an input port IN5, delays the received signal for one period T of the reference clock signal PCLK and outputs the delayed signal. The second delay 102 delays the digital RF signal delayed by the first delay 100 for one period T, and outputs the delayed signal. The first bit checker 104 determines whether all bits of the digital RF signal output by the second delay 102 are ‘0’, and outputs the checked result C1 to the charge pump controller 116. The second bit checker 106 determines whether all bits of the output digital RF signal output from the first delay 100 are ‘0’, and outputs the checked result C2 to the charge pump controller 116. The third adder 108 sums the outputs of the first and second delays 100 and 102, and outputs the sum C3 to the charge pump controller 116.

[0037] The counter 110 counts in response to the most significant bit (MSB) of the digital RF signal output from the first delay 110, and outputs a maximum value C4 among counted values to the charge pump controller 116. That is, the counter 110 counts how long the sign of the output of the first delay 100 does not change, resets the counted value when the sign is changed, and outputs the highest value among the counted values as a maximum value (or maximum time) C4 to the charge pump controller 116.

[0038] The sign comparator 112 compares the MSB of the digital RF signal output from the first adder 12 via the input port IN5 with the MSB of the digital RF signal output from the first delay 100, and outputs the result of comparison to the third delay 114. The third delay 114 delays the result of the comparison by the sign comparator 112 for one period T, and outputs the delayed result C5 to the charge pump controller 116.

[0039] The charge pump controller 116 receives the output C3 of the third adder 108 in response to the outputs C1 and C2 of the first and second bit checkers 102 and 104, outputs the phase control signal PC corresponding to the output C3 of the third adder 108 and the output C5 of the third delay 114, compares the output C4 of the counter 110 with a second predetermined value, and outputs the frequency control signal FC corresponding to the result of the comparison. Here, the second predetermined value is 11T in the case of a CD system, and 14T in the case of a DVD system.

[0040] FIG. 5 is a block diagram of the reference signal generator 24 shown in FIG. 1, which includes a charge pump 130, a second lowpass filter 132, and a voltage controlled oscillator 134.

[0041] The charge pump 130 shown in FIG. 5 outputs to the second lowpass filter 132 a signal corresponding to an amount of charge sunk or sourced in response to the phase and frequency control signals PC and FC output from the charge pump controller 116 of FIG. 4. The second lowpass filter 132 filters a low frequency component of the signal output from the charge pump 130, and outputs the filtered signal as a control voltage signal to the voltage controlled oscillator 134.

[0042] The voltage controlled oscillator 134 outputs a reference clock signal PCLK having a frequency 1/T which varies in response to the control voltage signal output from the second lowpass filter 132.

[0043] Hereinafter, a data recovery method according to the present invention, which is performed in the data recovery apparatus shown in FIG. 1, is described referring to the attached drawings.

[0044] FIG. 6 is a flowchart illustrating the data recovery method according to the present invention, which is performed in the data recovery apparatus shown in FIG. 1. The method includes step 150 of converting an analog RF signal into a digital RF signal, step 152 of generating the reference clock signal in which sampling error has been compensated, compensating for an asymmetry error, and digitally controlling the level of the digital RF signal, and step 154 of obtaining a bit train.

[0045] Referring to FIG. 6, as described above, in step 150 an analog RF signal is converted into a digital RF signal by sampling according to the reference clock signal PCLK having the controlled frequency and phase. Following this, the adder 12 and the digital level detector 18 of FIG. 1 compensate for the asymmetry error, the digital edge detector 22 and the reference signal generator 24 control the frequency and the phase of the reference clock signal PCLK, and the adaptive digital equalizer 16 and the digital level detector 18 digitally equalize the digital RF signal, in step 152.

[0046] FIG. 7 is a flowchart illustrating the asymmetry error compensation method of step 152 shown in FIG. 6, according to the present invention. The method includes steps 156 and 158 of compensating for the asymmetry error according to whether the asymmetry error exists. Referring to FIG. 7, the digital level detector 18 of FIG. 1 determines whether an asymmetry error exists, using the digital RF signal as described above, in step 156. Here, the asymmetry corrector 40 shown in FIG. 2 can be used for this determination. If the asymmetry error exists, the asymmetry error is included in the digital RF signal, i.e., the first adder 12 combines the asymmetry error and the digital RF signal, the procedure returns to step 156, according to step 158.

[0047] For digitally equalizing the digital RF signal, the adaptive digital equalizer 16 (see FIG. 1) digitally regulates the level of the signal output from the first lowpass filter 14 under the control of the digital level detector 18, as described above.

[0048] FIG. 8 is a flowchart illustrating a method for controlling the frequency and phase of the PCLK in step 152 shown in FIG. 6, according to the present invention. The method includes steps 160 through 164 of controlling the frequency and the phase of the PCLK according to the sampling accuracy.

[0049] Referring to FIG. 8, it is determined whether sampling was performed accurately when the analog RF signal was converted into the digital RF signal, in step 160. If the sampling was not performed accurately, frequency and phase errors are obtained, in step 162. The steps 160 and 162 can be performed in the digital edge detector 22 shown in FIG. 4.

[0050] Following step 162, the reference clock signal PCLK, having a frequency and a phase which are controlled according to the frequency and phase errors is obtained. For this, the reference signal generator 24 obtains a new reference clock signal PCLK in response to a frequency error signal corresponding to the frequency error and a phase error signal corresponding to the phase error, as described above, in step 164. Therefore, the ADC 10 shown in FIG. 1 can exactly convert the analog RF signal into the digital RF signal according to the new reference clock signal PCLK.

[0051] FIG. 9 is a flowchart illustrating steps 160 and 162 shown in FIG. 8, which is comprised of steps 180, 182, 184, 188, 190, 192 and 194 of determining whether sampling was accurately performed, and steps 186, 196 and 198 of obtaining frequency and phase errors.

[0052] The method shown in FIG. 9 is performed in the digital edge detector 22 shown in FIG. 4. The first delay 100 delays the digital RF signal by T, in step 180. The counter 110 calculates the maximum time for which the MSB of the delayed digital RF signal remains at the same level during step 182. That is, the counter 110 calculates the maximum time for which the sign of the delayed digital RF signal does not change. Next, the charge pump controller 116 determines whether the maximum time is the same as a predetermined value, for example 11T or 14T, in step 184. If the maximum time is equal to the predetermined value, the charge pump controller 116 generates no frequency error signal FC, and the procedure proceeds to step 188. However, if the maximum time is not the same as the predetermined value, the charge pump controller 116 generates a frequency error signal FC to increase or decrease the frequency varied by the voltage controlled oscillator 134, in step 186.

[0053] The digital RF signal delayed by the first delay 100 for T is again delayed for T by the second delay 102 in step 188. Following this, the second bit checker 106 determines whether all bits of the digital RF signal delayed by the first delay 100 are ‘0’, and if so, the procedure ends, in step 190. However, if every bit is not ‘0’, the first bit checker 104 determines whether all bits of the digital RF signal delayed by the second delay 102 are ‘0’, and if so, the procedure ends, in step 192. On the other hand, if the bits of the digital RF signal delayed by the second delay 102 are not all ‘0’, the sign comparator 112 determines whether the sign of the once-delayed digital RF signal is the same as that of the non-delayed digital RF signal. Here, if the sign of the once-delayed digital RF signal is the same as that of the non-delayed digital RF signal, the procedure ends, in step 194. That is, if the signs are the same, it is considered that there is no phase difference, so that the phase error signal PC is not generated.

[0054] On the other hand, if it is determined in step 194 that the signs are not the same, i.e. there is a phase difference, the third adder 108 adds the signals delayed by the first and second delays 100 and 102, in step 196. Then, the charge pump controller 116 generates the phase error PC using the sum C3, in step 198. That is, if the once-delayed digital RF signal and/or the twice-delayed digital RF signal are not composed of ‘0’ bits, the charge pump controller 116, compares the sign of the input C3 with the signs of C6 and C7, and generates the phase error signal PC to allow the phase of the reference clock signal PCLK to lag or lead according to the result of the comparison. When both the once-delayed and twice-delayed digital RF signals are composed of ‘0’ bits, which is the initial state, the phase error signal PC is not generated.

[0055] Following step 152, the viterbi decoder 20 decodes the digital RF signal, output from the adaptive digital equalizer 16, using a viterbi decoding technique to obtain a bit train, in step 154. Then, the bit train obtained by the step 154 is converted into a bit train composed of 8 bits by an EFDM (not shown).

[0056] The above-described data recovery apparatus according to the present invention is applicable to any of a number of optical disk reproduction systems, such as a CD system or a DVD system.

[0057] As described above, in the data recovery apparatus and method according to the present invention for an optical disk reproduction system, data for EFDM is digitally recovered from the analog RF signal, so that data recovery capability is improved. Since the sampling frequency of the analog-to-digital converter is varied by the reference clock signal PCLK even though the speed multiple of the disk varies, the present invention can be generally used in a data reproduction channel with the same modulation method. Also, when the data recovery apparatus is produced as a chip, the chip is smaller and power consumption is lower than that of an analog system.

[0058] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.