Slope generator

[0002] The present invention relates to slope generators for generating a slope between a first and a second voltage level.

[0003] Slope generators (also referenced as waveform, ramp or sawtooth wave generators) are used in several applications for generating signals with a controllable slope. Typically, a current integrating capacitor is charged/discharged to produce a ramp signal.

[0004] FIG. 1 depicts a slope generator 10 as known in the art, e.g. a 1DB6 (“Snake”) Slope Generator IC as used in the Hewlett-Packard HP8112A. The slope generator 10 comprises a fixed connected current source 20 providing a charge current I_up to load a ramp-capacitor C_ramp from a voltage low level V_l to a voltage high level V_h as output voltage V_out at a node 25. A current source 30 switchable by a current switch 40 (consisting of transistors Q1 and Q2) provides a current I_dn (whereby I_dn>I_up) to discharge the ramp-capacitor C_ramp from voltages V_h to V_l with a discharge current of I_dn−I_up. An input pulse V_in with fast edges at the current switch 40 controls the coupling of the current source 30 to the ramp-capacitor C_ramp. A low-level of the input pulse V_in switches on I_dn and a high level of the input pulse V_in switches off I_dn.

[0005] With the current I_dn being turned off, the ramp-capacitor C_ramp will be charged with a constant current I_up (thus generating a rising slope with the slew rate of dV/dt=I_up/C_ramp) until a clamping diode D2 (coupled to a clamping voltage V_cl_h) is taking over this current, thus stopping the charging. With I_dn being turned on, the ramp-capacitor C_ramp will be discharged with a constant current I_dn−I_up (thus generating a falling slope with the slew rate of dV/dt=−(I_dn−I_up)/C_ramp) until a clamping diode D1 (coupled to a clamping voltage V_cl_l) is taking over this current, thus stopping the discharging.

[0006] The voltage levels V_l and V_h of the output voltage V_out at the ramp node 25 of the ramp-capacitor C_ramp are derived from the clamping voltages V_cl_l and V_cl_h:

[0007] V_—l=V_—cl_—l(I_dn−I_up, T)−Vf_—D1(I_dn−I_up, T)  (1a)

[0008] V_—h=V_—cl_—h(I_up, T)+Vf_—D2(I_up, T)  (1b).

[0009] The clamping voltage V_cl_l and the forward voltage Vf_D1 at diode D1 are both dependent on the differences between the currents I_dn and I_up and on the temperature T. Accordingly, the clamping voltage V_cl_h and the forward voltage Vf_D2 at diode D2 are both dependent on the current I_up and the temperature T.

[0010] The time to charge the capacitor C_ramp and thus the rising time T_rise of the slope generator 10 is: $\begin{array}{cc}{T}_{—}\mathrm{rise}=C_{—}\mathrm{ramp}\times \frac{\left|V_{—}h-V_{—}1\right|}{I_{—}\mathrm{up}}.& \left(2\right)\end{array}$

[0011] Accordingly and with I_dn>I_up, the time to discharge the capacitor C_ramp and thus the falling time T_fall of the slope generator 10 is: $\begin{array}{cc}{T}_{—}\mathrm{fall}=C_{—}\mathrm{ramp}\times \frac{\left|V_{—}h-V_{—}1\right|}{\left|I_{—}\mathrm{dn}-I_{—}\mathrm{up}\right|}.& \left(3\right)\end{array}$

[0012] As apparent from equations (2) and (3), the timing of the slope generator 10 directly depends on the voltage levels V_h and V_l. Therefore, significant effort has to be spent to compensate the thermal and current dependency of the clamping diodes D1 and D2.

[0013] Another, even more serious disadvantage of the slope generator 10 of FIG. 1 is the capacitive loading by two clamping diodes (D1 and D2), thus limiting the minimum feasible ramp-capacitance C_ramp_eff, and accordingly, the minimum feasible transition times T_rise and T_fall. This is since the fastest slope (or transition time) is determined by the highest possible charging current and the lowest possible capacitance at the node 25, whereby the capacitance at the node 25 is determined by the capacitor C_ramp and parasitic capacitances. On the other hand, the parasitic capacitance of the clamping diodes D1 and D2 exhibits a strong dependency on the applied voltages, thus resulting in a negative impact on a desired linear slope. Since V_cl_l and V_cl_h represent low impedance nodes, the influence of parasitic capacitance of the clamping diodes D1 and D2 will add fully to the ramp capacitor C_ramp.

[0014] It is an object of the invention to provide an improved slope generator with a more accurate level clamping.

[0015] The object is solved by independent claim 1. Preferred embodiments are shown by the dependent claims.

[0016] A slope generator according to invention generates, in response to an input signal, a slope between a first and a second voltage level of an output voltage at an output node. The slope generator comprises a capacitor coupled to the output node, a first current source for providing a first current to the output node, and a second current source for providing a second current to the output node controlled by a first current switch. A control electrode of a first current path of the first current switch is coupled to and controlled by an input signal and a second current path is coupled to the output node. The first current switch provides the first and the second voltage levels, or corresponding voltage levels derived therefrom, to the output node.

[0017] According to the invention, the first current switch represents a combined current switching/voltage level providing (clamping) circuit, thus diminishing the influence of parasitic capacitance loads at the ramp-node.

[0018] In a preferred embodiment, the first current switch comprises two emitter-coupled transistors and a control electrode of the second current path is coupled to the output node. In contrast to the prior art as depicted in FIG. 1, wherein two diodes are connected to a low impedance node, this inventive embodiment provides just one diode connected to a low impedance node, thus allowing faster transition times for given ramp capacitor, charge currents and ramp voltage swings. Thus, the ‘clamping principle’ is to go—from the voltage levels V_l and V_h—one diode drop down and then one diode drop up again, thus directly transferring V_h and V_l to the ramp node. With matching diodes, all temperature and current dependencies are cancelled out with a very simple circuitry.

[0019] The invention allows smaller achievable output transition times, a much simpler design and the good amplitude stability.

[0020] Other objects and many of the attendant advantages of the present invention will be readily appreciated and become better understood by reference to the following detailed description when considering in connection with the accompanied drawings. Features that are or can be built up substantially equally or similarly are referred to with the same reference sign.

[0021] FIG. 1 depicts a slope generator 10 as known in the art,

[0022] FIG. 2A depicts a first embodiment of a slope generator 100 according to the invention,

[0023] FIG. 2B depicts a diagram of currents and voltages for an example of the slope generator 100 of FIG. 2A in operation, and

[0024] FIG. 3 depicts a second embodiment of a slope generator 200 according to the invention as a differential circuit.

[0025] FIG. 2A depicts a first embodiment of a slope generator 100 according to the invention. In accordance with the slope generator 10 of FIG. 1, the slope generator 100 comprises the ramp-capacitor C_ramp and the (positive) current source 20 providing the current I_up, both coupled to the node 25. The slope generator 100 further comprises the (negative) current source 30 providing the current I_dn to the current switch 40 consisting of the transistors Q1 and Q2. The current switch 40 is coupled to and controlled by the input signal V_in.

[0026] In contrast to the slope generator 10 of FIG. 1, a voltage level generation unit 105 provides the two voltage levels V_h and V_l to the current switch 40. The voltage level generation unit 105 preferably comprises a current switch 120 (consisting of transistors Q3 and Q4) controlling the coupling of a current source 110 providing a current I_q. The current switch 120 generates the two voltage levels V_h and V_l at the collector (node Q4_C) of transistor Q4, following the input signal V_in. The collector of transistor Q4 is coupled to the base of transistor Q1 of the current switch 40. Collector and base of transistor Q2 are commonly coupled to node 25 thus rendering the transistor Q2 to be diode-connected.

[0027] Whereas the current switch 40 in FIG. 1 only has the function of switching on or off the current I_dn to node 25, the current switch 40 in FIG. 2A further provides the two voltage levels V_h and V_l to the node 25.

[0028] In the example of FIG. 2A, to current source 30 is selected to provide a current I_dn=2×I_up for reasons which become clearer later.

[0029] In operation, the slope generator 100 repetitively goes through four different states:

[0030] State #1: Low level state

[0031] State #2: Transition from low level to high level

[0032] State #3: High level state

[0033] State #4: Transition back to low level

[0034] FIG. 2B depicts a diagram of currents and voltages for an example of the slope generator 100 in operation.

[0035] State #1: Assuming V_in is at a low level. Transistor Q3 will be turned off and transistor Q4 will be turned on. The collector of Q4 is coupled via an impedance Rc to a potential VCC, preferably ground level, thus generating the first voltage level:

[0036] V_—l=Vcc−I_—q×Rc  (4a)

[0037] at the collector of Q4 at node Q4_C. The voltage V_out at the node 25 is at an equilibrium point where no current is flowing into or out of the ramp capacitor C_ramp. The current I_up provided from the current source 20 is forced to flow through the diode-connected transistor Q2. Since the current source 30, coupled to the common emitters of transistors Q1 and Q2, pulls the current I_dn=2×I_up, exactly the same current I_up will flow through the transistor Q2 and the base emitter diode of transistor Q1.

[0038] Having identical currents flowing through the base-emitter diodes of the transistors Q1 and Q2, the output voltage V_out at the ramp-node 25 will be determined by the voltage level V_l and the base-emitter voltages Vbe_Q1 of transistor Q1 and Vbe_Q2 of transistor Q2:

[0039] V_out=V_—l−Vbe_—Q1(I_up)+Vbe_—Q2(I_up)  (4b).

[0040] Assuming a good matching of the transistors Q1 and Q2, the base-emitter voltages Vbe_Q1 and Vbe_Q2 will be substantially identical, thus keeping the output voltage V_out exactly at the voltage level V_l:

[0041] V_out=V_—l  (4c).

[0042] State #2: Assuming a fast (relative to the intended slope at node 25) positive transition (from low level to high level) of the input signal V_in. Transistor Q3 will be turned on and transistor Q4 will be turned off, thus generating the second voltage level:

[0043] V_—h=Vcc  (5a)

[0044] at the collector of transistor Q4. Transistor Q1 will be turned on and transistor Q2 will be turned off (as output voltage V_out at node 25 still is at V_l due to the capacitor C_ramp). Transistor Q1 will provide the full current I_dn, and no current will flow through transistor Q2. This forces the current source 20 to provide the current I_up to the capacitor C_ramp, thus charging the capacitor C_ramp with a current I_ramp=I_up and at a rate of:

[0045] dV/dt=I_up/C_ramp  (5b)

[0046] State #3: As the output voltage V_out is reaching the second voltage level V_h, transistor Q2 will start to turn on, taking over more and more of the current I_up from the current source 20 until a new equilibrium is reached at the ramp node 25. Now again, no current is flowing into or out of the ramp capacitor C_ramp. The current I_up from the current source 20 has to flow through transistor Q2 and, since the current source 30 pulls the current I_dn=2×I_up, the same current I_up will flow through transistor Q1. This, again, keeps the output voltage V_out at the ramp node 25 exactly at the second voltage level V_h.

[0047] State #4: Assuming a fast (relative to the intended slope at node 25) negative transition (from high level to low level) of the input signal V_in. Transistor Q3 will be turned off and transistor Q4 will be turned on, thus generating again the first voltage level V_l=VCC−I_q×Rc at the collector of transistor Q4. Transistor Q1 will be turned off and transistor Q2 will be turned on (as the output voltage V_out at node 25 still is at second voltage level V_h due to the capacitor C_ramp). The full current I_dn will be forced through transistor Q2. As I_dn is twice I_up, the effective discharging current through the capacitor C_ramp is −I_up.

[0048] Reentering State #1: As the output voltage V_out at node 25 is reaching the first voltage level V_l, transistor Q1 will start to turn on, taking over a part of the current I_dn pulled by the current source 30, until a new equilibrium is reached at the ramp node 25. Now again, no current is flowing into or out of the ramp capacitor C_ramp. The current I_up is forced to flow through transistor Q2, and the same current I_up flows through transistor Q1 (see above), thus keeping the output voltage V_out exactly at the first voltage level V_l.

[0049] It is to be understood that the voltage level generation unit 105 comprising the current switch 120 in combination with the current source 110 (providing the current I_q) only represent a preferred embodiment of the invention for providing the two voltage levels V_h and V_l to the current switch 40. The current switch 120, however, decouples the input and transforms the input signal(s) V_in to the voltage levels V_h and V_l. It is clear that though the input signal is depicted in FIG. 2A as differential input, any kind of input signal (differential or non-differential) can be applied. As an alternative to the current switch 120, a pulse voltage source allowing to switch between the voltage levels V_h and V_l can also be applied.

[0050] Further more, it is clear that the provided current I_dn is only preferably selected to be twice the current I_up. For the embodiments of FIGS. 2A and 3, a certain offset of the voltage levels has to be considered in case that I_dn>I_up, but I_dn 2×I_up, which can be compensated either in the generation of the voltage levels or in the stage following the voltage output. In case that I_dn=2×I_up, the offset voltage at the ramp node 25 is constantly at (V_h+V_l)/2.

[0051] FIG. 3 depicts a second embodiment of a slope generator 200 according to the invention as a fully differential circuit. The differential generation of slopes makes the design less sensitive to common mode effects. The embodiment of FIG. 3 substantially corresponds to the embodiment of FIG. 2A. Components corresponding due to the differential characteristics are denoted with A and B.

[0052] The difference between the embodiments of FIGS. 2A and 3 is that in FIG. 3 both the normal and the complementary input signals V_in are fed through separate slope-generators 100A and 100B built up substantially in accordance with the slope generator 100 of FIG. 2. The slope-generators 100A and 100B employ substantially identical capacitors C_rampA and C_rampB and substantially identical charge-/discharge currents. The voltage level generation unit 105 provides the differential voltage levels to the transistors Q1A and Q1B. With a positive step at V_in a positive slope is generated at node 25A via the transistors Q1A and Q2A. At the same time, a negative slope with the substantially identical transition time is generated at node 25B via transistors Q1B and Q2B, thus generating a differential output signal V_out.