Integrator Circuit With Limiter

Integrator circuits of the type described herein are for instance used for forming pulses. They enable rising and dropping portions of predetermined slopes to be generated, with a zone of constant voltage defined by the limitation arranged therebetween.

There exist essentially two different ways of obtaining such limitation. In the case of the active limitation, a control circuit is activated to maintain the voltage at the capacitor constant, when the limit voltage has been reached. For this purpose, the amplification of the control circuit must be kept low to allow rapid transient of the control circuit. However, this means that the limiting voltage does not remain constant and that the difference between the start and the final value of the limitation is relatively high.

In the case of the passive limitation, a clamping circuit with diodes is used which receives the constant current previously supplied to the capacitor after the clamping voltage has been reached. However, the particular current/voltage characteristic of the diodes results in a voltage discontinuity during the transition from the constant clamping voltage to the dropping slope (discharge of the capacitor), and as a result thereof the pulse shape becomes inaccurate. Although this voltage discontinuity can be avoided by passing the pulse through an additional limiter circuit which clips off the inaccurate portion of the pulse, such procedure offers the disadvantage that the contant-voltage time varies with any change of the slope of the rising and/or dropping portion. However, in many applications, it is desired that this contant-voltage section should remain uniformly long even if the slope should be varied.

It is an object of the present invention to provide an integrator circuit using a limiter device comprising diodes and supplying accurate transitions between the sloping portions and the constant-voltage portion, while eliminating any variations of the length of the constant-voltage portion when the slope steepness is varied.

According to the invention an integrator circuit is provided, comprising a capacitor, at least one connectable and disconnectable power source for charging and discharging the capacitor, and a limiter device comprising diodes for limiting the capacitor voltage to a predetermined value. The limiter device can be separated from the remaining integration circuit, thus avoiding the effect resulting from the current/voltage characteristic of the diodes, particularly undesirable voltage discontinuity.

FIG. 1 shows a basic circuit diagram of an integrator in accordance with the invention;

FIG. 2 shows the output voltage/time curve of the circuit shown in FIG. 1; and

FIG. 3 shows a detailed circuit diagram of a preferred embodiment of the invention.

FIG. 1 shows an integration capacitor C.sub.I that can be charged and/or discharged via current sources I.sub.R and I.sub.V. The capacitor voltage U.sub.c can be kept at an output terminal 11. Clamping circuits 13 and 13' prevent the capacitor voltage U.sub.c from rising above a predetermined value .+-.U.sub.cmax. Both the two current sources I.sub.R and I.sub.V and the clamping circuits 13 and 13' can be connected to the integration capacitor C.sub.I via switches S.sub.1, S.sub.2 and S.sub.3 or S.sub.3 '. The switches S.sub.1, S.sub.2, S.sub.3 and S.sub.3 ' can be actuated by means of a control circuit 15.

Now, the switching sequence will be described in connection with FIG. 2, which shows the curve of the output voltage U.sub.c related to time. At the moment t.sub.o the switches S.sub.1 and S.sub.3 are closed, whereas the switches S.sub.2 and S.sub.3 ' remain open. This is the condition shown in FIG. 1. Then the capacitor C.sub.I is charged via the current source I.sub.R (FIG. 1) and as a result a sloping rise of the voltage U.sub.c is achieved until the clamping voltage U.sub.cmax is reached at the moment t.sub.1. Thereafter, this voltage is maintained until the moment t.sub.2.

At the moment t.sub.2, the switches S.sub.1 and S.sub.3 are opened, whereas the switch S.sub.2 is closed, when the capacitor C is discharged via the current source I.sub.V, and as a result a sloping drop of the voltage U is achieved until the value zero is reached at the moment t.sub.3. About this moment, the switch S.sub.3 ' is closed. The capacitor C.sub.I continues to be negatively charged and the voltage U.sub.c continues to drop until the negative clamping voltage U.sub.cmax is reached at the moment t.sub.4. This voltage is then maintained until the moment t.sub.5.

At the moment t.sub.5, the switches S.sub.2 and S.sub.3 ' are opened, whereas the switch S.sub.1 is closed. As a result, the capacitor C.sub.I is again positively charged via I.sub.R. At about the moment t.sub.6, the switch S.sub.3 is closed again, and the operating cycle starts with the moment t.sub.o.

FIG. 3 shows the circuit of a preferred embodiment of the present invention. Again, the integration capacitor is marked with the reference C.sub.I. Its voltage U.sub.c can be tapped at an output terminal 23. Charging and discharging of the integration capacitor C.sub.I is effected with currents I.sub.R and/or I.sub.V supplied by current sources 29 and/or 29'.

An input terminal 21 is supplied with a symmetrical switching signal (square signal) from a control circuit not shown in the drawings. This signal reaches one base each of two transistor pairs T.sub.1 and/or T'.sub.1 acting as differential amplifiers. The other base of each such transistor pairs is connected to earth. The transistor pairs T.sub.1 and T.sub.1 ' generate on lines 25 and 25' signals of opposite phase, and on lines 27 and 27' signals in equal phase in relation to the input signal at the terminal 21. The complementary signals on the lines 25 and 27 are supplied also to a transistor pair T.sub.2. A low signal level on line 25 (and simultaneously a high signal level on line 27) causes the current I.sub.R of a current source 29 to be supplied to an integration capacitor C.sub.I so that the latter is charged. The voltage U.sub.c at the integration capacitor C.sub.I can be tapped at a terminal 23.

If one assumes that during the charging of C.sub.I the voltage U.sub.c is lower than the voltage U.sub.1 of a current source 31, the diode D.sub.2 is non-conductive, and a current source 33 with 1.3 I.sub.R draws current from the current source 31, via a diode D.sub.1. As soon as the voltage U.sub.c becomes equal to the voltage U.sub.1 the diode D.sub.2 becomes conductive, and the current I.sub.R from the current source 29 is supplied to the current source 33 (1.3 I.sub.R) via diode D.sub.2. Now, the charging of the integration capacitor C.sub.I is discontinued, and its voltage remains constant, which means that a clamped condition is obtained.

Now, when the signal level on lines 25 and 27 changes, the transistor pair T.sub.2 switches over, the current I.sub.R which previously passed the diode D.sub.2, is now supplied to the connection point 35 between the diodes D.sub.1 and D.sub.2. At the same time, this connection point is simultaneously supplied via the transistor pair T.sub.3 with the current 0.3 I.sub.R from a current source 37, which was previously discharged to earth by the transistor pair T.sub.3. As connection point 35 is now supplied with a current equal to that discharged by it (1.3 I.sub.R in both cases), no current can flow through the diode D.sub.2, and thus the clamping circuit is separated from the integration capacitor C.sub.I.

At the same time, the transistor pair T'.sub.2 connects a current source 29' (I.sub.V) with the integration capacitor C.sub.I so that the latter is discharged. The function of the lower half of the circuit shown in FIG. 3 is basically identical to that of the upper circuit portion with the exception that the components (T.sub.1 ', T.sub.2 ', T.sub.3 ', D.sub.1 ', D.sub.2 ' in relation to T.sub.1, T.sub.2, T.sub.3, D.sub.1, D.sub.2), the currents (I.sub.V in relation to I.sub.R) and the voltages (U.sub.1 ' in relation to U.sub.1) are oppositely directed or orientated. The signals on lines 25' and 27' are equal in phase to those on lines 25 and 27. In the embodiment shown in the drawing, the output voltage U.sub.c at the terminal 23 shows a trapezoidale curve (as shown in FIG. 2) with constant portions of +2 volt and -2 volt, between which linear sloping portions are encountered the steepness of which can be varied by corresponding changes to the currents I.sub.R and/or I.sub.V.