Semiconductor device

[0002] The present invention relates to a semiconductor device for generating voltages that are used as internal power supply voltages for semiconductor devices, such as, DRAMS, by using an external power supply voltage fed by a peripheral circuitry.

[0003] Semiconductor devices, such as, DRAMS, operating at several levels of power supply voltages in the internal circuitry are provided with an up- or a down-converter for up-converting or down-converting an external power supply voltage fed by a peripheral circuitry.

[0004] Shown in FIG. 12 is a circuit diagram of a typical up-converter.

[0005] The up-converter is provided with an operational amplifier 1, a resistor-voltage divider 5 connected to the positive input terminal of the operational amplifier 1, and an inverter IV1 connected to the output terminal of the operational amplifier 1, a ring oscillator 2 driven by the output of the inverter IV1, a charge pump 3 driven by the output of the ring oscillator 2, and a capacitor Cpp connected to the output terminal of the charge pump 3.

[0006] The resistor-voltage divider 5 divides an up-converted voltage Vpp that has been up-converted by the charge pump 3.

[0007] The operational amplifier 1 compares a divided voltage TAP of the resistor-voltage divider 5 with a reference voltage VBGR, to output a positive signal if the former voltage level is higher than the latter, whereas a negative signal if the latter is higher than the former.

[0008] This results in an output OSCE of the inverter IV1 being brought into a low level state if TAP>VBGR, whereas a high level if TAP<VBGR.

[0009] The reference voltage VBGR is set at, for example, 1. 25V, that is generated by a band-gap reference circuit (not shown) exhibiting no thermal behavior.

[0010] Illustrated in FIG. 13 are voltage waveforms of the up-converted voltage Vpp, the divided voltage TAP, and the output OSCE of the inverter IV1.

[0011] The operation of the up-converter shown in FIG. 12 will be explained with reference to the voltage waveforms illustrated in FIG. 13.

[0012] Transition of the up-converted voltage Vpp from its stable condition (a desired voltage level) to a lower level with the divided voltage TAP lower than the reference voltage VBGR triggers the transition of the inverter output voltage OSCE from a low to a high level.

[0013] This voltage transition initiates the ring oscillator 2 for oscillation and also the charge pump 3 for up-conversion.

[0014] The up-converted voltage Vpp at a high level gradually raises the divided voltage TAP higher than the reference voltage VBGR, thus the inverter output voltage OSCE being brought into a low level state.

[0015] This voltage transition halts the oscillation of the ring oscillator 2 and also the up-conversion of the charge pump 3.

[0016] Repetition of the operation described above obtains the up-converted voltage Vpp expressed as follows:

[0017] Vpp={1+(R2/R1)}X VBGR . . .   (1)

[0018] Shown in FIG. 14 is the equivalent circuit of the operational amplifier 1 of FIG. 12.

[0019] The operational amplifier 1 shown in FIG. 14 is provided with PMOS transistors Q1 and Q2 that constitute a current mirror, NMOS transistors Q3 and Q4 that turns on or off according to the logic of an input signal, an NMOS transistor Q5 that enables or disables the operational amplifier 1, and an NMOS transistor Q6 that validates or invalidates the output of the operational amplifier 1.

[0020] In FIG. 14, the transistor Q3 turns on when its gate voltage is higher than a gate voltage of the transistor Q4, thus the transistors Q1 and Q2 turn on to generate an output voltage VOUT almost equal to the positive power supply voltage Vdd.

[0021] On the other hand, the transistor Q4 turns on when its gate voltage is lower than a gate voltage of the transistor Q3, thus an output voltage VOUT becoming almost equal to the ground level.

[0022] Present DRAMs and FRAMs, etc., turn on its up-converter in operation when the memories are on (an operating mode), whereas turns it off when the memories are off (a waiting mode) for power saving. Up-converted power supply voltages are, however, used at many sections of the memories, thus resulting in a heavy load. Such an up-converter control takes a considerably long time for up-converting power supply voltages at desired levels.

[0023] An up-converter shown in FIG. 15 has been proposed for solving such a problem.

[0024] The up-converter shown in FIG. 15 is provided with a voltage controller 21afor the operating mode and a voltage controller 21bfor the waiting mode. Both controllers have almost the same circuitry. An operational amplifier Is of the voltage controller 21bis a low power consumption-type. Resistors R1H and R2H in the voltage controller 21bhave resistance higher than those of resistors R1L and R2L in the voltage controller 21a.

[0025] The operational amplifier 1a operates when a signal “active” indicating the operating mode is high, whereas and the operational amplifier 1b operates when a signal “standby” indicating the waiting mode is high.

[0026] The up-converter shown in FIG. 15, however, has the following drawbacks:

[0027] The driving performance of the up-converter is preferably restricted in the waiting mode because almost no circuitry in the semiconductor device operates in this mode. The waiting mode requires a small current consumed by the operational amplifier 1s, while larger resistance for the resistors R1H and R2H that constitute the resistor-voltage divider 5 (FIG. 12) for a small pass-current.

[0028] Decrease in current consumed by the operational amplifier 1scan be achieved by a well known technique, such as, provision of a current-limiting transistor.

[0029] However, the larger the resistance of the resistors R1H and R2H, the larger the area of resistor-wiring, and the larger the stray capacitance of the resistor-wiring. This results in signal delay due to resistor and capacitor, which causes a low voltage-feedback control.

[0030] Not only the up-converter, but also the down-converter has the same disadvantages as discussed below.

[0031] Shown in FIG. 16 is a circuit diagram of a typical down-converter.

[0032] The down-converter is provided with an operational amplifier 1, a PMOS transistor Q8, and resistors R1 and R2 that constitute a resistor-voltage divider.

[0033] Decrease in down-converted voltage Vout lower than a desired voltage causes decrease in a divided voltage TAP of the resistor-voltage divider lower than a reference voltage VBGR, which brings the output of the operational amplifier 1 into a lower level, to turn on the transistor Q8 for raising the voltage Vout.

[0034] Shown in FIG. 17 is a circuit diagram of another typical down-converter, provided with voltage controllers for the operating and waiting modes.

[0035] Like the up-converter shown in FIG. 12, the down-converter (FIG. 17) inevitably has a large chip size, a large delay through wiring, and a high production cost for power saving in the waiting mode due to the existence of resistor-voltage divider.

[0036] A purpose of the present invention is to provide a semiconductor device having a small chip size for power saving.

[0037] The present invention provides a semiconductor device including: an internal voltage generator for generating an internal voltage that is obtained up-converting or down-converting an external power supply voltage; a resistor-voltage divider, having a plurality of resistors, to output a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the first resistors; a capacitor-voltage divider, having a plurality of capacitors connected in series between an output terminal of the internal voltage generator and a ground level, to output a second divided voltage from the capacitors; and a comparator to compare a reference voltage and the first divided voltage for controlling the internal voltage generator according to a result of comparison, the comparator judging whether to halt operation of the internal voltage generator or not based on the result of comparison between the reference voltage and the first divided voltage while the internal voltage generator is operating, on the other hand, the comparator operating the internal voltage generator based on the result of comparison between the reference voltage and the second divided voltage while the internal voltage generator is not operating, the comparator further controlling the resistor-voltage divider so that a current flows therethrough only when the internal voltage generator is operating.

[0038] Moreover, the present invention provides a semiconductor device including: an internal voltage generator for generating an internal voltage that is obtained up-converting or down-converting an external power supply voltage; a resistor-voltage divider, having a plurality of resistors, to output a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the resistors; a capacitor-voltage divider, having a plurality of capacitors connected in series between an output terminal of the internal voltage generator and a ground level, to output a second divided voltage from the capacitors; and a comparator to compare a reference voltage and the first divided voltage for controlling the internal voltage generator according to a result of comparison, the comparator controlling the first resistor-voltage divider so that no current flows therethrough when the internal voltage generator is out of operation, to operate the internal voltage generator based on the result of comparison between the reference voltage and the second divided voltage.

[0039] Furthermore, the present invention provides a method of controlling an internal voltage of a semiconductor device, including the steps of: generating an internal voltage that is obtained up-converting or down-converting an external power supply voltage; outputting a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of a plurality of resistors; connecting the internal voltage and a ground level via capacitance, to output a second divided voltage by the capacitance-connection; judging whether or not to halt the internal voltage generation according to a result of comparison between a reference voltage and the first divided voltage while the internal voltage generation is proceeding, on the other hand, starting the internal voltage generation according to the result of comparison between the reference voltage and the second divided voltage while the internal voltage generation is not proceeding; and outputting the first divided voltage only when the voltage obtained up-converting or down-converting the external power supply voltage is being generated.

[0040] Moreover, the present invention provides a method of controlling an internal voltage of a semiconductor device, including the steps of: generating an internal voltage that is obtained up-converting or down-converting an external power supply voltage; outputting a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of a plurality of resistors; connecting the internal voltage and a ground level via capacitance, to output a second divided voltage by the capacitance-connection; placing the first divide-voltage as a ground level when the internal voltage obtained up-converting or down-converting the external power supply voltage is not generated; starting the internal voltage generation according to the result of comparison between a reference voltage and the second divided voltage.

[0041] FIG. 1 shows a circuit diagram of an up-converter as the first preferred embodiment according to the present invention;

[0042] FIG. 2 shows a circuit diagram of an up-converter as the second preferred embodiment according to the present invention;

[0043] FIG. 3 shows a circuit diagram of an operational amplifier 61 shown in FIG. 2;

[0044] FIG. 4 illustrates waveforms of an up-converted voltage Vpp, a voltage at a positive input terminal TAPC of an operational amplifier 1, an output voltage SOSCE of a power controller 6, and an output voltage OSCE of an inverter IV1 shown in FIG. 2;

[0045] FIG. 5 shows a circuit diagram of an up-converter as the third preferred embodiment according to the present invention;

[0046] FIG. 6 shows a circuit diagram of a capacitor-voltage divider and its periphery;

[0047] FIG. 7 illustrates a sectional view of a capacitor C1′shown in FIG. 6;

[0048] FIG. 8 shows an exemplary circuit diagram where transistor switches SW1 and SW2 in FIG. 6 are replaced with a CMOS-type;

[0049] FIG. 9 shows a circuit diagram of a down-converter where a resistor-voltage divider and a capacitor-voltage divider are connected in parallel, like shown in FIG. 1;

[0050] FIG. 10 shows a circuit diagram of a down-converter provided with a power controller that controls a power supply to an operational amplifier, like shown in FIG. 2;

[0051] FIG. 11 shows a circuit diagram of a down-converter provided with another resistor-voltage divider;

[0052] FIG. 12 shows a circuit diagram of a typical up-converter;

[0053] FIG. 13 illustrates waveforms of an up-converted voltage Vpp, a divided voltage TAP, and an output voltage OSCE of an inverter IV1 shown in FIG. 12;

[0054] FIG. 14 shows the equivalent circuit of the operational amplifier shown in FIG. 12;

[0055] FIG. 15 shows a circuit diagram of a typical up-converter provided with a voltage controller for an operating mode and a voltage controller for a waiting mode;

[0056] FIG. 16 shows is a circuit diagram of a typical down-converter; and

[0057] FIG. 17 shows a circuit diagram of another typical down-converter provided with voltage controllers for the operating and waiting modes.

[0058] Preferred embodiments according to the present invention will be disclosed with reference to the attached drawings.

[0059] Disclosed below, as examples of a semiconductor device, are an up-converter that up-converts a power supply voltage fed by the external circuitry and a down-converter that down-converts the externally-fed power supply voltage.

[0060] In the following disclosure, an up-converted voltage is an internal voltage obtained by up-converting a power supply voltage fed by the external circuitry and a down-converted voltage is an internal voltage obtained by down-converting the externally-fed power supply voltage.

[0061] [The First Preferred Embodiment]

[0062] The feature of the first embodiment of the up-converter lies in low power consumption in the waiting mode.

[0063] Shown in FIG. 1 is first embodiment of the up-converter. Elements in this embodiment that are the same as or analogous to elements in FIG. 12 are referenced by the same reference numbers.

[0064] Like shown in FIG. 12, the up-converter (FIG. 1) is provided with an operational amplifier 1 (the first operational amplifier), an inverter IV1, a ring oscillator 2, and a charge pump 3.

[0065] In addition to these elements, the up-converter (FIG. 1) is provided with a capacitor-voltage divider 4 constituted by capacitors C1 and C2 series-connected between an up-converted Vpp and the ground level, a first resistor-voltage divider 5 constituted by resistors R1 and R2 series-connected between the up-converted Vpp and the ground level, an NMOS transistor switch SW1 (the first switch) connected between the resistors R1 and R2, and an NMOS transistor switch SW2 (the second switch) connected between the divided-voltage output terminals of the capacitor-voltage divider 4 and the first resistor-voltage divider 5.

[0066] The output OSCE of the inverter IV1 is fed to both gates of the transistor switches SW1 and SW2. The operational amplifier 1 is constructed as shown in FIG. 14. The ring oscillator 2 and charge pump 3 constitute an internal voltage generator.

[0067] The operation of the up-converter shown in FIG. 1 is disclosed.

[0068] A steady state provides the same voltage to the positive input terminal TAPC and the negative input terminal VBGR of the operational amplifier 1.

[0069] Increase in up-converted voltage Vpp over a desired voltage triggers the operational amplifier 1 to output a positive output voltage, that brings the output OSCE of the inverter INV1 into a low level state. This voltage transition halts the oscillation of the ring oscillator 2; hence the charge pump 3 stops an up-conversion operation.

[0070] As time lapses under no up-conversion operation, the up-converted voltage Vpp gradually decreases due to leakage at PN-junction capacitance of transistors of a load circuitry (not shown) to which the up-converted voltage Vpp is supplied.

[0071] Decrease in up-converted voltage Vpp lower than the desired voltage causes decrease in a voltage at the positive input terminal TAPC of the operational amplifier 1 lower than the reference voltage VBGR. The output of the operational amplifier 1 thus lowers to bring the output of the inverter INV1 into a high level. This transition initiates the oscillation of the ring oscillator 2; hence the charge pump 3 starts an up-conversion operation.

[0072] The high level-output of the inverter INV1 turns on the transistor switches SW1 and SW2, which provides the same voltage level to the positive input terminal TAPC of the operational amplifier 1 and the node TAPR of the resistors R1 and R2.

[0073] As disclosed, the up-converted Vpp is controlled by means of the resistors R1 and R2 during the up-conversion operation of the charge pump 3.

[0074] On the other hand, increase in up-converted voltage Vpp higher than the desired voltage causes increase in a voltage at the positive input terminal TAPC of the operational amplifier 1 higher than the reference voltage VBGR, to bring the output of the inverter INV1 into a low level. This transition halts the oscillation of the ring oscillator 2; hence the charge pump 3 stops the up-conversion operation.

[0075] The non-up-conversion state turns off the transistor switches SW1 and SW2, thus no current flowing through the resistors R1 and R2. The up-converted voltage Vpp is then detected only by the capacitors C1 and C2.

[0076] As disclosed, while the charge pump 3 executes no up-conversion operation, or during decrease in up-converted voltage Vpp, the up-converted voltage Vpp is detected only by the capacitors C1 and C2. Decrease in up-converted voltage Vpp lower the desired voltage again brings the output of the inverter INV1 into a high level state to initiate the up-conversion operation of the charge pump 3.

[0077] As disclosed above,the first embodiment is provided with the transistor SW1 between the resistors R1 and R2 constituting the first resistor-voltage divider 5 and the capacitor-voltage divider 4 connected to the positive input terminal of the operational amplifier 1. The up-converted voltage Vpp in the waiting mode (no up-conversion operation by the charge pump 3) is detected only by the capacitor-voltage divider 4 while no current is flowing through the first resistor-voltage divider 5. The first embodiment thus achieves power saving in the waiting mode.

[0078] [The Second Preferred Embodiment]

[0079] The feature of the second embodiment of the up-converter lies also in low power consumption in the waiting mode, lower than the first embodiment.

[0080] Shown in FIG. 2 is the second embodiment of the up-converter. Elements in this embodiment that are the same as or analogous to elements in FIG. 1 are referenced by the same reference numbers.

[0081] The second embodiment is unique in a power controller 6 that controls a power supply voltage fed to the power supply terminal of the operational amplifier 1.

[0082] The power controller 6 is provided with an operational amplifier 61 (the second operational amplifier) and an inverter IV2 connected to the output terminal of the operational amplifier 61.

[0083] The operational amplifier 61 operates at an operating speed slower than the operational amplifier 1, however, is a low power consumption-type with a small operating current.

[0084] Like the operational amplifier 1, the operational amplifier 61 compares a divided voltage TAPC of the capacitor-voltage divider 4 and the reference voltage VBGR. The power supply voltage Vcc is always supplied to the power supply terminal of the operational amplifier 61, different from the operational amplifier 1.

[0085] Shown in FIG. 3 is the circuitry of the operational amplifier 61. The circuit components in FIG. 3 that are the same as or analogous to elements in FIG. 14 are referenced by the same reference numbers.

[0086] As shown in FIG. 3, the operational amplifier 61 is provided with a transistor Q7 between the transistors Q3 and Q4, and the transistor Q5.

[0087] Control of a gate voltage BIAS of the transistor Q7 limits a current flowing from the transistors Q1 to Q4 for decrease in current consumption.

[0088] Illustrated in FIG. 4 are voltage waveforms of the up-converted voltage Vpp, the voltage at the positive input terminal TAPC of the operational amplifier 1, the output voltage SOSCE of the power controller 6, and the output OSCE of the inverter IV1.

[0089] The operation of the up-converter shown in FIG. 2 will be explained with reference to the voltage waveforms illustrated in FIG. 4.

[0090] A steady state provides the same voltage to the positive input terminal TAPC and the negative input terminal VBGR of the operational amplifier 1.

[0091] Increase in up-converted voltage Vpp over a desired voltage raises the output voltage of the operational amplifier 1 to bring the output OSCE of the inverter INV1 into a low level state. This voltage transition halts the oscillation of the ring oscillator 2; hence the charge pump 3 stops an up-conversion operation.

[0092] The transistors SW1 and SW2 are turned off during no up-conversion operation; hence the up-converted voltage Vpp is detected only by the capacitor-voltage divider 4.

[0093] Increase in up-converted voltage Vpp over the desired voltage also raises the output voltage of the operational amplifier 61 to bring the output voltage of the inverter INV2 into a low level state, thus no power supply voltage being fed to the power supply terminal of the operational amplifier 1.

[0094] As disclosed, no up-conversion operation by the charge pump 3 provides no current to the first resistor-voltage divider 5 and also the operational amplifier 1, for achieving further power saving.

[0095] On the other hand, decrease in up-converted voltage Vpp below the desired voltage lowers the output voltage of the operational amplifier 61 to bring the output voltage of the inverter INV2 into a high level state. The power supply voltage is thus fed to the power supply terminal of the operational amplifier 1 to operate again. The decrease in up-converted voltage Vpp brings the output of the operational amplifier 1 into a low level for initiating the oscillation of the ring oscillator 2, hence the charge pump 3 re-starting the up-conversion operation.

[0096] The high-level output voltage of the inverter INV2 turns on the transistor switches SW1 and SW2 to provide almost the same voltage to the positive input terminal TAPC of the operational amplifier 1 and the divided voltage TAPR of the first resistor-voltage divider 5.

[0097] As disclosed, the up-conversion operation by the charge pump 3 provides a current to the first resistor-voltage divider 5 and the power supply voltage to the operational amplifier 1. The operational amplifier 1 thus controls the up-converted voltage Vpp with the first resistor-voltage divider 5.

[0098] As disclosed above, the second embodiment provides no power supply voltage to the operational amplifier 1 so as not to control the up-converted voltage Vpp during no up-conversion operation of the charge pump 3, thus achieving further power saving compared to the first embodiment.

[0099] [The Third Preferred Embodiment]

[0100] The third embodiment is a modification of the first and second embodiments, for achieving a stable positive input voltage to the operational amplifier.

[0101] Shown in FIG. 5 is third embodiment of the up-converter. Elements in this embodiment that are the same as or analogous to elements in FIG. 2 are referenced by the same reference numbers.

[0102] The third embodiment is unique in a second resistor-voltage divider 7 in addition to the elements of the second embodiment. The second resistor-voltage divider 7 is constituted by resistors R1′ and R2′ connected between the up-converted voltage Vpp and the ground level.

[0103] In the second embodiment shown in FIG. 2, no up-conversion operation of the charge pump 3 turns off the transistor switches SW1 and SW2, so that the positive input terminal of the operational amplifier 1 is connected only to the node TAPC of the capacitors C1 and C2. The positive input terminal of the operational amplifier 1 is brought into a complete floating state. Ideally, a voltage corresponding to a capacitance-ratio of the capacitors C1 and C2 is fed to the positive input terminal of the operational amplifier 1. However, in reality, the voltage at the positive input terminal of the operational amplifier 1 gradually lowers due to leakage at the PN-junction of the drain of the transistor switch SW2 connected to the node TAPC, thus increasing the number of operations of the charge pump 3. This results in large power consumption in the waiting mode.

[0104] Contrary to this, the resistors R1′ and R2′ connected to the capacitors C1 and C2 in parallel, as shown in FIG. 5, do not bring the positive input terminal of the operational amplifier 1 into a floating state even in the waiting mode.

[0105] The resistance ratio of the resistors R1′ and R2′ is preferably the same as that of the resistors R1 and R2, however, this is not a must. The resistances of the resistors R1′ and R2′ are preferably larger than those of the resistors R1 and R2. The former resistance, for example, hundred times the latter limits the current flowing through the resistors R1′ and R2′ in the waiting mode to 1/100 of the current flowing through the resistors R1 and R2 in the operating mode.

[0106] As disclosed above, the third embodiment provided with the second resistor-voltage divider 7 connected in parallel to the capacitor-voltage divider 4 prevents the positive input terminal of the operational amplifier 1 from being brought into a floating state while the charge pump 3 is out of operation. The third embodiment offers a stable voltage level at the positive input terminal of the operational amplifier 1, thus achieving power saving.

[0107] Like the second embodiment, the third embodiment is provided with the capacitor-voltage divider 4 for quick suppression of voltage variation in response to a sudden change in up-converted voltage Vpp, thus achieving suppression of voltage variation in up-converted voltage Vpp.

[0108] The second resistor-voltage divider 7 may be added to the up-converter shown in FIG. 1, which also prevents the positive input terminal of the operational amplifier 1 from being brought into a floating state while the charge pump 3 is out of operation, thus achieving power saving.

[0109] [The Fourth Preferred Embodiment]

[0110] The feature of the fourth embodiment lies in depression-type capacitors for avoiding leakage at a transistor PN-junction even in the floating state at the node of the capacitors.

[0111] Shown in FIG. 6 is a circuit diagram of a capacitor-voltage divider 4 and its periphery. The capacitor-voltage divider 4 is provided with depression-type capacitors C1′and C2′connected in series between the up-converted voltage Vpp and the ground level.

[0112] Illustrated in FIG. 7 is a sectional view of the capacitor C1′. The drain D and the source S of a MOS transistor at the ground level do not cause leakage at the PN-junction between the drain terminal and the substrate. On the other hand, the capacitor C2′ is constructed such that the drain and the source of a MOS transistor are placed at the power supply voltage level so as not cause leakage at the PN-junction.

[0113] Shown in FIG. 8 is a circuit diagram provided with CMOS-type transistor switches SW1 and SW2. The CMOS-type transistor is not affected by a threshold level of a MOS transistor for accurate voltage transfer to the operational amplifier 1 according to the resistance ratio of the first resistor-voltage divider 5 and the capacitance ratio of the capacitor-voltage divider 4.

[0114] [The Other Preferred Embodiments]

[0115] The preferred embodiments described so far relate to an up-converter for power saving. However, not only the up-converter, but also the present invention is applicable to a down-converter.

[0116] Shown in FIG. 9 is a circuit diagram of a down-converter provided with a resistor-voltage divider and a capacitor-voltage divider, like shown in FIG. 1.

[0117] Elements in this embodiment that are the same as or analogous to elements in FIG. 1 are referenced by the same reference numbers.

[0118] The down-converter (FIG. 9) is provided with an operational amplifier 1, a PMOS transistor Q8, a capacitor-voltage divider 4 constituted by capacitors C1 and C2 connected in series between a down-converted voltage Vout and the ground level, a first resistor-voltage divider 5 constituted by resistors R1 and R2 connected in series between the down-converted voltage Vout and the ground level, a PMOS transistor switch SW10 (the first switch) connected between the resistors R1 and R2, and a PMOS transistor switch SW20 (the second switch) connected between the capacitor-voltage divider 4 and the first resistor-voltage divider 5.

[0119] The output OSCE of the operational amplifier 1 is fed to both the gates of the transistor switches SW1O and SW20.

[0120] Increase in down-converted voltage Vout higher than a desired voltage brings a divided voltage TAPR of the resistor-voltage divider 5 into a level higher than a reference voltage VBGR. The transition gradually raises the output voltage of the operational amplifier 1, to turn off the transistor Q8 for lowering the down-converted voltage Vout.

[0121] The high level-output of the operational amplifier 1 turns off the transistor switches SW10 and SW20, which provides no current flowing therethrough. The down-converted voltage Vout is thus detected only by the capacitors C1 and C2 for power saving.

[0122] This embodiment is provided with the capacitor-voltage divider 4 for quick suppression of voltage variation in response to a sudden change in down-converted voltage Vout.

[0123] On the other hand, decrease in down-converted voltage Vout lower than the desired voltage brings a divided voltage TAPR of the resistor-voltage divider 5 into a level lower than the reference voltage VBGR. The transition gradually lowers the output voltage of the operational amplifier 1, to turn on the transistor Q8 for raising the down-converted voltage Vout.

[0124] The down-converter shown in FIG. 10 is unique in a power controller 6 that controls a power supply voltage fed to the power supply terminal of the operational amplifier 1.

[0125] Elements in this embodiment that are the same as or analogous to elements in FIG. 9 are referenced by the same reference numbers.

[0126] The power controller 6 is provided with an operational amplifier 61 (the second operational amplifier) and an inverter IV2 connected to the output terminal of the operational amplifier 61.

[0127] The operational amplifier 61 operates at an operating speed slower than the operational amplifier 1, however, is a low power consumption-type with a small operating current, like shown in FIG. 3.

[0128] Like the operational amplifier 1, the operational amplifier 61 compares a divided voltage TAPC of the capacitor-voltage divider 4 and the reference voltage VBGR. The power supply voltage Vcc is always supplied to the power supply terminal of the operational amplifier 61, different from the operational amplifier 1.

[0129] In FIG. 10, a steady state provides the same voltage to the positive input terminal TAPC and the negative input terminal VBGR of the operational amplifier 1.

[0130] Increase in down-converted voltage Vout over a desired voltage raises the output voltage of the operational amplifier 1 to turn off the transistor Q8 for down-conversion operation. The transistors SW10 and SW20 are turned off during down-version operation; hence the down-converted voltage Vout is detected only by the capacitor-voltage divider 4.

[0131] Increase in down-converted voltage Vout over the desired voltage also raises the output voltage of the operational amplifier 61 to bring the output voltage of the inverter INV2 into a low level state, thus no power supply voltage being fed to the power supply terminal of the operational amplifier 1.

[0132] As disclosed, down-conversion operation provides no current to the operational amplifier 1, for achieving power saving.

[0133] On the other hand, decrease in down-converted voltage Vout below the desired voltage lowers the output voltage of the operational amplifier 61 to bring the output voltage of the inverter INV2 into a high level state. The power supply voltage is thus fed to the power supply terminal of the operational amplifier 1 to operate again. The decrease in down-converted voltage Vpp brings the output of the operational amplifier 1 in to a low level to turn on the transistor Q8 for raising the down-converted voltage Vout.

[0134] As disclosed above, this embodiment provides no power supply voltage to the operational amplifier 1 during down conversion operation, thus achieving further power saving compared to the embodiment shown in FIG. 9.

[0135] The embodiment shown in FIG. 11 is unique in a second resistor-voltage divider 7 in addition to the elements shown in FIG. 10. The second resistor-voltage divider 7 is constituted by resistors R1′ and R2′ connected between the down-converted voltage Vout and the ground level.

[0136] In the embodiment shown in FIG. 10, increase in down-converted voltage Vout turns off the transistor switches SW10 and SW20, so that the positive input terminal of the operational amplifier 1 is connected only to the node TAPC of the capacitors C1 and C2. The positive input terminal of the operational amplifier 1 is brought into a complete floating state. Ideally, a voltage corresponding to a capacitance-ratio of the capacitors C1 and C2 is fed to the positive input terminal of the operational amplifier 1. However, in reality, the voltage at the positive input terminal of the operational amplifier 1 gradually lowers due to leakage at the PN-junction of the drain of the transistor switch SW20 connected to the node TAPC, to turn on the transistor Q8, thus increasing the number of operations of raising the down-converted voltage Vout. This results in large power consumption in the waiting mode.

[0137] Contrary to this, the resistors R1′ and R2′ connected to the capacitors C1 and C2 in parallel, as shown in FIG. 11, do not bring the positive input terminal of the operational amplifier 1 into a floating state.

[0138] The resistance ratio of the resistors R1′ and R2′ is preferably the same as that of the resistors R1 and R2, however, this is not a must. The resistances of the resistors R1′ and R2′ are preferably larger than those of the resistors R1 and R2. The former resistance, for example, hundred times the latter limits the current flowing through the resistors R1′ and R2′ in the waiting mode to 1/100 of the current flowing through the resistors R1 and R2 in the operating mode.

[0139] As disclosed above, the embodiment shown in FIG. 11 provided with the second resistor-voltage divider 7 connected in parallel to the capacitor-voltage divider 4 prevents the positive input terminal of the operational amplifier 1 from being brought into a floating state while lowering the down-converted voltage Vout. This embodiment offers a stable voltage level at the positive input terminal of the operational amplifier 1, thus achieving power saving.

[0140] Like the embodiment shown in FIG. 9, this embodiment is provided with the capacitor-voltage divider 4 for quick suppression of voltage variation in response to a sudden change in down-converted voltage Vout, thus achieving suppression of voltage variation in down-converted voltage Vout.

[0141] The down-converters shown in FIGS. 9 to 11 are constructed almost same as the up-converters, such as, shown in FIG. 1, except the transistor Q9 instead of the ring oscillator 2 and the charge pump 3 and the PMOS transistor switches TW10 and TW20 instead of the NMOS transistor switches TW1 and TW2. Therefore, the present invention achieves power saving with a small chip size also in the down-converter.

[0142] As disclosed above, according to the present invention, the internal voltage, such as, the up-converted voltage and the down-converted voltage, is detected by the capacitor-voltage divider while no current is flowing through the resistor-voltage divider in the waiting mode where the internal voltage generator is out of operation. The present invention therefore achieves power saving in the waiting mode.

[0143] Moreover, since the capacitor-voltage divider quickly follows internal voltage variation, the present invention achieves a feedback control to regain a desired internal voltage even if it varies suddenly.