Combined Resistance-Capacitance Ladder Voltage Divider Circuit

The purpose of this invention is to provide a high impedance voltage divider that divides accurately for both low-frequency and high-frequency variations in the input voltage. As a result, both a transient-pulse input and its divided transient-pulse output have substantially the same shape.

FIGS. 1 and 2 illustrate a prior-art resistor voltage divider and a prior-art capacitor voltage divider, respectively. V.sub.OUT is the output voltage, V.sub.IN is the input voltage, R.sub.1 and R.sub.2 are resistors, C.sub.1 and C.sub.2 are capacitors. For the resistor divider, V.sub.OUT is equal to V.sub.IN R.sub.2 /(R.sub.1 +R.sub.2). For the capacitor divider, V.sub.OUT is equal to V.sub.IN C.sub.1 /(C.sub.1 +C.sub.2).

An advantage of the capacitor divider is that its output voltage does not tend to lag changes in the input voltage. A disadvantage is that, over time, any intrinsic conductive leakage across the capacitors will corrupt the ratio. Furthermore, the ratio is not valid unless the capacitor divider is initialized correctly. That is, the initial charge on the capacitors must be correct for the divider to operate properly. A typical such initial condition is V.sub.OUT =V.sub.IN =0.

A disadvantage of the resistor divider is that it draws direct current from the power supply. Minimizing this direct current requires maximizing the ohmic value of the sum of resistances R.sub.1 +R.sub.2. Since there is necessarily an output capacitance connected to the output terminal V.sub.OUT, a large ohmic value of resistor R.sub.2 slows operation of the resistor divider. That is, when input voltage V.sub.IN changes, output voltage V.sub.OUT is incorrect for a period of time. That period of time may be too long for the circuit application. Another drawback to increasing the ohmic value of resistors R.sub.1 and R.sub.2 is that the circuit is more vulnerable to disturbances from switches and other noise sources that may couple to output voltage terminal V.sub.OUT. One way to reduce noise sensitivity is to add a large capacitor load to output voltage terminal V.sub.OUT. This, however, further slows the response time of the circuit.

There is a need for a voltage divider that overcomes the foregoing disadvantages.

This invention is a voltage divider circuit having an input voltage at a first terminal and an output voltage at a second terminal. The circuit includes a parallel-connected first resistor and first capacitor coupled between the first and second terminals and a parallel-connected second resistor and second capacitor coupled between the second terminal and a reference. The ratio of the ohmic value of the second resistor to the sum of the ohmic values of the first and second resistors is substantially equal to the ratio of the value in farads of the first capacitor to the sum of the values in farads of the first and second capacitors.

In the drawings:

FIG. 1 is a prior-art resistor voltage divide;

FIG. 2 is a prior-art capacitor voltage divider;

FIG. 3 is the resistance-capacitance ladder voltage divider of this invention;

FIG. 4 illustrates a specific use of this circuit in an integrated circuit chip; and

FIG. 5 illustrates construction of the circuit using P-channel diodes to conserve space.

An exemplary circuit of this invention is illustrated in FIG. 3. The invention combines a resistor divider R.sub.1,R.sub.2 and a capacitor divider C.sub.1,C.sub.2 in parallel. Direct current is minimized by making the resistances R.sub.1 and R.sub.2 large. The capacitors C.sub.1 and C.sub.2 reduce noise sensitivity and also cause the circuit to work correctly at high speeds. Initialization is accomplished by the resistor divider R.sub.1, R.sub.2. The resistor divider R.sub.1, R.sub.2 also maintains the voltage ratio V.sub.OUT /V.sub.IN over an indefinite period of time. The ratio of the ohmic value of the second resistor R.sub.2 to the sum of the ohmic values of the first and second resistors (R.sub.1 +R.sub.2) is substantially equal to the ratio of the value in farads of the first capacitor C.sub.1 to the sum of the values in farads of the first and second capacitors (C.sub.1 +C.sub.2). That restriction is equivalent to restricting the time constant R.sub.1 C.sub.1 to be equal to the time constant R.sub.2 C.sub.2.

Note that, alternatively, the voltage at the reference terminal V.sub.REF may be a non-zero voltage.

A specific use of this circuit in an integrated circuit chip is illustrated in FIG. 4. This particular application requires a high-impedance, two-to-one voltage divider where the second voltage V.sub.OUT2 is one-half of the first voltage V.sub.OUT1. Voltages V.sub.OUT1 and V.sub.OUT2 are reference output voltages furnished by the circuit of FIG. 4 from a regulator voltage input V.sub.REG. For stability, diode resistor MP1 and the voltage divider DIV should draw low current. Also, the voltage divider DIV acts as the pull-down on first output voltage V.sub.OUT1. To conserve space, the resistor divider R1,R2 is constructed of P-channel diodes. The circuit is illustrated in FIG. 5, in which diode resistors MP2 and MP3 are matched, forming a two-to-one voltage divider. Capacitors C.sub.2 and C.sub.1 are also matched, forming a second two-to-one divider. Capacitor C.sub.3 further stabilizes V.sub.OUT1 and may have any value.

Resistors R.sub.1 and R.sub.2 each have an intrinsic capacitance determined primarily by the size and type of source-drain diffusion used for construction of the P-channel diodes used in the example embodiment. The intrinsic capacitance of resistor R.sub.1 should be less than about one-tenth of the capacitance of capacitor C.sub.1. If not, the intrinsic capacitance of resistor R.sub.1 should be subtracted from the design value of capacitor C.sub.1. Similarly, the resistor R.sub.2 and the load should either have intrinsic capacitances that total less than about one-tenth of the design value for capacitance of capacitor C.sub.2. If not, those intrinsic capacitances should be subtracted from the design value for capacitance of capacitor C.sub.2.

Capacitors C.sub.1 and C.sub.2 each have an intrinsic conductance determined primarily by insulator and/or junction leakage. The intrinsic conductance of capacitor C.sub.1 should be less than about one-tenth of the design value of the conductance of resistor R.sub.1. If not, the intrinsic conductance of capacitor C.sub.1 should be subtracted from the design value for conductance of resistor R.sub.1. Similarly, the capacitor C.sub.2 and the load should either have intrinsic conductances that total less than about one-tenth of the design value for conductance of resistor R.sub.2. If not, those intrinsic conductances should be subtracted from the design value for conductance of resistor R.sub.2.

While this invention has been described with respect to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Upon reference to this description, various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art. It is contemplated that the appended claims will cover any such modifications or embodiments that fall within the scope of the invention.