Method and System for Calibrating Analog-to-Digital Conversion

1. Technical Field of the Invention

The present invention relates in general to the field of analog-to-digital converters (ADCs), and in particular, to digital calibration of ADCs in which the calibration may be accomplished with dynamic estimation of reference signals that have unknown parameters.

2. Description of Related Art

The natural world operates in an analog domain, but information signals (voice, data, etc.) may frequently be processed, transmitted, or otherwise manipulated more efficiently in the digital domain. The conversion from the analog domain to the digital domain is accomplished with ADCs. An ADC receives as input an analog signal and produces as output a digital signal. However, some information present in the analog signal is necessarily lost during the conversion process even if an ADC is operating in an ideal manner. Unfortunately, real-world ADCs do not operate in an ideal manner. Consequently, the digital output of a real-world ADC does not track the analog input even as accurately an ideal ADC.

It is therefore beneficial to make and/or tune real-world ADCs to approximate ideal ADCs. Techniques have been developed to calibrate real-world ADCs so as to modify their performance to emulate ideal ADCs as closely as possible. For example, ADCs are traditionally calibrated using high precision digital voltmeters to characterize the errors that result from digitizing static or slowly varying analog reference voltages. The outcome from this static testing forms the basis for a hardware or software implemented calibration scheme. Another method of conventional ADC calibration is the use of a sinusoidal reference signal. The reference is sampled, and estimations of the ideal sample values are calculated. These estimations are calculated using a minimum squared error criterion that requires knowledge of the frequency of the calibration signal. The errors (i.e., the difference between the estimated values and the actual sampled values output by the ADC being calibrated) are then used to build a correction table. The correction table may subsequently be used to modify sampled values of actual (e.g., non-calibration, functional, etc.) analog input signals.

Efficient calibration schemes require that the reference signal be dynamically estimated on a sample-by-sample basis during the ADC calibration period(s). No method currently exists for dynamic estimation of a reference signal (e.g., a calibration signal) with one or more unknown parameters (e.g., frequency, phase, etc.) during an ADC calibration. Hence, existing calibration procedures rely on accurate and costly signal generators and/or precise and expensive measuring components.

The deficiencies of the prior art are overcome by the method and system of the present invention. For example, as heretofore unrecognized, it would be beneficial to enable calibration of ADCs using a reference signal of a given waveform type, but with unknown parameters. In fact, it would be beneficial if such a calibration procedure could also be accomplished in real-time using overflow processing capacity of a system in which a single ADC is employed.

These and other benefits are achieved by the method and system of the present invention in which ADCs are calibrated using an analog calibration signal that is easy to generate (e.g., a sinusoidal signal). The present invention, however, is equally applicable to other calibration signals as well, such as saw-tooth and triangle waves. Advantageously, a calibration scheme in accordance with the principles of the present invention is independent of the actual parameters of the calibration signal (e.g., amplitude, frequency, initial phase, etc. for a sinusoidal-type calibration signal). Relevant parameters of an applied calibration signal that are needed for a calibration are calculated from the converted digital data.

In one embodiment, the present invention is composed of several exemplary operational components. An estimator calculates estimates of relevant parameter(s) (e.g., the frequency) of a calibration signal of a known waveform type from the digital outputs of an ADC. A filter utilizes the temporal information and at least one variable related to the estimated parameter(s) of the calibration signal to reconstruct the calibration signal in the digital domain. Also, a table generator calculates correction table entries from the ADC output and the reconstructed calibration signal. These exemplary components may be implemented in either hardware, software, or some combination thereof. Other principles of the present invention, including alternative specific embodiments, are further explained below.

An important technical advantage of the present invention is that it enables ADC calibration to be fully implemented in software.

Another important technical advantage of the present invention is that it provides robustness against variations in an analog calibration signal.

Yet another important technical advantage of the present invention is the ability to improve the efficiency of ADC calibration; consequently, fewer samples of the calibration signal are required.

The above-described and other features of the present invention are explained in detail hereinafter with reference to the illustrative examples shown in the accompanying drawings. Those skilled in the art will appreciate that the described embodiments are provided for purposes of illustration and understanding and that numerous equivalent embodiments are contemplated herein.

A more complete understanding of the method and system of the present invention may be had by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 illustrates an exemplary ADC environment in which the present invention may be advantageously implemented;

FIG. 2A illustrates an exemplary analog input signal versus digital output signal graph of an ideal ADC;

FIG. 2B illustrates an exemplary analog input signal versus digital output signal graph of a practical ADC;

FIG. 3A illustrates an exemplary application of calibration in accordance with the present invention;

FIG. 3B illustrates another exemplary application of calibration in accordance with the present invention;

FIG. 4A illustrates an exemplary ADC and an associated calibrator with selected signals denoted in accordance with the present invention;

FIG. 4B illustrates exemplary details of one embodiment of calibration logic in accordance with the present invention;

FIG. 4C illustrates exemplary details of another embodiment of calibration logic in accordance with the present invention;

FIG. 5 illustrates a method in flowchart form for calibrating an ADC in accordance with the present invention;

FIG. 6 illustrates a reference signal reconstruction analysis in graphical form; and

FIG. 7 illustrates un-calibrated and calibrated performance characteristics in graphical form.

A preferred embodiment of the present invention and its advantages are best understood by referring to FIGS. 1-7 of the drawings, like numerals being used for like and corresponding parts of the various drawings.

Referring now to FIG. 1, an exemplary ADC environment in which the present invention may be advantageously implemented is illustrated. An ADC 105 is shown as part of a telecommunications system environment 100. Specifically, environment 100 includes a receiver 115 of a mobile radio system base station (BS) 110 in communication with a telephone switching system (SS) 120 (e.g., a node in a wireline system). The receiver 115 provides an analog incoming signal (e.g., transmitted from a mobile station (MS) (not shown) of the mobile radio system) to an analog filter H(s) 125 that limits the bandwidth of the ADC 105 analog input signal to one Nyquist zone. The digital output signal of the ADC 105 is connected to a digital filter H(z) 130, which may further filter the incoming signal. The output of the digital filter H(z) 130 may be processed further and forwarded to the SS 120.

The ADC 105 converts a time continuous and amplitude continuous signal to a time discrete and amplitude discrete signal. The output data rate of the ADC 105 is controlled by a sampling clock generator 135 with frequency F.sub.s, which is also the data rate of the ADC output. The ADC 105 may optionally include a sample and hold (S/H) circuit (not shown in FIG. 1), which holds an instantaneous value of the (analog filtered) analog input signal, which is received from the analog filter H(s) 125, at selected instants of time so that the ADC 105 may sample them.

The ADC 105 quantizes each sampled analog input signal into one of a finite number of levels and represents (e.g., codes) each level into a bit pattern that is delivered as the digital output at the rate of the sampling clock generator 135. The digital output of the ADC 105 is composed of an exemplary number of eight (8) bits. Hence, 256 levels may be represented. The telecommunications system environment 100 will be used to describe a preferred embodiment of the present invention. However, it should be understood that the principles of the present invention are applicable to other ADC environments, such as video implementations, delta modulation, a flash ADC, an integrating ADC, pulse code modulation (PCM), a sigma-delta ADC, and a successive approximation ADC.

Referring now to FIG. 2A, an exemplary analog input signal versus digital output signal graph of an ideal ADC is illustrated. The ideal ADC graph is shown generally at 200. The abscissa axis 210 represents the analog input, and the ordinate axis 220 represents the level of digital output. The dashed diagonal line 230 represents a linear, non-quantized output response for the analog input signal; it is used here as an aiming line for the quantized output. The corresponding output of the ideal ADC is represented by the stair-stepped line 240. As can be seen, the ideal ADC digital output 240 tracks the analog input 230 as accurately as possible with a given number of quantization levels (e.g., resolution) and sampling rate.

Referring now to FIG. 2B, an exemplary analog input signal versus digital output signal graph of a practical ADC is illustrated. The practical ADC graph is shown generally at 250. The dashed diagonal line 230 is again shown as an aiming line for ideal mid-step transition of the digital output. The corresponding output of the practical ADC is represented by the roughly stair-stepped line 260. As can be seen, the practical ADC digital output 260 does not track the analog input 230 as accurately as does the ideal ADC (of FIG. 2A) with the same given number of quantization levels and sampling rate. Thus, it can be seen that the effective number of bits b.sub.EFF of a b-bit ADC may differ from the actual number of bits (b) due to errors (e.g., offset errors, gain errors, and linearity errors). The ADC calibration principles of the present invention advantageously ameliorate these various error conditions.

Application of the ADC calibration principles of the present invention provides many advantages over conventional approaches. For example, robustness against variations in the analog calibration signal is provided. There is no need for highly-stable signal generators because the present invention calculates relevant parametrical information from quantized samples of the calibration signal utilizing prior knowledge of the waveform type. The calibration signal may be generated by a low-complexity, low-precision (but spectrally pure) local oscillator included in the system using the ADC (e.g., the system may be an integrated circuit (IC), BS, etc.). The present invention allows for a design using two ADCs that switches between reference and functional input signals, where one ADC is being calibrated while the other is running functionally. Using this solution, the calibrated ADC(s) may be sensitive to temperature drift without requiring the cessation of functional data conversion while implementing repetitive calibration.

Another exemplary advantage of the present invention is increased efficiency as compared to conventional solutions. Because the filter (as explained further below) yields a better estimation of the reference signal than prior methods, fewer samples of the reference signal are needed for calibration. Additionally, the calibration scheme may be fully implemented in software. If the system the ADC is connected to has sufficient overflow capacity, then no additional digital signal processing (DSP) resources (e.g., hardware, processing cycles, etc.) are needed. In principle, the calibration may be made transparently during normal operation and delayed by only a memory access by utilizing, for example, a known pilot, as explained further below. The correction table may therefore be trained incrementally with short bursts of samples from the pilot tone used as a reference signal, thus allowing for a design using only one ADC, which is alternately connected to the reference signal and calibrated incrementally during known intermissions of the incoming functional signal.

A pilot is a signal which stands apart from the information portion of the overall signal channel, but is carried by the same physical transmission medium. The pilot may occupy just one frequency in the utilized signal band (a so-called pilot tone), and the information may be spread in frequency to the side or around the pilot, but not on the same frequency as the pilot. A pilot is often used to adjust the system to carry the information with as high a quality as possible. Because the pilot has well-known characteristics, it may be measured and used to adjust signal level, synchronize clocks, etc., regardless of the information carried on the channel. In accordance with the principles of the present invention, the pilot signal, which may already be present in the relevant system for other purposes, may be used as a reference signal to calibrate the ADC.

A still further advantage provided by application of the principles of the present invention is that the calibration scheme adapts to the reference signal, requiring knowledge of the waveform type only. This allows for both a calibration procedure using several different frequencies and a design using an extended correction table. The correction table addressing is then extended with addresses depending upon the difference between the value of the previous sample and that of the current sample. This corrects the dynamic aspect of the errors in the ADC. Moreover, improvement of the linearity may be enhanced still further by preloading the correction table and using the output thereof for the calibration scheme. Thus, the calibrator becomes a feedback system. The improvement is due, at least in part, to the more-accurate amplitude estimation of the reference signal.

Referring now to FIG. 3A, an exemplary application of calibration in accordance with the present invention is illustrated. An ADC 310A and calibrator 340A are shown generally at 300. The ADC 310A may receive an analog functional input signal, and the calibrator 340A produces a digital calibrated output signal. The ADC 310A may be, for example, equivalent to the ADC 105 (of FIG. 1), and the calibrator 340A may include a correction table 350. When the ADC 310A is to be processing an incoming functional signal, a switch 330A is connected to the functional signal, and a switch 330B need not be connected to the output of the ADC 310A. However, when the functional signal is engaged in a known intermission, for example, the switch 330A is connected to the reference signal, and the switch 330B connects the output of the ADC 310A to the calibration logic (CL) 320. The CL 320 may produce correction table outputs for the correction table 350. In this manner, the speed of the CL 320 of the present invention enables real-time calibration with only a single ADC 310A. It should be understood that the switch 330B may alternatively be part of the calibrator 340A.

Thus, the switch 330A serves to switch between the functional operating mode and the calibration operating mode. The switch 330B, on the other hand, also enables a feedback system to be activated during calibration. The calibration procedure may therefore be accomplished in two phases. In the first phase, the switch 330B is connected to the ADC 310A output. When the correction table 350 has been trained, the switch 330B is connected to the output of the correction table 350, which enables a finer tuning of the table. The ADC 310A and the calibrator 340A of 300, for example, may benefit from calibration using a pilot tone. For example, if there is a pilot tone with an amplitude using most of the ADC 310A input range on the functional signal and if there exists a known intermission in the information carrying part of the spectrum, then this intermission can be used for ADC calibration using the pilot as a calibrating reference.

Referring now to FIG. 3B, another exemplary application of calibration in accordance with the present invention is illustrated. The present invention also enables real-time calibration with two ADCs as shown generally at 360. A reference signal and a functional signal are alternately input to a pair of ADCs 310B and 310C via switches 330C and 330D, respectively. While one is receiving the reference signal, the other is receiving and operating on the functional signal. ADC 310B and 310C forward their outputs as inputs to calibrators 340B and 340C, respectively. Switch 330E selects, for providing as the calibrated output, the forwarded digital signal that corresponds to the analog functional input signal. In this manner, calibration may be constantly in process, if desired. Advantageously, this two-ADC exemplary application enables, during a normal calibration operation, calibration to account for drift and changes during the normal operation.

It should be noted that the calibration resources may be shared, except for the correction table 350. In other words, a single calibrator 340 may alternatively receive the output of the ADCs 310B and 310C (e.g., by means of a switch) (not shown). The three switches 330C, 330D, and 330E may be synchronized. The switch transition is a fraction of the sampling period so that functional converted data passing through the system is not interrupted. In the exemplary application 360, the ADCs 310B and 310C should not have an internal delay in order for all the switches to be in the same phase. This may be solved, however, with a delay of the output switch 330E (not explicitly shown).

Referring now to FIG. 4A, an exemplary ADC and an associated calibrator are illustrated with selected signals denoted in accordance with the present invention. An exemplary ADC 310 and an exemplary calibrator 340 are shown generally at 400. The analog input signal s(t) (e.g., an airborne radio wave analog voice signal emanating from an MS transmitter (not shown), received at the receiver 115 (of FIG. 1), and frequency downconverted and filtered inside the BS 110) is supplied to the ADC 310. The ADC 310 may correspond to, for example, the ADC 105 of the BS 110 (of FIG. 1). It should be understood that the ADC 310 (and hence the ADC 105) may include the calibrator 340.

Continuing with FIG. 4A, the ADC 310 may include, for example, a sampler 405, a quantizer 410, and a coder 415. It should be understood, however, that the present invention is applicable to other ADC designs. The sampler 405 samples the incoming analog input signal s(t) and produces the time discrete sampled signal s(k), which is forwarded to the quantizer 410. The signal is then converted to the digital output x(k) by the quantizer 410 and the coder 415. The digital output x(k) is supplied to the calibrator 340, which includes the correction table 350 and the CL 320. The calibrator 340 then produces the calibrated digital signal y(k).

Referring now to FIG. 4B, exemplary details of one embodiment of calibration logic in accordance with the present invention are illustrated. The calibrator 340 is shown receiving the digital output signal x(k) of the ADC 310 (of FIG. 4A) and producing the calibrated digital signal y(k). The calibrator 340 includes the correction table 350 and the CL 320. The digital output signal x(k) is supplied to three exemplary components of the CL 320, which are described in mathematical detail below. First, the digital output signal x(k) is supplied as an input to an estimator/calculator 460. The estimator/calculator 460 (i) estimates at least one parameter (e.g., the frequency .omega.) relating to the analog input reference signal s(t) and (ii) calculates coefficients (e.g., the coefficients c.sub.l). Second, the digital output signal x(k) is supplied as an input (along with the coefficients c.sub.l) to a finite impulse response (FIR) filter 455. The FIR filter 455 produces an estimate of s(k) (e.g., s(k)), where s(k) may, for example, correspond to the output of the sampler 405 (of FIG. 4A). It should be noted that other filter types may alternatively be used. For example, an Infinite Impulse Response (IIR) filter may be used in place of the FIR filter 455.

Third, the correction calculator 465 also receives the digital output signal x(k) as an input. The correction calculator 465 computes table entries (e.g., the values of s.sub.i) for the correction table 350 using the digital output signal x(k) along with the calculated s(k) from the FIR filter 455. During calibration operation mode, the digital output signal x(k) is used to address the correction table 350, and the output of the correction table s.sub.i is the data written/stored to the table entry for that address. The correction table 350 may be, for example, stored in a memory (e.g., a random access memory (RAM) or a serial access memory (SAM)). It should be understood that the correction table 350 need not be in tabular form, for it may be organized into any convenient data structure.

During functional operation mode, the digital output signal x(k) continues to be used to address the correction table 350, but the value of the table entry at that address is read/retrieved and then output as the variable y(k). Hence, the digital output signal x(k) is passed through the correction table 350 in both functional and calibration operation modes. The correction table 350 is preferably initialized with s.sub.i =x.sub.i for every input level (i=0, . . . , M-1) before functional use of the y(k) data and before any calibration (such initialization is not explicitly shown) The calibration may thus be performed later when a scheduled calibration phase occurs in the system.

Each of the functional units (components) shown in the calibrator 340 are described more fully in mathematical form below. It should be understood that the FIR filter 455, the estimator/calculator 460, and the correction calculator 465 need not be discrete electronic hardware units. Each may alternatively be implemented (either fully or partially) in software using, for example, a general purpose DSP. Furthermore, each may be implemented using excess computing capacity in whatever system (e.g., a BS) in which the calibrator 340 and the ADC 310 are being employed. Moreover, each may be implemented in either hardware, software, firmware, etc., or some combination thereof and/or share resources such as memory and/or processor cycles. It should be further understood that the calibrator 340 may be incorporated as part of the ADC 310.

Referring now to FIG. 4C, exemplary details of another embodiment of calibration logic in accordance with the present invention are illustrated. The exemplary details of this calibration logic embodiment are designated generally by 480 and are specially targeted for implementations in which the number of calibration samples may be limited. In the calibrator 480, the correction calculator 465 (of the calibrator 340 of FIG. 4B) is replaced by a "(1-C)" multiplier 485, a summer 490, and a "C" multiplier 495, which forms a feedback loop from the output of the correction table 350. The input s.sub.i to the correction table 350 therefore becomes the sum of Cs.sub.i and (1-)s(k). Calibrator 480 will likewise be explained in greater mathematical detail below.

Multiple schemes have previously been proposed in order to calibrate ADCs. In fact, a calibration scheme has recently been proposed that works in the digital domain only in S.-H. Lee and B.-S. Song, "Digital-domain calibration of multistep analog-to-digital converters", IEEE Journal on Solid-State Circuits, Vol. 27, No. 12, pp. 1679-1688, 1992, which is hereby incorporated by reference in its entirety herein. One drawback with a method such as the one in Lee and Song's article is that it requires accurate signal generators and measurement devices to measure the code errors.

In contradistinction, the calibration scheme for ADCs in accordance with the present invention does not require such accurate signal generators and measurement devices. The scheme may be implemented fully digitally and completely in software. Furthermore, it does not require internal calibration circuitry. The calibration scheme does entail, on the other hand, a calibration signal connected to the ADC input. It also may include the storing of code errors directly in memory; consequently, the normal conversion is not slowed by error calculations.

The calibration procedure utilizes a known waveform as the calibration signal, such as a sine wave signal, a sum of several sine wave signals, a saw-tooth signal, a triangle wave signal, etc. In an exemplary embodiment that is described below, the calibration scheme for sinusoidal calibration signals is described, but it should be understood that other waveform types may be employed. The scheme may be decomposed into the following exemplary functional blocks, each of which is described in further detail below: First is a processor for estimating the frequency of the analog input s(t), where the estimate .omega. is computed from the quantized output x(k) of the ADC. Second is a linear time invariant FIR filter having as input the output x(k) of the ADC, such that characteristics of the filter include coefficients which are set to minimize the noise gain. The filter output s(k) is a reconstruction of the analog calibration signal at the given sampling instants (in principle, a continuous-amplitude discrete-time signal). And, a third functional block is a processor for computing an updated reconstruction table in dependence upon x(k) and s(k).

A derivation of a calibration scheme in accordance with the present invention is summarized in Table 1.

Initially, the calibration signal is sampled and quantized. The calibration signal s(t) is a continuous time (t[s] is the time instant) sine wave with frequency F [Hz], amplitude A [Volts] where A>0, and initial phase .phi. [radians], that is

The frequency F is in the range (0, F.sub.s /2) where F.sub.s [Hz] is the sampling frequency. An ideal S/H circuit with sampling rate F.sub.s results in a discrete time signal

where .omega.=2.pi.F/F.sub.s is the normalized (angular) frequency in (0, .pi.), and k is a running (integer) time index.

Consider a b-bits uniform quantizer. For simplicity, but without loss of generality, let the maximum swing of the ADC be .+-.1. Then, the resolution is ##EQU1## A b-bit quantized signal x(k)=Q.sub.b [s(k)] can be modeled as mathematically represented by (4) and as shown in J. G. Proakis and D. M. Manolakis, Digital Signal Processing-Principles, Algorithms and Applications, Prentice Hall International, Third Edition, 1996, Chapter 9.2, pp. 748-762, which is hereby incorporated by reference in its entirety herein,

where Q.sub.b [.multidot.] denotes a b-bits quantizer and e(k) is white zero mean quantization noise with variance ##EQU2## The model from (4)-(5), describing the quantized output of the ADC, is known to be valid for small quantization steps A and when s(k) traverses several quantization levels between two successive samples.

A quality measure for ADCs is the signal-to-quantization noise ratio (SQNR) defined as the ratio of the signal power P to the power of the quantization noise, that is ##EQU3## where (5) was used in the second equality. For s(k) in (2), it holds that P=A.sup.2 /2. From (6) it is evident that each additional bit increases SQNR by 20 log.sub.10 2.apprxeq.6 dB.

Secondly, in order to reconstruct the calibration signal s(k) from the quantized inputs x(k), an L-th order FIR filter is employed, that is ##EQU4## Filter coefficients ({c.sub.l } from l=0 to L) are sought such that s(k).ident.s(k) for a noise-free sinusoidal input (2) (after that the transient died away). In addition, {C.sub.l } is sought such that the sensitivity against white (quantization) noise is minimized. The sensitivity against noise, or the so called noise gain (NG), is ##EQU5## The optimization problem to be solved is ##EQU6## where s(k) is the sine-wave in (2). This optimization problem was solved in P. Handel, "Predictive digital filtering of sinusoidal signals", IEEE Transactions on Signal Processing, Vol. 46, No. 2, pp. 364-375, 1998, which is hereby incorporated by reference in its entirety herein, and the following result holds true ##EQU7## where ##EQU8## The reconstruction filter may be composed of (7) where the coefficients are determined by (10)-(13) with .omega. there replaced by an estimate .omega.. Obtaining an estimate .omega. from the A/D output x(k) is described below.

Thirdly, the frequency of the calibration signal s(t) is estimated. The filter coefficients (10)-(13) do not depend on the initial phase or the amplitude of the calibration signal s(t); they only depend on .omega.. Several methods may be used to estimate the frequency of a noise corrupted sinusoidal signal. For example, D. C. Rife and R. R. Boorstyn, "Single tone parameter estimation from discrete-time observations", IEEE Transactions on Information Theory, Vol. IT-20, No. 5, pp. 591-598, 1974, which is hereby incorporated by reference in its entirety herein, shows that frequency estimation may be mathematically characterized as ##EQU9## The maximization of (14) may be performed by aid of the fast Fourier transform followed by an iterative minimization. Using the estimate .omega. from (14) in place of .omega. in (10)-(13) completes the reconstruction of s(k) from x(k).

And fourthly, a reconstruction table may be updated using the following exemplary algorithm. The scheme is based on the expression for the optimal, in the sense that E[e(k).sup.2 ] is minimized, reconstruction levels in scalar quantization, as derived by S. P. Lloyd, "Least squares quantization in PCM", IEEE Transactions on Information Theory, Vol. IT-28, pp. 127-135, March 1982, which is hereby incorporated by reference in its entirety herein.

The quantized output, x(k), from the ADC has M=2.sup.b possible different values at time instant k. Let these be

where x.sub.i corresponds to the i-th level of a uniform quantizer. For k.epsilon.{L, L+1, . . . , N-1}, let A.sub.i (m) be the number of times x(k) has been equal to x.sub.i, for L.ltoreq.k.ltoreq.m, and let A.sub.i (L-1)=0. Now the reconstruction table

can be constructed from s(k) as follows: Let s.sub.i be assigned the initial values s.sub.i =x.sub.i, i=0, . . . , M-1. Then, assuming that x(k)=x.sub.i at time instant k.gtoreq.L, update s.sub.i according to ##EQU10## After the data has been processed, and the table has been updated, the operation of the quantizer becomes: The input signal produces a sample s(k) which is quantized to x(k)=x.sub.i, then the quantized value x.sub.i is remapped, using the updated table, to the output s.sub.i.

The formula in (17) calculates an average of estimates for every encountered level in the input signal x(k). An averaging process may be considered as similar to a low pass filter. Thus, for an implementation in which the number of calibration samples is limited (e.g., due to limited calibration time or arithmetic resolution in average calculation, for example), the averaging may be replaced with a low pass filter. Consequently, for a limited number of calibration samples per level, the formula (17) may be approximated with ##EQU11## Because the level of x(k) (which defines the variable "i") acts as the address for the correction table 350 (of FIG. 4C), the calibration functionality as defined by (18) may be implemented with the "(1-C)" multiplier 485, the summer 490, and the "C" multiplier 495.

Referring again to an alternative embodiment of the present invention as illustrated in FIG. 4C, the correction table 350 has a two phase functionality for each sample, one read phase and one write phase. The input signal x(k) with level i acts like an address to the correction table 350 in both phases. In phase one, y(k) gets the value s.sub.i from the correction table 350 and holds it until the end of phase two. This value s.sub.i is multiplied by "C" and summed with the estimate s(k) multiplied by "(1-C)". In phase two, the output of the summation is written to the correction table 350. During functional data conversion, the correction table 350 is still mapping x(k) to a value s.sub.i on the output y(k), but no write operation to the correction table 350 is being performed. If the correction table 350 is not initialized, then there is likely to be more of a transient response from the filtering function, thus demanding more samples than if the correction table 350 is initialized. That is, as long as the input of the filter 455 is not connected to y(k) (i.e., not engaged in the feedback case that may be activated by switch 330B of FIG. 3A), the correction table 350 may be initialized by a longer calibration phase. The frequency estimation and coefficient calculation may also be accomplished during the initialization step alone, especially if the frequency of the reference input signal s(t) to the ADC 310 does not drift outside the passband of the filter 455.

Referring now to FIG. 5, a method in flowchart form for calibrating an ADC in accordance with the present invention is illustrated. Flowchart 500 begins with the application of an analog calibration signal to an input of an ADC (step 510). The ADC produces a digital output based on the analog calibration signal input (step 520). Operating in the digital domain, at least one parameter relating to the calibration signal is estimated based on the digital output of the ADC (step 530). The calibration signal is reconstructed in the digital domain based on the type of waveform of the analog calibration signal and the one or more estimated parameters (step 540). A reconstruction data structure may be created and stored. The digital outputs of the ADC are compared to the values in the reconstruction data structure to determine a correction data structure (step 550). The correction data structure (e.g., a table in a memory) may then be applied to A/D conversion of functional signals (step 560).

The ADC is therefore calibrated by applying the entries in the correction data structure to the digital ADC outputs of a functional signal. Advantageously, the correction data structure may be updated continuously to account for, e.g., temperature drift. The method described in the flowchart 500 may be considered a first coarse tuning phase that may be alternatively followed by a finer tuning of the correction table in a second phase. During the second phase, the data passed through the correction table is input to the calibrator. The second phase may also stand alone for satisfactory calibration as long as the correction table is initialized.

Referring now to FIG. 6, a reference signal reconstruction analysis in graphical form is illustrated. By way of example, reconstruction accuracy of the sampled calibration signal s(k) from quantized data x(k)=Q.sub.b [s(k)], where b=8, 12, and 16, is shown at graph 600. The theoretical (solid lines) and empirical ("+") improvement blmp is shown as a function of the filter length L.

The effective, or improved, number of bits using the prior knowledge that s(k) is sinusoidal is given by ##EQU12## where the second equality is based on the approximation that for long filters (i.e., L>>1) the noise gain is NG.apprxeq.2/L, as can be determined in P. Handel, "Predictive digital filtering of sinusoidal signals", IEEE Transactions on Signal Processing, Vol. 46, No. 2, pp. 364-375, 1998.

The performance of the reconstruction scheme is illustrated at graph 600 with "FILTER LENGTH L" along the abscissa axis and "RESOLUTION (BITS)" along the ordinate axis. The absolute improvement b.sub.IMP in recovering a sinusoidal input with frequency .omega.=0.5 is displayed for b=8, 12, and 16 for different lengths of the filter L. As noted above, in graph 600 solid lines represent theoretical values calculated from (19) and the crosses represent values calculated from simulations. The empirical values are calculated for an ideal uniform quantizer. The frequency is estimated according to (14) and the empirical improvement is measured utilizing sequences of length 10,000 samples. From the graph 600, it may be seen at 610 that for L=100, a quantized b=12 bits sine wave may be reconstructed with b.sub.IMP =14.8 bits resolution.

Referring now to FIG. 7, un-calibrated and calibrated performance characteristics in graphical form are illustrated. Simulation results are provided at un-calibrated graph 700 and calibrated graph 750. In each graph, "FREQUENCY (MHz)" is along the abscissa axis, and "POWER (dBFS)" is along the ordinate axis. The performance of one embodiment of the present invention was evaluated on data from a simulation model describing a 12-bit ADC. The parameters of the calibration signal that was used are: F=11.21826 [MHz], A=0.89 [V] (i.e., a signal level of -1 dBFS), and F.sub.s =50 [MHz]. The length of the sequence is N=82000 (i.e., 1.64 ms).

The output x(k) from the simulation model is characterized by a spurious free dynamic range (SFDR) and a signal to noise and distortion ratio (SNDR). Measured figures from the un-calibrated ADC model are:

In Table 2, the SFDR and SNDR are shown after calibration as a function of the length L of the reconstruction filter. For the calibrated ADC, performance is measured for input frequency F=1.55 MHz and F=11.2 MHz, respectively. From Table 2, improvements up to 30 dB in SFDR and 15 dB in SNDR may be seen.

Continuing now with FIG. 7, performance characteristics or F=1.55 MHz input at -1 dBFS are shown. Specifically, performance characteristics for an un-calibrated (graph 700) and a calibrated (graph 750) 12-bit ADC for single tone at 1.55 MHz are shown. Power spikes are virtually eliminated in the calibrated graph 750. Also, the SNDR is 14 dB higher and the SFDR is 31 dB higher in the calibrated 12-bit ADC.

Thus, a calibration scheme for ADCs is shown and described. Exemplary advantages are illustrated and performance may be evaluated by utilizing an ADC simulation model. Specifically, for a 12-bit ADC, approximate improvements in SFDR of 30 dB and in SNDR of 15 dB have been illustrated.

Although preferred embodiment(s) of the method and system of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the present invention is not limited to the embodiment(s) disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit and scope of the present invention as set forth and defined by the following claims.