Integrated Circuit Analog-to-Digital Converter and Associated Calibration Method and Apparatus

The present invention relates to the field of electronics, and, more particularly, to an analog-to-digital converter and associated calibration method and apparatus.

Analog-to-digital converters are widely used to process electrical signals in many electronic applications. An integrated circuit analog-to-digital converter (ADC) typically accepts an analog input voltage signal and converts the signal into a digital form as the output. A modern digital communication system, such as for a cellular telephone base station, for example, may often require an ADC with a high resolution of greater than 12 bits, a bandwidth greater than 200 MHz, and low power consumption and low distortion for improved overall system performance.

A pipelined ADC includes a series of subconverter stages with each stage including a flash analog-to-digital converter, a digital-to-analog converter (DAC) and an interstage amplifier connecting the DAC to an adjacent stage. The last stage typically includes only a flash ADC. A multi-step ADC may include one or more similar subconverter stages which are sequentially reused in generating the digital output signal.

There are several potential error sources in the subconverter stages of an integrated circuit analog-to-digital converter. These errors include offset, noise, DAC and flash ADC errors, and errors in the interstage gain amplifier. The subconverter flash ADC error may be readily corrected, for example, by the use of digital error correction logic circuits. The kT/C thermal noise error source caused in a sampled-data system may be reduced by proper choice of the sampling capacitor size.

Two dominant error sources in a high resolution pipelined or multi-step ADC are the DAC and the interstage amplifier gain errors. To reduce these two errors, a conventional method has been to measure the components that contribute to the errors, and then calculate and implement the calibration. However, the effectiveness of the calibration is often judged by the linearity of the analog-to-digital converter. Although the correlation between the converter linearity and the error contributing components is theoretically close, it is still only an indirect method to achieve good linearity through component measurement/calibration.

U.S. Pat. No. 4,354,177 to Sloane discloses an apparatus and method for exciting the input of an ADC with exponential signals to generate histograms to determine an amplitude probability distribution of each digital output value. The histograms may be processed in a manner which produces the transfer characteristic of the converter under test which is independent of the dynamic characteristics of the excitation signals, thus eliminating the need for accurate knowledge of the parameter values of the testing circuit.

The DAC of an analog-to-digital converter typically includes a resistor ladder network formed by thin film resistors. These resistors may be laser trimmed to reduce the DAC error. However, the interstage gain error is not as readily determined and corrected. In the past, attempts have been made to trim the capacitors or disconnect small value trimming capacitors associated with a switched capacitor interstage amplifier as disclosed, for example, in an article entitled "A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3- .mu.m CMOS" by Lin et al. appearing in IEEE Journal of Solid-State Circuits, vol. 26, No. 4, April 1991. Unfortunately, trimming capacitors may be extremely difficult in practice, especially to achieve predictable and accurate results. Predictable results are also very difficult when disconnecting small trim capacitors to calibrate the gain.

In view of the foregoing background, it is therefore an object of the present invention to provide an integrated circuit analog-to-digital converter being readily calibrated to have higher accuracy.

It is another object of the present invention to provide a method and apparatus for readily calibrating an analog-to-digital converter to have higher accuracy.

These and other objects, features and advantages of the present invention are provided by an analog-to-digital converter (ADC) integrated circuit which in one embodiment preferably comprises a plurality of subconverter stages with a first subconverter stage including an amplifier having a non-ideal gain, and reference voltage means for generating reference voltages for the subconverter stages, and wherein the reference voltage means preferably comprises adjusted reference voltage output means for providing an adjusted reference voltage to a second subconverter stage to compensate for the non-ideal gain of the amplifier. The ADC may also preferably include output means connected to the subconverter stages for generating a digital output signal.

The first subconverter stage may preferably comprise a switched capacitor amplifier for driving the second subconverter stage. Moreover, the reference voltage means may include original reference voltage output means for providing an original reference voltage to the first subconverter stage, and while the adjusted reference voltage output means provides the adjusted reference voltage to the second subconverter stage to compensate for the non-ideal gain of the switched capacitor amplifier. Accordingly, complicated and difficult capacitor trimming for the amplifier is not needed. Rather, a relatively simple and predictable trimming of thin film resistors, for example, in the reference voltage means may be used to compensate for the non-ideal gain of the amplifier.

The analog-to-digital converter (ADC) may have a non-ideal amplifier gain that results in either one or more missing codes or one or more overlapping codes in the digital output signal. Adjustment of the reference voltage, such as by trimming of the reference voltage resistors readily corrects for either type of error. Moreover, the amplifier gain of subsequent stages may also be adjusted to provide even greater accuracy.

The subconverter stages may each also preferably comprise a flash analog-to-digital converter (DAC), and a digital-to-analog converter connected to the flash analog-to-digital converter. Since error in the DAC is another significant concern, the DAC of the first stage also preferably includes a trimmed thin film resistor network to compensate for such an error.

The ADC also preferably includes output means connected to the subconverter stages for generating a digital output signal. The output means may comprise digital delay and digital error correction means for further correcting the output signal. The ADC may also include timing control means for supplying clock signals to the sampling means and the subconverter stages. In addition, the sampling means of the ADC may also be provided by open loop sampling means for operating at a relatively wide bandwidth.

Another embodiment of the analog-to-digital converter integrated circuit in accordance with the present invention comprises a subconverter stage and timing control means associated therewith for successively operating the subconverter stage a plurality of times. The subconverter stage also preferably comprises an amplifier, such as a switched capacitor amplifier, for driving a second and subsequent operations of the subconverter stage. The amplifier may also have a non-ideal gain that is corrected by reference voltage means for generating reference voltages for each operation of the subconverter stage. The reference voltage means may include adjusted reference voltage output means for providing an adjusted reference voltage for a second operation of the subconverter stage to compensate for the non-ideal gain of the amplifier. Subsequent operations may also have their respective reference voltages adjusted.

A method aspect of the present invention is for enhancing the accuracy of an analog-to-digital converter integrated circuit including a plurality of subconverter stages as described above. More particularly, the method preferably includes the steps of: generating a first output histogram for the ADC; and adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage to the second subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit. The method may also preferably include the step of estimating an amount of adjusting based upon the first output histogram, and wherein the adjusting is carried out based on the estimated amount of needed adjusting.

The subconverter stages may also include a digital-to-analog converter including trimmable resistor network. Accordingly, the method preferably further comprises the step of trimming the resistor network to compensate for an error in the digital-to-analog converter of the first subconverter stage.

Another method aspect according to the invention is for enhancing the accuracy of an analog-to-digital converter integrated circuit of a type comprising a subconverter stage and timing control means for successively operating the subconverter stage a plurality of times. The method preferably includes the steps of: generating a first output histogram for the ADC; and adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage for the second operation of the subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit.

An apparatus in accordance with another aspect of the invention is for enhancing the accuracy of an ADC integrated circuit of a type comprising first and second subconverter stages as described above. The apparatus preferably includes: first histogram means for generating a first output histogram for the ADC; and first adjusting means for adjusting the adjustable reference voltage output means of the ADC, based upon the first output histogram, to provide an adjusted reference voltage to the second subconverter stage to compensate for the non-ideal gain of the amplifier of the first subconverter stage and thereby provide enhanced accuracy for the ADC integrated circuit. The apparatus preferably further comprises estimating means for estimating an amount of adjusting based upon the first output histogram prior to the adjusting. The adjustable reference voltage means may be provided by at least one thin film resistor; and wherein the first adjusting means comprises laser trimming means for trimming the thin film resistor.

The subconverter stages of the ADC may include a digital-to-analog converter including a trimmable resistor network. The apparatus may thus preferably further comprise DAC trimmer means for trimming the resistor network to compensate for an error in the digital-to-analog converter of the first subconverter stage.

Yet another aspect of the present invention is directed to an apparatus for enhancing the accuracy of an analog-to-digital converter integrated circuit of a type comprising a subconverter stage and timing control means for successively operating the subconverter stage a plurality of times. This embodiment of the apparatus preferably comprises: first histogram means for generating a first output histogram for the ADC; and first adjusting means for adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage for the second operation of the subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit.

FIG. 1 is a schematic diagram of a first embodiment of an analog-to-digital converter in accordance with the present invention.

FIG. 2 is a schematic diagram of a second embodiment of an analog-to-digital converter in accordance with the present invention.

FIG. 3 is a schematic diagram of a third embodiment of an analog-to-digital converter in accordance with the present invention.

FIG. 4 is a flow chart of a method in accordance with the present invention.

FIG. 5 is a part of a transfer curve and corresponding histogram of an analog-to-digital converter having a missing code and before any trimming of the reference voltage generator in accordance with the present invention.

FIG. 6 is a part of a transfer curve and corresponding histogram of an analog-to-digital converter as in FIG. 5 and after a first trimming of the reference voltage generator in accordance with the present invention.

FIG. 7 is a part of a transfer curve and corresponding histogram of an analog-to-digital converter as in FIG. 6 and after a final trimming of the reference voltage generator in accordance with the present invention.

FIG. 8 is a graph of the transfer curve of the analog-to-digital converter during a calibration in accordance with the present invention.

FIG. 9 is a graph of the INL curve of the analog-to-digital converter during a calibration in accordance with the present invention.

FIG. 10 is a part of a transfer curve and corresponding histogram of an analog-to-digital converter having an overlapping code and before any trimming of the reference voltage generator in accordance with the present invention.

FIG. 11 is a part of a transfer curve and corresponding histogram of an analog-to-digital converter as in FIG. 10 and after a first trimming of the reference voltage generator in accordance with the present invention.

FIG. 12 is schematic diagram of an apparatus for trimming an analog-to-digital converter in accordance with the present invention.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

Referring now initially to FIG. 1, an embodiment of an analog-to-digital converter 20 in accordance with the invention is described. The illustrated ADC 20 includes a plurality of subconverter stages 21, 22 and 24 connected together in a pipelined configuration as would also be readily understood by those skilled in the art. The outputs of the subconverter stages 21, 22 and 24 are coupled to a delay and digital error correction circuit 35 as would be readily understood by those skilled in the art. The digital output of the illustrated ADC 20 is produced by the delay and digital error correction circuit 35. Other output means are also contemplated by the present invention for providing the digital output signal from the plurality of subconverter stages as would be readily understood by those skilled in the art.

The ADC 20 also includes the illustrated sample and hold circuit 26 for providing a relatively large input bandwidth. The sample and hold circuit 26 includes the illustrated amplifier 27 and the associated capacitors C and switches S driven by signals from the illustrated clock 30 as would be readily understood by those skilled in the art.

The illustrated reference voltage generator 36 provides reference voltages for each of the subconverter stages 21, 22 and 24. In particular, each of the subconverter stages 21, 22 and 24 may preferably include a flash analog-to-digital converter 40 as shown with reference to the detailed schematic portion of the first subconverter stage 21. As would be readily understood by those skilled in the art, the flash ADC 40 may preferably be provided by a string of thin film resistors producing inputs to a plurality of comparators driving associated logic decoding circuitry. A reference voltage Vref1 feeds the string of resistors for the flash ADC 40 as would also be understood by those skilled in the art.

The output of the flash ADC 40 is connected to a digital-to-analog converter 42 and is also connected to the illustrated delay and digital error correction circuit 35. The digital-to-analog converter is connected to a switched capacitor amplifier 44 as illustrated. The switched capacitor amplifier 44 serves as an interstage amplifier and drives the second subconverter stage 22. The switched capacitor amplifier 44 includes the illustrated amplifier 45, capacitors C and various switches S driven by clock signals. In particular, the capacitor C(G.sub.o) indicates that this capacitor is a factor in determining the original gain G.sub.o. of the amplifier 44 as discussed in greater detail below.

The present invention addresses two dominant error sources in a high resolution pipelined or multi-step ADC. These errors are from the DAC 42 and the interstage gain amplifier 44. In the past, an attempt has been made to trim the capacitors or disconnect small value trimming capacitors associated with a switched capacitor amplifier to correct of non-ideal gain as disclosed, for example, in the article entitled "A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3- .mu.m CMOS" by Lin et al. appearing in IEEE Journal of Solid-State Circuits, vol. 26, No. 4, April 1991. Unfortunately, trimming capacitors may be difficult in practice to achieve predictable and accurate results. Disconnecting small capacitors may also produce unpredictable changes.

Another conventional approach has been to measure the components that contribute to the errors, and then to calculate and implement the calibration. However, the effectiveness of the calibration is often judged by the linearity of the converter. Although the correlation between the converter linearity and the error contributing component is theoretically close, it is still an indirect method to achieve good linearity through component measurement/calibration.

One aspect of the present invention is a correction or calibration technique based on the measurement of the ADC histogram, which has a one-to-one correspondence to the ADC linearity. It bypasses the component measurement and achieves good ADC linearity through direct component calibration based on histogram measurements.

It has been shown that in an n-bit ADC with an m-bit first stage and a normalized reference voltage of 1V, the residual voltage output from the interstage gain amplifier, digitized by the remainder of the ADC with an rV reference, contains the two error terms ##EQU1##

As a first step, the two error sources may be separated and treated independently. With the DAC error corrected, the interstage gain error appears in the converter transfer curve with a constant discontinuity, J, between two adjacent code segments, where ##EQU2## which results in missing codes (DNL=-1) or overlapped codes (DNL=1). The DNL can be returned to the normal value of 0 by reducing the last equation to 0, which implies that G=G.sub.0 r and where G is the actual gain and G.sub.o is the ideal gain. The calibration can therefore be done by monitoring the DNL changes. Conventional methods have been to trim/calibrate the gain G=G.sub.0 by forcing r=1. However, it can also be achieved by calibrating r=G/G.sub.0 in accordance with the present invention.

The above concept can be implemented in several different ways. For example, an ADC 20 may use a standard 4-stage (4 bits/stage) pipelined architecture as illustrated. The first subconverter stage 21 may include a resistor ladder DAC 42, a 4-bit flash ADC 40, and an interstage gain amplifier 44 with G.sub.0 =8. The DAC can be background-calibrated to achieve the required 12-b accuracy, for example, and as would be readily understood by those skilled in the art. However, since the fabrication process offers thin-film resistors, a conventional laser-trim method may preferably be used.

According to one important aspect of the present invention, instead of trimming/calibrating the capacitors of the switched capacitor amplifier 44 for an exact gain of 8, the reference voltages to the remaining stages are calibrated to match the gain by monitoring the histogram of the ADC 20 output. The changes to the reference voltages may be readily accomplished through laser-trimmed resistor ladders in the reference voltage generator 36. Those of skill in the art will readily appreciate that other techniques for adjusting the reference voltages are also contemplated by the present invention, such as including, for example, disconnecting fuse links, using a digital-to-analog converter, etc.

The illustrated ADC 20 further includes a reference voltage generator 36 for generating reference voltages Vref1, Vref2 and Vrefn for the subconverter stages. The reference voltage generator 36 illustratively includes a trimmed reference voltage output circuit 37 for providing a trimmed reference voltage Vref2 to a second subconverter stage 22 to compensate for a non-ideal gain of the amplifier. The trimmed reference voltage output circuit 37 may include a thin film resistor network being laser trimmed as would be readily understood by those skilled in the art. Accordingly, complicated and difficult capacitor trimming for the amplifier 44 is not needed. Rather, a relatively simple and predictable trimming of a thin film resistor network 37 in the reference voltage generator 36 may be used to compensate for the non-ideal gain of the amplifier. The other reference voltages Vref1 and Vrefn may be their original values since reference voltage trimming is typically only needed for the second stage. Alternatively, the reference voltages to a third and/or subsequent subconverter stages may also be similarly individually calibrated as would be readily understood by those skilled in the art. Yet another variation may provide the adjusted reference voltage for the second stage to the downstream stages.

Turning now additionally to FIG. 2, another embodiment of a multi-step ADC 50 in accordance with the invention is described. In this embodiment, the subconverter stage 51 is repetitively used by operation of the timing and control circuit 53 and the associated switching means 54 as would be readily appreciated by those skilled in the art. The other elements are similar to those described above and need no further explanation herein. In this embodiment, the reference voltage provided for the second step of the conversion Vref2 is adjusted by the illustrated trimmed resistor reference 37 to account for the non-ideal amplifier gain. As noted above other equivalent circuits may also be used to adjust the reference voltages to correct for the non-ideal amplifier gain.

A three subconverter stage multi-step ADC 60 is understood with reference to FIG. 3. In this embodiment the third subconverter stage 61 includes only the flash ADC. Those of skill in the art will readily appreciate operation of this analog-to-digital converter 60 as the other circuit elements are similar to those described above. Those of skill in the art will recognize that the pipelined embodiments of an ADC may be more efficient than the multi-step implementations, since there is typically less idle time for the pipelined configuration.

The method and apparatus aspects of the invention are further understood with additional reference to FIGS. 4 through 12. As shown in the flow chart of FIG. 4, after the start Block 70, the resistor network for the DAC is driven and trimmed at Block 74. The DAC resistors may be isolated and a current forced therethrough to establish a voltage across the resistor ladder. The drive current is preferably a constant fixed value. The tap voltages can be calculated and the resistors trimmed, if necessary, to correct any errors exceeding tolerances. If the DAC is within tolerance at Block 76, the method proceeds to consider and correct for a non-ideal gain of the interstage amplifier.

At Block 78 the ADC is operated to generate an initial histogram as would be readily understood by those skilled in the art. The initial histogram preferably may indicate missing codes as shown, for example, in the histogram of FIG. 5 or may have overlapping codes as in FIG. 10. If the histogram has a missing or overlapping code as determined at Block 80, an estimate is made of the needed trimming (Block 82). A formula to estimate the amount of adjustment that has to be done on the reference voltage is given by: ##EQU3## where Vr=reference voltage used in generating the first histogram

D=number of missing or overlap codes

D>0 for missing codes

D<0 for overlap codes

N=ADC resolution in bits, and

M=first subconverter resolution in bits assuming 1-bit overlap for redundancy.

The trimming is accomplished by laser trimming at Block 84. The histogram is again generated at Block 78. If the laser trimming has provided the needed correction as determined at Block 80 the process is complete (Block 90). If the error has been only partially corrected, for example, the estimating and trimming steps may be repeated as would be readily appreciated by those skilled in the art. If the ADC is otherwise within tolerance at Block 92 it is accepted (Block 93), and if not, it is rejected (Block 94) and the process ends (Block 90).

Turning briefly to FIGS. 5, 6 and 7 the progression of a two step adjustment for missing codes is understood. FIG. 5 illustrates a relatively wide gap indicating several missing codes; FIG. 6 illustrates a partial adjustment where the number of missing codes is reduced; and FIG. 7 illustrates the fully adjusted or corrected ADC output. Similarly, FIG. 10 illustrates the case of several overlapping codes prior to any correction, and FIG. 11 illustrates a partial correction for overlapping codes. The full correction of overlapping codes produces an output as in FIG. 7 as would be readily understood by those skilled in the art.

Referring now briefly to FIG. 8, the illustrated transfer curve has an abrupt step or jump, the size of which is indicative of the number of missing codes. The corresponding INL curve of FIG. 9 also shows the step and wherein the step size also corresponds to the number of missing codes.

The apparatus 100 according to another aspect of the present invention is explained with particular reference to the schematic diagram of FIG. 12. The apparatus 100 includes a conventional laser trimmer 105 that may be used to trim thin film resistors for one or both of the schematically illustrated DAC resistor network 101 and the voltage reference resistors 102 of the ADC 20. The laser trimmer 105 is operated by the schematically illustrated controller 116.

In particular, the controller 116 illustratively includes a test input driver circuit 108 that may provide the desired input for generating the output histogram for correcting for a non-ideal interstage amplifier gain as discussed in greater detail above. These input signals may take the form of sinusoidal or other signals with a known amplitude probability distribution function as would be readily understood by those skilled in the art. The test input driver circuit 108 may also supply the current for calibration of the DAC resistor network 101 as also described above.

The controller 116 also includes an output histogram generator circuit 110 for generating histogram data for the ADC 20 being calibrated. The output histogram generator 110 cooperates with the trimming estimator 112 which estimates an amount of voltage reference resistor trimming to correct for the non-ideal gain of the interstage amplifier as described above. The trimming estimator 112, in turn, cooperates with the laser control circuit 114 to drive the laser trimmer 105. Those of skill in the art will readily appreciate that the apparatus 100 could also adjust the desired reference voltages by disconnecting fuse links and other methods, for example as also discussed herein. The histogram generation may be performed continuously during the adjusting process, or may be performed after each adjustment or trimming as would be readily understood by those skilled in the art.

A low power, wide input bandwidth, low distortion ADC is provided by the present invention. In addition, the invention also provides a method and apparatus for making the ADC. Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.