US 5,909,427 AGrant
Redundant Switch System and Method of Operation
Issue Date:1999-06-01
•38 Claims
•3 Drawing Sheets
Abstract
A redundant switch (50) is provided for performing a switch fabric test. The redundant switch (50) includes a foreground switch fabric controller (24) for controlling a foreground switch fabric (26), a background switch fabric controller (124) for controlling a background switch fabric (126), and a first I/O module (14) in communication with the foreground switch fabric controller (24). The first I/O module (14) sends, at the request of the foreground switch fabric controller (24), a test cell to an input of the background switch fabric (126) and receives the test cell from a corresponding output of the background switch fabric (126). The first I/O module (14) determines if an error occurred and provides an error signal to the foreground switch fabric controller (24) in response if an error occurred. The foreground switch fabric controller (24) may log the error signal or enable an alarm or indicator in response.
Metadata
Assignees
- Fujitsu Network Communications, Inc.
- Fujitsu Limited
Inventors
- Thomas A. Manning
- Stephen A. Caldara
- Stephen A. Hauser
Application Information
Application Number:US 683793&
Filing Date:1996-07-18
Priority Date:1996-07-18
Art Unit:271
Classifications
IPC:
H04J 314H04L 1256
Field of Search:
370395216;218;219;220;244;242;250;386;387;388;389;395181;182.01;182.02;185.01
Patent Drawings (3 sheets)
Description
Technical Field of the Invention
The present invention relates generally to communication switching systems, and more specifically to a redundant switch system and method of operation.
Background of the Invention
Usage and demand for modern communication systems continues to soar as users demand more and more sophisticated communication services and bandwidth while relying on the instant availability of these communication systems. Increasingly, communication systems are used to provide all types of information including voice, video, and data.
Modern communication systems include a collection of components, such as digital switching systems, that communicate, manipulate, and process information in a variety of ways. Digital switching systems are integral components of today's modern communication systems. The availability of communication systems is directly related to the availability of the digital switching systems used in these communication systems. As reliance on communication systems continues to increase, the availability of the digital switching systems used in these communications systems becomes critically important.
Problems arise when attempting to increase the availability of a digital switching system. The digital switching system may provide redundant capability so that if a circuit or module of the digital switching system fails, a backup circuit or module may be used. Problems arise when transitioning from a system or circuit operating in the foreground to a system or circuit operating in the background. Performance suffers greatly when the transition causes delays, interruptions in service, and errors. Often, when a circuit or module fails, the backup circuit is not properly initialized or operating correctly resulting in data loss or complete system failure. Also, overall system performance suffers when system resources are consumed attempting to verify that a backup circuit or module is operating correctly so that the backup circuit or module may be relied upon in the event of a failure.
Summary of the Invention
In accordance with the present invention, a redundant switch system and method of operation are provided which substantially eliminate or reduce the disadvantages and problems associated with increasing the availability and reliability of a digital switching system. The present invention provides a redundant switch system and ensures that the background switch is available and operating correctly while minimizing or eliminating any adverse effects on actual switching operation.
According to an embodiment of the present invention, a redundant switch system is provided that includes a first switch control module, a second switch control module, and a first I/O module. The first switch control module includes a first switch fabric operating in the foreground under the control of a first switch fabric controller. The first switch fabric receives communication signals from an input port and provides the communication signals to at least one of its output ports. The first switch fabric controller may initiate a switch fabric test. The second switch control module includes a second switch fabric operating in the background and under the control of a second switch fabric controller. The second switch fabric receives communication signals at an input port and provides the communication signals to at least one of its output ports. The first I/O module exchanges communication signals with the first switch fabric and the second switch fabric. The I/O module provides a test communication signal to an input of both switch fabrics in response to the initiation of a switch fabric test by the first switch fabric controller. The I/O module then receives the test communication signal from an output of the second switch fabric and generates or provides an error signal if an error is detected in the received test communication signal.
The redundant switch and method of operation provides various technical advantages. A technical advantage of the present invention includes increased switch availability. Another technical advantage includes the ability to systematically and routinely check the operation of a background switch during actual switch operation to ensure that the background switch is operating correctly while minimizing or eliminating any adverse effect on overall switch performance. Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
Brief Description of the Drawings
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts, in which:
FIG. 1 is an overview block diagram illustrating a control and a data interconnection between a first I/O module and a foreground switch control module;
FIG. 2 is a block diagram illustrating a redundant switch system including the data interconnection between the first I/O module and the foreground switch control module and a background switch control module; and
FIG. 3 is a flowchart illustrating a method for operating the redundant switch system.
Detailed Description of the Invention
FIG. 1 is an overview block diagram of a control and a data interconnection between a first I/O module 14 and a foreground switch control module 10 of a digital communication switch. Also shown in FIG. 1 are a plurality of additional I/O modules represented by a second I/O module 16 and an n.sup.th I/O module 18. Each of the plurality of I/O modules interconnect with foreground switch control module 10 in the same manner that first I/O module 14 couples to foreground switch control module 10. A background switch control module 12 is also provided which interconnects to each of the plurality of I/O modules in the same manner that foreground switch control module 10 interconnects to each of these plurality of I/O modules. Background switch control module 12 operates in the background and serves as a redundant module in the event that foreground switch control module 10 fails or is taken out of service.
In operation, the plurality of I/O modules receive information, such as voice, video, and data, from a corresponding communications link using a variety of access technologies. Each I/O module provide this information to the inputs of a foreground switch fabric 26 of foreground switch control module 10 and background switch control module 12. Foreground switch control module 10, using a foreground switch fabric controller 24 and any available switching scheme, controls the switching of foreground switch fabric 26 so that the communication information provided by each I/O module is properly routed or mapped to the appropriate destination I/O module. Foreground switch control module 10 receives control information from the various I/O modules to assist with carrying out the switching scheme.
First I/O module 14 is representative of the plurality of I/O modules and includes a line interface 39 and a cell flow processor 38. In one embodiment, line interface 39 includes a connectivity engine, a network interworking, and a physical interface to exchange information with a particular type of access technology provided by the communication link or network that is coupled to line interface 39. This coupling is not shown in FIG. 1.
Each of the plurality of I/O modules occupies a particular port in the digital communication switch. Each of the plurality of I/O modules are similar, except for the line interface which allows a particular I/O module to interface with a particular access technology. The access technology may include virtually any communications format or protocol such as asynchronous transfer mode (ATM), cell relay, frame relay, circuit emulation, LAN emulation, internetworking, and the like, and using virtually any physical medium or transmission hierarchy. Line interface 39 may support any suitable communication technique, whether connection-based or connectionless. Thus, first I/O module 14 may interface, through line interface 39, with a communication link that supports a particular access technology, while the line interfaces of other I/O modules may support different access technologies. In this manner, information may be received by an I/O module in a particular format, converted to a common or core cell format used in foreground switch control module 10 by the line interface, routed to a destination I/O module through foreground switch control module 10, and finally provided to the communication link coupled to the destination I/o module that uses a completely different access technology than the source communication link.
Cell flow processor 38 provides an interface between line interface 39 and foreground switch control module 10. Cell flow processor 38 interconnects with foreground switch control module 10 using a first I/O serial data signal 40 and a first I/O serial control signal 42. In one embodiment, these may be provided as eleven unidirectional lines. The reference to "lines" may include conductors, couplings, connectors, matings, connections, and the like. Cell flow processor 38 also provides these same signals to background switch control module 12 through similar interconnections. Unlike line interface 39, which may vary from one I/O module to another, cell flow processor 38 has the same structure and performs the same function in all I/O modules. In a particular embodiment, cell flow processor 38 implements a core cell transfer function using ATM with virtual channel (VC) buffer and bandwidth control.
Cell flow processor 38 includes a to-switch port processor (TSPP) 28, a from-switch port processor (FSPP) 30, a serializer 32, and a deserializer 34. In a particular implementation, TSPP 28 and FSPP 30 may be implemented using an application specific integrated circuit (ASIC). Cell flow processor 38 uses TSPP 28 to receive information from line interface 39, to process the information, to provide communication signals to and from foreground switch control module 10, which exchange control information with foreground switch control module 10. TSPP 28 controls access to input buffers and to the bandwidth of foreground switch fabric controller 24 on a per connection basis. TSPP 28 requests and receives grants for switch bandwidth from foreground switch fabric controller 24. TSPP 28 also receives flow control information. FSPP 30 may also be an ASIC. The FSPP 30 controls access to output buffers and linked bandwidth on a per connection basis. FSPP 30 also sends and receives flow control information.
Serializer 32 receives the information from TSPP 28 in parallel format and converts the information to serial format and provides the information as either first I/O serial data signal 40. TSPP 28 also receives control information from foreground switch fabric controller 24. FSPP 30 receives information from foreground switch control module 10 through first I/O serial data signal 40 and first I/O serial control signal 42. Deserializer 34 receives these data signals where they are converted from serial format to parallel format and then provided to FSPP 30. TSPP 28 and FSPP 30 are in communication with one another.
In one embodiment, foreground switch control module 10 and background switch control module 12 are essentially interchangeable modules with one operating in the foreground and the other operating in the background to provide a redundant system to increase overall system availability. Thus, the following discussion of foreground switch control module 10 may apply to background switch control module 12.
Foreground switch control module 10 includes a port processor 20, a foreground switch fabric controller 24, and a foreground switch fabric 26 having input ports and output ports corresponding to each of the plurality of I/O modules. Port processor 20 is used to communicate with the TSPPs 28 and FSPPs 30 on the I/O modules in the system.
Foreground switch fabric controller 24 controls the operation of foreground switch fabric 26 by determining how the data signals provided from the plurality of I/O modules, such as first I/O serial data signal 40, are interconnected (switched) by foreground switch fabric 26. Foreground switch fabric controller 24 accumulates and arbitrates transfer requests from each I/O module. Foreground switch fabric controller 24 may also maintain and access a topology state for each connection. This topology information controls the fan-in and the fan-out of multipoint connections. In one embodiment, foreground switch fabric controller 24 may include a bandwidth arbiter (BA) ASIC to decide which I/O modules or ports have access to foreground switch fabric 26, and a multipoint topology controller (MTC) ASIC to maintain and access topology states for each connection in the digital communication switch. Foreground switch fabric controller 24 receives control signals from each of the I/O modules, such as first I/O serial control signal 42 from first I/O module 14. Foreground switch fabric controller 24 uses this information to determine which data signal from all of the I/O modules should be provided at a particular input of foreground switch fabric 26 and routed to a particular output of foreground switch fabric 26.
Once foreground switch fabric controller 24 determines which connection should be made within foreground switch fabric 26, a control signal is provided to the TSPP of the appropriate I/O module so that the correct data signal may be provided to the input port of foreground switch fabric 26 corresponding to that I/O module. For example, first I/O module 14, through TSPP 28, provides first I/O serial control signal 42 to foreground switch fabric controller 24 indicating a request for communication from first I/O module 14. Eventually, foreground switch fabric controller 24 grants the request and communicates the grant to TSPP 28 through first I/O serial control signal 42. At this time, the cell may be transferred from TSPP 28 through first I/O serial data signal 40 to foreground switch fabric 26. Foreground switch fabric 26, under the control of foreground switch fabric controller 24, maps or switches first I/O serial data signal 40 to the designated output port for receipt by the FSPP of the receiving I/O module. The data signals provided from the various I/O modules, such as first I/O serial data signal 40, may be provided as communication cells having a header portion and a data portion. These communication cells may be provided in asynchronous transfer mode (ATM) format, or the like. The information may then be processed by the line interface of the receiving I/O module and provided in the communication format of the interfacing access technology.
Background switch control module 12 receives the same signals from the I/O modules, such as I/O first module 14, that are provided to foreground switch control module 10. Background switch control module 12 operates in the same manner as foreground switch control module 10. In the event that foreground switch control module 10 fails or is taken out of service, background switch control module 12 may operate in the foreground with minimal disruption of service. In one embodiment, port processor 20 switches between foreground control module 10 and background control module 12 in response to external control. However, before taking foreground switch control module 10 out of service or before foreground switch control module 10 fails, it is important to ensure that background switch control module 12 is operating correctly so that service will not be disrupted.
FIG. 2 is a block diagram illustrating a redundant switch system, including the data interconnection with first I/O module 14. As discussed above, when first I/O module 14 provides information to foreground switch control module 10, the information is correspondingly also provided to background switch control module 12. Background switch control module 12 includes the same or similar components as that provided in foreground switch control module 10. These same or similar components may include a background switch fabric controller 124, and a background switch fabric 126 as shown in FIG. 2. Before both foreground switch control module 10 and background switch control module 12 may both receive the same information, background switch fabric controller 124 and foreground switch fabric controller 24 must be synchronized so that these controllers stay in lock-step. This may include identically configuring control registers, and updating tables and entries. When a communication cell is provided from TSPP 28, it is provided to serializer 32 in parallel format and converted to serial format and provided to processor interface 36. In one embodiment, processor interface 36 then provides the communication cell to background switch fabric 126 through a background first I/O serial data signal 41. This same communication cell is also provided to foreground switch fabric 26 through first I/O serial data signal 40. At this time, both background switch fabric 126 and foreground switch fabric 26, under the control of their respective switch fabric controllers, map or switch the communication cell to a designated output port where the cell may then be provided to that port's I/O module for further processing. In normal operation, first I/O serial data signal 40, as provided at the output of foreground switch fabric 26, is a communication cell that is provided to the designated I/O module. However, if foreground switch control module 10 fails or is taken out of service, then background first I/O serial data signal 41, as provided at the output of background switch fabric 126, may be provided to the designated I/O module.
It is critical that the components of background switch control module 12 are operating correctly so that in the event of a failure, background switch control module 12 may be relied upon for continued operation with minimal interruption of service. Thus, it is desirous to routinely verify the operation of background switch control module 12 to ensure that it is operating correctly while minimizing or eliminating any adverse effect on overall system performance caused by the verification of the background operation. The present invention accomplishes all of this as illustrated below.
First, foreground switch fabric controller 24 determines a point in time in which unallocated bandwidth is provided in foreground switch fabric 26. During this period or slot of time, foreground switch fabric 26 may map or switch from an input port to an output port without adversely affecting the transfer of any other communication cell. In one embodiment, unallocated bandwidth may be normally provided for every input and output port of foreground switch fabric 26 once every 5 milliseconds.
During this time of unallocated bandwidth, a test cell may be sent from the TSPP of each I/O module to the corresponding input port of both the foreground switch fabric 26 and the background switch fabric 126. Both switch fabrics then switch the test cell to the output port corresponding to the I/O module that sent the test cell.
The FSPP of each I/O module then receives the same test cell from the background switch fabric 126 that was originally provided from the TSPP. The FSPP then performs error checking to determine whether an error occurred in the transmission through background switch fabric 126. This may be accomplished using parity checking or cyclic redundancy check (CRC) techniques to determine if an error occurred. CRC is an error checking procedure commonly used in data communications in which each transmitted bit is applied to a register containing a series of XOR gates, thereby solving a polynomial equation. The result of this operation is appended to the test cell and compared to an identical operation performed on the received test cell. If the values match, no error was detected. There are several standard CRC checks, including CRC-6, CRC-16, CRC-32 which is used in the IEEE 802 LAN standards.
In operation, foreground switch fabric controller 24 detects unused bandwidth in foreground switch fabric 26 and enables a switch fabric test to test the operation of background switch control module 12. At this time, foreground switch fabric controller 24 provides a control signal to the FSPP of each I/O module or to a designated I/O module indicating that a switch fabric test is to be performed. For example, FSPP 30 of first I/O module 14 receives a signal from foreground switch fabric controller 24 indicating that a switch fabric test is to be performed. In response, FSPP 30 instructs TSPP 28 to send a test cell. The test cell is provided to serializer 32 in parallel format and converted to serial format and then provided to processor interface 36. Processor interface 36 provides the test cell in serial format to background switch fabric 126 as background first I/O serial data signal 41. Background switch fabric 126 receives background first I/O serial data signal 41 and maps or switches the signal from a first input port to a corresponding first output port, under the control of background switch fabric controller 124. Background switch fabric 126 then provides the signal to processor interface 36. This signal is also referenced in FIG. 2 as background first I/O serial data signal 41. Processor interface 36 then provides the signal containing the test cell to Deserializer 34 where the signal is converted from serial format to parallel format and provided to FSPP 30.
FSPP 30 performs CRC error detection and determines whether or not an error has occurred. If an error has occurred, FSPP 30 sends a control signal to foreground switch fabric controller 24 where the error is stored or logged. In one embodiment, if an error occurs, an alarm or indicator may be enabled as a result of the error condition. After a predefined number of CRC errors, foreground switch fabric controller 24 and, in one embodiment, background switch fabric controller 124, interrupts foreground switch control module 10 and places background switch control module 12 as the primary or foreground control module.
During the time in which the switch fabric test is enabled, deserializer 34 acts as a switch fabric selector or multiplexer and provides the output of background switch fabric 126 to deserializer 34 for error processing by FSPP 30.
The switch fabric test has been described, and shown in FIG. 2, with respect to first I/O module 14. In one embodiment, every 5 milliseconds every I/O module of the digital communication switch may send a test cell through background switch fabric 126 and then back to the FSPP of the sending I/O module for error checking. The present invention provides technical advantages by testing the operation of background switch fabric 126 and background switch fabric controller 124 without adversely affecting the performance of the digital communication switch.
FIG. 3 is a flow chart illustrating a method for operating redundant switch system 50. The method begins at step 200 and proceeds to step 202 where the foreground switch fabric controller detects unallocated switch bandwidth. This may be accomplished by examining a switch allocation table and locating unallocated slots in the switch allocation table. The method proceeds next to step 204 where a switch fabric test is enabled at the point in time where unallocated switch bandwidth may be used.
Proceeding next to step 206, the foreground switch fabric controller sends a control signal to the FSPPs of each I/O module. The control signal indicates that a switch fabric test has been enabled and that a test cell should be sent from the TSPPs of each I/O module to the background switch fabric. The method proceeds next to step 208 where the FSPPs' signal their TSPP to send the test cell. The test cell may be provided in memory as part of the TSPP and may be shorter than a normal cell to prevent any clock skewing due to the high speed nature of the serial interface between the I/O modules and the switch control modules. The additional signaling needed to implement the switch fabric test may require that the test cell be one-half of a normal cell so that timing errors are not encountered.
Proceeding next to step 210, the TSPPs send the test cell to both switch fabrics where the test cell is provided at each I/O module's input port. The method then proceeds to step 212 where both switch fabrics transfer the test cell from each I/O module's input port to each I/O module's corresponding output port. The corresponding output port is the output port that corresponds to the I/O module that sent the test cell. The test cell is then provided from the background switch fabric to the FSPP of the I/O module. Deserializer 34, acting as a switch fabric selector, provides the output of the background switch fabric to the FSPP instead of the output of the foreground switch fabric.
Next, the method proceeds to step 214 where the FSPPs receive the test cell and perform error checking, such as CRC error checking, to determine if an error has occurred. If an error has occurred, the FSPP may provide a signal to the foreground switch fabric controller where the error is logged or stored in an error table. The method proceeds next to step 216 where the errors are analyzed and an appropriate action is taken. For example, after a predefined number of CRC errors have occurred, the background switch control module 12 may be transitioned from operating in the background to operating in the foreground. Optionally, an alarm or indicator may be enabled as a result of the errors. The method then concludes at step 218.
Thus, it is apparent that there has been provided, in accordance with the present invention, a redundant switch system and method of operation that satisfies the advantages set forth above. The present invention improves overall system availability while eliminating or minimizing any adverse effect on overall system operation.
Although the preferred embodiment of the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations may be made to the described embodiment without departing from the spirit and scope of the present invention. The direct connections illustrated herein could be altered by one skilled in the art such that two devices are merely coupled to one another through an intermediate device or devices without being directly connected while still achieving the desired results demonstrated by the present invention. Other examples of changes, substitutions, and alterations are readily ascertainable by one skilled in the art and could be made without departing from the spirit and scope of the present invention as defined by the following claims.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A redundant switch system for use in a digital communication switch, the redundant switch system comprising: a first switch control module having a first switch fabric and a first switch fabric controller, the first switch fabric having a plurality of input ports and a plurality of output ports and operating in the foreground under the control of the first switch fabric controller, the first switch fabric operable to contemporaneously receive communication signals at all of the plurality of input ports and to provide the communication signals to at least one of the plurality of output ports, the first switch fabric controller operable to initiate a switch fabric test; a second switch control module having a second switch fabric and a second switch fabric controller, the second switch fabric having a plurality of input ports and a plurality of output ports and operating in the background under the control of the second switch fabric controller, the second switch fabric operable to contemporaneously receive communication signals at all of the plurality of input ports and to provide the communication signals to at least one of the plurality of output ports; and a first I/O module in communication with the first switch fabric controller, the first I/O module operable to exchange communication signals with the first switch fabric and the second switch fabric, provide a test communication signal to one of the plurality of input ports of the second switch fabric in response to the initiation of the switch fabric test by the first switch fabric controller, receive the test communication signal from one of the plurality of output ports of the second switch fabric, and generate an error signal if an error occurs when providing and receiving the test communication signal.
2. The redundant switch system of claim 1, wherein the first I/O module includes a cell flow processor operable to process asynchronous transfer mode cells.
3. The redundant switch system of claim 1, wherein the first switch fabric controller initiates the switch fabric test so that the switch fabric test occurs during a time when the bandwidth of the first switch fabric is unallocated.
4. The redundant switch system of claim 1, wherein the first I/O module is operable to provide the error signal to at least the first switch fabric controller.
5. The redundant switch system of claim 1, wherein the first switch fabric controller includes a bandwidth arbiter and a memory, the bandwidth arbiter operable to control at least the first switch fabric and determine when unallocated bandwidth is available, the memory operable to store the error signal.
6. The redundant switch system of claim 1, wherein the test communication signal is a test communication cell having a pseudo asynchronous transfer mode cell format.
7. The redundant switch system of claim 6, wherein the test communication cell is smaller in size than a normal asynchronous transfer mode cell.
8. The redundant switch system of claim 1, wherein the test communication signal is provided in an asynchronous transfer mode cell format.
9. The redundant switch system of claim 1, wherein the first I/O module generates an error signal if the test communication signal provided to one of the plurality of input ports of the second switch fabric differs from the test communication signal received from one of the plurality of output ports of the second switch fabric.
10. The redundant switch system of claim 9, wherein the first I/O module performs a cyclic redundancy check to determine if an error occurred.
11. The redundant switch system of claim 9, wherein the first I/O module generates an error signal if the test communication signal is not received by the first I/O module.
12. The redundant switch system of claim 9, wherein the first I/O module performs a checksum to determine if an error occurred.
13. The redundant switch system of claim 1, wherein the switch fabric test can be disabled.
14. The redundant switch system of claim 1, wherein the first switch fabric and the second switch fabric are emitter coupled logic cross-point devices.
15. The redundant switch system of claim 1, wherein the test communication signal is a digital test communication cell that includes a header portion and a data portion.
16. The redundant switch system of claim 3, wherein the first switch fabric controller determines the time when the bandwidth of the first switch fabric is unallocated by using a switch allocation table and locating unused switch allocation table slots.
17. The redundant switch system of claim 3, wherein the digital communication switch is a distributed asynchronous transfer mode switch.
18. The redundant switch system of claim 3, wherein the first I/O module includes a cell flow processor having a to-switch port processor and a from-switch port processor that each include a memory.
19. The redundant switch system of claim 18, wherein the from-switch port processor determines whether an error has occurred when receiving the test communication signal.
20. The redundant switch system of claim 19, wherein the cell flow processor further includes a serializer operable to provide the test communication signal to the second switch fabric, and a deserializer operable to receive the test communication signal from the second switch fabric.
21. The redundant switch system of claim 20, wherein the first I/O module includes a line interface for exchanging communication signals between the cell flow processor and a communication link, the line interface operable to convert a communication signal received from the communication link into a format compatible with the redundant switch system and to convert a communication signal received from the redundant switch system into a format compatible with the communication link.
22. An I/O module in electrical communication with a communication link and first and second switch fabric control modules, said first and second switch fabric control modules comprising respective first and second switch fabric controllers, first and second switch fabrics operating under the control of the respective controllers, and wherein each of said switch fabrics includes first and second pluralities of inputs and outputs, said I/O module for exchanging communication signals between said communication link and said switch fabric control modules, the I/O module comprising: a cell flow processor; and a line interface operable to receive communication signals from the communication link in a first communication signal format, to convert the communications signals to a second communication signal format used by the cell flow processor, and to provide the communication signals to the cell flow processor in said second communication signal format; said cell flow processor being operable to serialize the communications signals that are received from said line interface, to provide said serialized, converted communication signals to said first switch fabric control module and to provide a serialized test communication signal to one of said plurality of inputs of said second switch fabric in said second communication signal format, to receive the test communication signal from one of said plurality of outputs of the second switch fabric, to generate an error signal if the received test communication signal is not the same as the provided test communication signal.
23. The I/O module of claim 22 wherein the test communication signal includes a header portion and a data portion.
24. The I/O module of claim 23 wherein the test communication signal is stored locally and provided by the cell flow processor.
25. The I/O module of claim 23 wherein the test communication signal is provided in asynchronous transfer mode format.
26. The I/O module of claim 22 wherein the cell flow processor includes a to-switch port processor to provide the test communication signal and a from-switch port processor to receive the test communication signal.
27. The I/O module of claim 22 wherein the cell flow processor determines if the received test communication signal is the same as the provided test communication signal by using a cyclic redundancy check.
28. A method for operating a redundant switch system to perform a switch fabric test, the method comprising the steps of: determining an availability of unallocated bandwidth in a first switch fabric performing foreground operations; generating a switch fabric test enabling signal in response to available unallocated bandwidth; providing the switch fabric test enabling signal to a cell flow processor; providing a serialized test communication signal to an input of a second switch fabric performing background operations in response to the cell flow processor receiving the switch fabric test enabling signal; transporting the serialized test communication signal from the input of the second switch fabric to an output of the second switch fabric; receiving the serialized test communication signal from an output of the second switch fabric; deserializing the serialized test communication signal; and performing error checking on the deserialized test communication signal.
29. The method of claim 28, wherein the test communication signal is a test communication cell.
30. The method of claim 28, further comprising a step of receiving the test communication signal at the cell flow processor.
31. The method of claim 30, wherein error checking is performed at the cell flow processor.
32. The method of claim 28, further comprising a step of: generating an error signal indicating that an error occurred if the test communication signal provided to the input of the second switch fabric differs from the test communication signal received from an output of the second switch fabric.
33. The method of claim 28, further comprising the step of: performing an action after a predefined number of errors are found.
34. The method of claim 33, wherein the action includes enabling an alarm.
35. The method of claim 28, further comprising the step of: incrementing a memory register when an error occurs.
36. The method of claim 28, further comprising the steps of: providing a test communication signal to every input of the second switch fabric; receiving a corresponding test communication signal from every output of the second switch fabric; and performing error checking on every received test communication signal.
37. The method of claim 28, further comprising a step of providing unallocated bandwidth during a predefined period of time.
38. The method of claim 28, wherein the cell flow processor includes a to-switch port processor for sending the test communication signal and a from-switch port processor for receiving the test communication signal.
Patent Citations (271)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3804991 | 1974-04-01 | Hammond et al. | |
| US3974343 | 1976-08-01 | Cheney et al. | |
| US4069399 | 1978-01-01 | Barrett et al. | |
| US4084228 | 1978-04-01 | Dufond et al. | |
| US4240143 | 1980-12-01 | Bessemer et al. | |
| US4485467 | 1984-11-01 | Miles et al. | |
| US4603382 | 1986-07-01 | Cole et al. | |
| US4715030 | 1987-12-01 | Koch et al. | |
| US4727537 | 1988-02-01 | Nichols | |
| US4737953 | 1988-04-01 | Koch et al. | |
| US4748658 | 1988-05-01 | Gopal et al. | |
| US4797881 | 1989-01-01 | Ben-Artzi | |
| US4821034 | 1989-04-01 | Anderson et al. | |
| US4837761 | 1989-06-01 | Isono et al. | |
| US4849968 | 1989-07-01 | Turner | |
| US4870641 | 1989-09-01 | Pattavina | |
| US4872157 | 1989-10-01 | Hemmady et al. | |
| US4872159 | 1989-10-01 | Hemmady et al. | |
| US4872160 | 1989-10-01 | Hemmady et al. | |
| US4872197 | 1989-10-01 | Pemmaraju | |
| US4878216 | 1989-10-01 | Yunoki | |
| US4893302 | 1990-01-01 | Hemmady et al. | |
| US4893307 | 1990-01-01 | McKay et al. | |
| US4894824 | 1990-01-01 | Hemmady et al. | |
| US4897833 | 1990-01-01 | Kent et al. | |
| US4897841 | 1990-01-01 | Gang, Jr. | |
| US4899333 | 1990-02-01 | Roediger | |
| US4920531 | 1990-04-01 | Isono et al. | |
| US4922503 | 1990-05-01 | Leone | |
| US4933938 | 1990-06-01 | Sheehy | |
| US4942574 | 1990-07-01 | Zelle | |
| US4947390 | 1990-08-01 | Sheehy | |
| US4953157 | 1990-08-01 | Franklin et al. | |
| US4956839 | 1990-09-01 | Torii et al. | |
| US4958341 | 1990-09-01 | Hemmady et al. | |
| US4979100 | 1990-12-01 | Makris et al. | |
| US4993018 | 1991-02-01 | Hajikano et al. | |
| US5014192 | 1991-05-01 | Mansfield et al. | |
| US5021949 | 1991-06-01 | Morten et al. | |
| US5029164 | 1991-07-01 | Goldstein et al. | |
| US5060228 | 1991-10-01 | Tsutsui et al. | |
| US5067123 | 1991-11-01 | Hyodo et al. | |
| US5070498 | 1991-12-01 | Kakuma et al. | |
| US5072447 | 1991-12-01 | Perloff et al. | |
| US5083269 | 1992-01-01 | Syobatake et al. | |
| US5084867 | 1992-01-01 | Tachibana et al. | |
| US5084871 | 1992-01-01 | Carn et al. | |
| US5090011 | 1992-02-01 | Fukuta et al. | |
| US5090024 | 1992-02-01 | Vander Mey et al. | |
| US5093827 | 1992-03-01 | Franklin et al. | |
| US5093912 | 1992-03-01 | Dong et al. | |
| US5115429 | 1992-05-01 | Hluchyj et al. | |
| US5119369 | 1992-06-01 | Tanabe et al. | |
| US5119372 | 1992-06-01 | Verbeek | |
| US5128932 | 1992-07-01 | Li | |
| US5130975 | 1992-07-01 | Akata | |
| US5130982 | 1992-07-01 | Ash et al. | |
| US5132966 | 1992-07-01 | Hayano et al. | |
| US5146474 | 1992-09-01 | Nagler et al. | |
| US5146560 | 1992-09-01 | Goldberg et al. | |
| US5150358 | 1992-09-01 | Punj et al. | |
| US5151897 | 1992-09-01 | Suzuki | |
| US5157657 | 1992-10-01 | Potter et al. | |
| US5163045 | 1992-11-01 | Caram et al. | |
| US5163046 | 1992-11-01 | Hahne et al. | |
| US5179556 | 1993-01-01 | Turner | |
| US5179558 | 1993-01-01 | Thacker et al. | |
| US5185743 | 1993-02-01 | Murayama et al. | |
| US5191582 | 1993-03-01 | Upp | |
| US5191652 | 1993-03-01 | Dias et al. | |
| US5193151 | 1993-03-01 | Jain | |
| US5197067 | 1993-03-01 | Fujimoto et al. | |
| US5198808 | 1993-03-01 | Kudo | |
| US5199027 | 1993-03-01 | Barri | |
| US5239539 | 1993-08-01 | Uchida et al. | |
| US5253247 | 1993-10-01 | Hirose et al. | |
| US5253248 | 1993-10-01 | Dravida et al. | |
| US5255264 | 1993-10-01 | Cotton et al. | |
| US5255266 | 1993-10-01 | Watanabe et al. | |
| US5257311 | 1993-10-01 | Naito et al. | |
| US5258979 | 1993-11-01 | Oomuro et al. | |
| US5265088 | 1993-11-01 | Takigawa et al. | |
| US5267232 | 1993-11-01 | Katsube et al. | |
| US5268897 | 1993-12-01 | Komine et al. | |
| US5271010 | 1993-12-01 | Miyake et al. | |
| US5272697 | 1993-12-01 | Fraser et al. | |
| US5274641 | 1993-12-01 | Shobatake et al. | |
| US5274768 | 1993-12-01 | Traw et al. | |
| US5280469 | 1994-01-01 | Taniguchi et al. | |
| US5280470 | 1994-01-01 | Buhrke et al. | |
| US5282201 | 1994-01-01 | Frank et al. | |
| US5283788 | 1994-02-01 | Morita et al. | |
| US5285446 | 1994-02-01 | Yonehara | |
| US5287349 | 1994-02-01 | Hyodo et al. | |
| US5287535 | 1994-02-01 | Sakagawa et al. | |
| US5289462 | 1994-02-01 | Ahmadi et al. | |
| US5289463 | 1994-02-01 | Mobasser | |
| US5289470 | 1994-02-01 | Chang et al. | |
| US5291481 | 1994-03-01 | Doshi et al. | |
| US5291482 | 1994-03-01 | McHarg et al. | |
| US5295134 | 1994-03-01 | Yoshimura et al. | |
| US5301055 | 1994-04-01 | Bagchi et al. | |
| US5301184 | 1994-04-01 | Uriu et al. | |
| US5301190 | 1994-04-01 | Tsukuda et al. | |
| US5301193 | 1994-04-01 | Toyofuku et al. | |
| US5303232 | 1994-04-01 | Faulk, Jr. | |
| US5305311 | 1994-04-01 | Lyles | |
| US5309431 | 1994-05-01 | Tominaga et al. | |
| US5309438 | 1994-05-01 | Nakajima | |
| US5311586 | 1994-05-01 | Bogart et al. | |
| US5313454 | 1994-05-01 | Bustini et al. | |
| US5313458 | 1994-05-01 | Suzuki | |
| US5315586 | 1994-05-01 | Charvillat | |
| US5319638 | 1994-06-01 | Lin | |
| US5321695 | 1994-06-01 | Proctor et al. | |
| US5323389 | 1994-06-01 | Bitz et al. | |
| US5333131 | 1994-07-01 | Tanabe et al. | |
| US5333134 | 1994-07-01 | Ishibashi et al. | |
| US5335222 | 1994-08-01 | Kamoi et al. | |
| US5335325 | 1994-08-01 | Frank et al. | |
| US5339310 | 1994-08-01 | Taniguchi | |
| US5339317 | 1994-08-01 | Tanaka et al. | |
| US5339318 | 1994-08-01 | Tanaka et al. | |
| US5341366 | 1994-08-01 | Soumiya et al. | |
| US5341373 | 1994-08-01 | Ishibashi et al. | |
| US5341376 | 1994-08-01 | Yamashita | |
| US5341483 | 1994-08-01 | Frank et al. | |
| US5345229 | 1994-09-01 | Olnowich et al. | |
| US5345438 | 1994-09-01 | Ozaki | |
| US5350906 | 1994-09-01 | Brody et al. | |
| US5355372 | 1994-10-01 | Sengupta et al. | |
| US5357506 | 1994-10-01 | Sugawara | |
| US5357507 | 1994-10-01 | Hughes et al. | |
| US5357508 | 1994-10-01 | Le Boudec et al. | |
| US5357510 | 1994-10-01 | Norizuki et al. | |
| US5359600 | 1994-10-01 | Ueda et al. | |
| US5361251 | 1994-11-01 | Aihara et al. | |
| US5361372 | 1994-11-01 | Rege et al. | |
| US5363433 | 1994-11-01 | Isono | |
| US5363497 | 1994-11-01 | Baker et al. | |
| US5365514 | 1994-11-01 | Hershey et al. | |
| US5369570 | 1994-11-01 | Parad | |
| US5371893 | 1994-12-01 | Price et al. | |
| US5373504 | 1994-12-01 | Tanaka et al. | |
| US5375117 | 1994-12-01 | Morita et al. | |
| US5377262 | 1994-12-01 | Bales et al. | |
| US5377327 | 1994-12-01 | Jain et al. | |
| US5379297 | 1995-01-01 | Glover et al. | |
| US5379418 | 1995-01-01 | Shimazaki et al. | |
| US5390170 | 1995-02-01 | Sawant et al. | |
| US5390174 | 1995-02-01 | Jugel | |
| US5390175 | 1995-02-01 | Hiller et al. | |
| US5392280 | 1995-02-01 | Zheng | |
| US5392402 | 1995-02-01 | Robrock, II | |
| US5394396 | 1995-02-01 | Yoshimura et al. | |
| US5394397 | 1995-02-01 | Yanagi et al. | |
| US5398235 | 1995-03-01 | Tsuzuki et al. | |
| US5400337 | 1995-03-01 | Munter | |
| US5402415 | 1995-03-01 | Turner | |
| US5412648 | 1995-05-01 | Fan | |
| US5414703 | 1995-05-01 | Sakaue et al. | |
| US5418942 | 1995-05-01 | Krawchuk et al. | |
| US5420858 | 1995-05-01 | Marshall et al. | |
| US5420988 | 1995-05-01 | Elliott | |
| US5422879 | 1995-06-01 | Parsons et al. | |
| US5425021 | 1995-06-01 | Derby et al. | |
| US5425026 | 1995-06-01 | Mori | |
| US5426635 | 1995-06-01 | Mitra et al. | |
| US5432713 | 1995-07-01 | Takeo et al. | |
| US5432784 | 1995-07-01 | Ozveren | |
| US5432785 | 1995-07-01 | Ahmed et al. | |
| US5432908 | 1995-07-01 | Heddes et al. | |
| US5436886 | 1995-07-01 | McGill | |
| US5436893 | 1995-07-01 | Barnett | |
| US5440547 | 1995-08-01 | Easki et al. | |
| US5444702 | 1995-08-01 | Burnett et al. | |
| US5446733 | 1995-08-01 | Tsuruoka | |
| US5446737 | 1995-08-01 | Cidon et al. | |
| US5446738 | 1995-08-01 | Kim et al. | |
| US5448559 | 1995-09-01 | Hayter et al. | |
| US5448621 | 1995-09-01 | Knudsen | |
| US5450406 | 1995-09-01 | Esaki et al. | |
| US5452296 | 1995-09-01 | Shimizu | |
| US5454299 | 1995-10-01 | Thessin et al. | |
| US5455820 | 1995-10-01 | Yamada | |
| US5455825 | 1995-10-01 | Lauer et al. | |
| US5457687 | 1995-10-01 | Newman | |
| US5459743 | 1995-10-01 | Fukuda et al. | |
| US5461609 | 1995-10-01 | Pepper | |
| US5461611 | 1995-10-01 | Drake, Jr. et al. | |
| US5463620 | 1995-10-01 | Sriram | |
| US5463629 | 1995-10-01 | Ko | |
| US5463775 | 1995-10-01 | DeWitt et al. | |
| US5465331 | 1995-11-01 | Yang et al. | |
| US5465365 | 1995-11-01 | Winterbottom | |
| US5469003 | 1995-11-01 | Kean | |
| US5473608 | 1995-12-01 | Gagne et al. | |
| US5475679 | 1995-12-01 | Munter | |
| US5479401 | 1995-12-01 | Bitz et al. | |
| US5479402 | 1995-12-01 | Hata et al. | |
| US5483526 | 1996-01-01 | Ben-Nun et al. | |
| US5485453 | 1996-01-01 | Wahlman et al. | |
| US5485455 | 1996-01-01 | Dobbins et al. | |
| US5487063 | 1996-01-01 | Kakuma et al. | |
| US5488606 | 1996-01-01 | Kakuma et al. | |
| US5491691 | 1996-02-01 | Shtayer et al. | |
| US5491694 | 1996-02-01 | Oliver et al. | |
| US5493566 | 1996-02-01 | Ljungberg et al. | |
| US5497369 | 1996-03-01 | Wainwright | |
| US5499238 | 1996-03-01 | Shon | |
| US5504741 | 1996-04-01 | Yamanaka et al. | |
| US5504742 | 1996-04-01 | Kakuma et al. | |
| US5506834 | 1996-04-01 | Sekihata et al. | |
| US5506839 | 1996-04-01 | Hatta | |
| US5506956 | 1996-04-01 | Cohen | |
| US5509001 | 1996-04-01 | Tachibana et al. | |
| US5509007 | 1996-04-01 | Takashima et al. | |
| US5513134 | 1996-04-01 | Cooperman et al. | |
| US5513178 | 1996-04-01 | Tanaka | |
| US5513180 | 1996-04-01 | Miyake et al. | |
| US5515359 | 1996-05-01 | Zheng | |
| US5517495 | 1996-05-01 | Lund et al. | |
| US5519690 | 1996-05-01 | Suzuka et al. | |
| US5519700 | 1996-05-01 | Punj | |
| US5521905 | 1996-05-01 | Oda et al. | |
| US5521915 | 1996-05-01 | Dieudonne et al. | |
| US5521916 | 1996-05-01 | Choudhury et al. | |
| US5521917 | 1996-05-01 | Watanabe et al. | |
| US5521923 | 1996-05-01 | Willmann et al. | |
| US5523999 | 1996-06-01 | Takano et al. | |
| US5524113 | 1996-06-01 | Gaddis | |
| US5526344 | 1996-06-01 | Diaz et al. | |
| US5528588 | 1996-06-01 | Bennett et al. | |
| US5528590 | 1996-06-01 | Iidaka et al. | |
| US5528591 | 1996-06-01 | Lauer | |
| US5530695 | 1996-06-01 | Digne et al. | |
| US5533009 | 1996-07-01 | Chen | |
| US5533020 | 1996-07-01 | Byrn et al. | |
| US5535196 | 1996-07-01 | Aihara et al. | |
| US5535197 | 1996-07-01 | Cotton | |
| US5537394 | 1996-07-01 | Abe et al. | |
| US5541912 | 1996-07-01 | Choudhury et al. | |
| US5544168 | 1996-08-01 | Jeffrey et al. | |
| US5544169 | 1996-08-01 | Norizuki et al. | |
| US5544170 | 1996-08-01 | Kasahara | |
| US5546389 | 1996-08-01 | Wippenbeck et al. | |
| US5546391 | 1996-08-01 | Hochschild et al. | |
| US5546392 | 1996-08-01 | Boal et al. | |
| US5550821 | 1996-08-01 | Akiyoshi | |
| US5550823 | 1996-08-01 | Irie et al. | |
| US5553057 | 1996-09-01 | Nakayama | |
| US5553068 | 1996-09-01 | Aso et al. | |
| US5555243 | 1996-09-01 | Kakuma et al. | |
| US5555265 | 1996-09-01 | Kakuma et al. | |
| US5557607 | 1996-09-01 | Holden | |
| US5568479 | 1996-10-01 | Watanabe et al. | |
| US5570361 | 1996-10-01 | Norizuki et al. | |
| US5570362 | 1996-10-01 | Nishimura | |
| US5572522 | 1996-11-01 | Calamvokis et al. | |
| US5577032 | 1996-11-01 | Sone et al. | |
| US5577035 | 1996-11-01 | Hayter et al. | |
| US5583857 | 1996-12-01 | Soumiya et al. | |
| US5583858 | 1996-12-01 | Hanaoka | |
| US5583861 | 1996-12-01 | Holden | |
| US5590132 | 1996-12-01 | Ishibashi et al. | |
| US5602829 | 1997-02-01 | Nie et al. | |
| US5610913 | 1997-03-01 | Tomonaga et al. | |
| US5623405 | 1997-04-01 | Isono | |
| US5625846 | 1997-04-01 | Kobayakawa et al. | |
| US5633861 | 1997-05-01 | Hanson et al. | |
| JPX484943 | 1992-03-01 |
Non-Patent Literature (17)
- An Ascom Timeplex White Paper, Meeting Critical Requirements with Scalable Enterprise Networking Solutions Based on a Unified ATM Foundation, pp. 1-12, Apr. 1994--Apr. 1995?.
- Douglas H. Hunt, ATM Traffic Management--Another Perspective, Business Communications Review, Jul. 1994.
- Richard Bubenik et al., Leaf Initiated Join Extensions, Technical Committee, Signalling Subworking Group, ATM Forum/94-0325R1, Jul. 1, 1994.
- Douglas H. Hunt et al., Flow Controlled Virtual Connections Proposal for ATM Traffic Management (Revision R2), Traffic Management Subworking Group, ATM Forum/94-0632R2, Aug. 1994.
- Flavio Bonomi et al., The Rate-Based Flow Control Framework for the Available Bit Rate ATM Service, IEEE Network, Mar./Apr. 1995, pp. 25-39.
- R. Jain, Myths About Congestion Management in High Speed Networks, Internetworking Research and Experience, vol. 3, 101-113 (1992).
- Douglas H. Hunt et al., Credit-Based FCVC Proposal for ATM Traffic Management (Revision R1), ATM Forum Technical Committee Traffic Management Subworking Group, ATM Forum/94-0168R1, Apr. 28, 1994.
- Douglas H. Hunt et al., Action Item Status for Credit-Based FCVC Proposal, ATM Forum Technical Committee Traffic Management Subworking Group, ATM Forum/94-0439, Apr. 28, 1994.
- Timothy P. Donahue et al., Arguments in Favor of Continuing Phase 1 as the Initial ATM Forum P-NNI Routing Protocol Implementation, ATM Forum Technical Committee, ATM Forum/94-0460, Apr. 28, 1994.
- Richard Bubenick et al., Leaf Initiated Join Extensions, Technical Committee, Signalling Subworking Group, ATM Forum/94-0325, Apr. 28, 1994.
- Rob Coltun et al., PRP: A P-NNI Routing Protocol Proposal, ATM Forum Technical Committee, ATM Forum/94-0492, Apr. 28, 1994.
- Richard Bubenik et al., Leaf Initiated Join Extensions, ATM Forum Technical Committee, Signalling Subworking Group, ATM Forum 94-0325, Apr. 28, 1994.
- Richard Bubenik et al., Requirements For Phase 2 Signaling Protocol, ATM Forum Technical Committee, Signalling Subworking Group, ATM Forum 94-1078, Jan. 1, 1994.
- H.T. Kung and K. Chang, Receiver-Oriented Adaptive Buffer Allocation in Credit-Based Flow Control for ATM Networks, Proceedings of INFOCOM '95, Apr. 2-6, 1995, pp. 1-14.
- H.T. Kung et al., Credit-Based Flow Control for ATM Networks: Credit Update Protocol, Adaptive Credit Allocation, and Statistical Multiplexing, Proceedings of ACM SIGCOMM '94 Symposium on Communications Architectures, Protocols and Applications, Aug. 31-Sep. 2, 1994, pp. 1-14.
- SITA, ATM RFP: C-Overall Technical Requirements, Sep. 1994.
- Hosein F. Badran et al., Head of Line Arbitration in ATM Switches with Input-Output Buffering and Backpressure Control, Globecom, pp. 347-351, 1991.