Charge Pump Circuit of Nonvolatile Semiconductor Memory

The invention is in the field of nonvolatile memories and is more specifically related to charge pump circuits of the nonvolatile memories.

Nonvolatile memories, such as EEPROMs(electrically erasable and programmable memories), use an internally generated high voltage, and a power supply voltage, by which data bits are programmed into memory cells and erased from the memory cells. With the construction of the memory cell in which a floating gate is interposed and electrically isolated between a control gate and a channel region, charges for a data bit are charged at the floating gate to program the memory cell and discharged from the floating gate to perform an erase operation of the memory cell. To perform these functions, an EEPROM needs a voltage high enough to create an electric field between the floating gate and channel region (or bulk region), causing the charges for a data bit to be put into a tunneling condition therebetween. The high voltage generator in the EEPROM is generally referred to as a charge pump circuit. High voltages are generated from a main charge pump circuit and from a local charge pump circuit (or switch charge pump circuit) which receives an output voltage from the main charge pump circuit. High voltage generated by the local charge pump circuit is applied to word lines coupled to control gates of the memory cells (or cell transistors), as disclosed in U.S. Pat. No. 5,473,563.

The local charge pump circuit shown in FIG. 1 provides, during a program mode, a voltage of about 20 V to control gates of cell transistors coupled to a selected word line while unselected word lines are held at a pass voltage of about 10 V . FIG. 1, illustrates a local charge pump, having a generic configuration for the purpose of creating high voltage, including depletion-type MOS (metal-oxide-semiconductor) capacitor 102 and enhancement-typed NMOS field effect transistors 103, 104, 107 and 108. Clock pulse .phi.P generated from oscillator 101 is applied to one electrode of capacitor 102 and the other electrode of capacitor 102, node 110, is connected to the drain and gate of transistor 103. The gate of transistor 103 is coupled to a high voltage generator 105, e.g., the aforementioned main charge pump generating high voltage VH. At switching node 111 connected to the source of transistor 103, the gate of transistor 104 and the gate of transistor 108 which is connected between high voltage generator 105 and output terminal 109, input voltage Vin is loaded through transistor 107 whose gate is fixed to power supply voltage Vcc.

Clock pulse .phi.P, as shown in FIG. 2, has an amplitude between a ground voltage (0 V ) and, the power supply voltage Vcc. In order to provide a stable high voltage to a selected word line, first as a precharging step, input voltage Vin is equivalent to Vcc and is applied to input terminal 106, thereby the precharge voltage at node 111 is Vin-Vtn where Vtn is the threshold voltage of transistor 107. The output voltage Vout becomes Vin-2 V tn where 2 V tn is a sum of threshold voltages of transistors 107 and 108. The voltage at node 110 is also Vin-2 V tn during the precharge period. Thereafter, clock pulse .phi.P goes to Vcc and node 110 is pulled up to Vin-2 V tn+.DELTA.V (.DELTA.V denotes an incremented value of voltage) from the precharge level Vin-2 V tn due to a capacitive coupling by capacitor 102. Switching node 111 retains a voltage of Vin-2 V tn+.DELTA.V-VTN (VTN is threshold voltage of transistor 103), which is higher than the precharge level Vin-Vtn by .DELTA.V-Vtn-VTN. Consequently, while .phi.P is being pulled down to the ground voltage along its falling edge, the voltage level on node 110 is lowered to Vin-2 V tn from Vin-2 V tn+.DELTA.V, by .DELTA.V, by means of a decoupling capacitance through capacitor 102. Since the voltage level at node 110, Vin-2 V tn, is lower than the voltage level at switching node 111 Vin-2 V tn+.DELTA.V-VTN, the current voltage level of node 110 becomes Vin-3 V tn+.DELTA.V-VTN due to decreasing the threshold voltage of transistor 104. The voltage level that switching node 111 is Vin-3 V tn+2.DELTA.V-2 V TN. As a result, the voltage level of node 111 is increased by .DELTA.V-(Vtn+VTN) due to the charge accumulation resulting from every rising edge of clock pulse .phi.P generated from oscillator 101.

In order to secure a stabilized application of high voltage output to selected word lines from the charge pump circuit, the .DELTA.V may not be lower than the sum of threshold voltages of transistors 103 and 104, i.e., Vtn+VTN. However, in a low power memory the voltage .DELTA.V is not high enough to overcome Vtn+VTN. Further, it is impossible to boost the output voltage because a body effect induced by an increasing voltage level on node 111 causes the threshold voltages of transistors 103 and 104 to increase, and because the low power supply voltage limits the available charge accumulation on switching node 111. The body effect, otherwise referred to as substrate bias effect or back-bias effect, appears when the junction of the source of a transistor and a substrate is in a reverse-biased condition caused by increasing the threshold voltage of a transistor such as 103 or 104. A generic formula defining the threshold voltage (vt) involved in the body effect is as follows,

where Vfb is flat-band voltage, .phi.f is work function, .UPSILON. body coefficient and Vsb substrate bias sensitivity.

In the above equation, Vsb is inclined to be sensitive to a substrate voltage while voltage V110 at node 110 and voltage V111at switching node 111 are increasing by themselves, causing the threshold voltages of transistors 103 and 104 to be increased thereby. Therefore, increasing the threshold voltages of the switching transistors 103 and 104 in a low power supply voltage deteriorates the transconduction characteristic with high pumping voltage. Accordingly, the voltage .DELTA.V is not high enough to overcome the threshold voltages of transistors 103 and 104, i.e., .DELTA.V>Vtn+VTN is not achieved (as aforementioned, Vtn and VTN are threshold voltages of transistors 104 and 103, respectively). For example, assuming that the power supply voltage Vcc is 3 V and the coupling ratio of capacitor 102 is 0.9, .DELTA.V and Vth+VTH become about 2.7 V and 1.8 V, respectively. Therefore, the output voltage Vout does not reach let alone exceed 18 V . Referring to FIG. 2, the output voltage Vout is increased during period T1 through which clock pulse .phi.P retains the level of Vcc. But, if Vout rises over 16 v, the increased V111 causes the body effect to be deeper and thereby the coupling voltage .DELTA.V is rapidly reduced to blunt stepping levels of the output voltage Vout. FIG. 4 shows a variation of the output voltage Vout when the power supply voltage Vcc is sloped down, by 0.2 V, to 2.4 V from 3.0 V, demonstrating that the reduction of the power supply voltage is directly involved in decreasing the output voltage Vout of the charge pump circuit.

Accordingly, an object of the invention is to provide a charge pump circuit having an improved transconduction characteristic in a nonvolatile memory.

It is another object of the invention to provide a charge pump circuit having an improved transconduction characteristic in a nonvolatile memory.

In order to accomplish those objects, a charge pump circuit in accordance with this invention generates an output voltage in response to a clock pulse. The charge pump circuit has a switching node connected to a gate of a transistor which is connected between a high voltage output from a high voltage generator and the output voltage, a first path for providing a first coupling voltage to the switching node in response to the clock pulse and a second path for providing a second coupling voltage to the switching in response to an inverse signal of the clock pulse. Each path includes a capacitor, where a capacitor in the first path has a coupling ratio greater than that of a capacitor of the second path.

FIG. 1 illustrates a conventional charge pump circuit;

FIG. 2 is a graphic view showing variations of voltages on nodes and output voltages in FIG. 1;

FIG. 3 is a graphic view showing a variation of output voltage in FIG. 1 when a power supply voltage decreases;

FIG. 4 illustrates a charge pump circuit incorporating the preferred embodiment of the invention;

FIG. 5 is a graphic view showing variations of voltages on nodes and an output voltage in FIG. 4; and

FIG. 6 is a graphic view showing a variation of the output voltage in FIG. 4 when a power supply voltage decreases.

Hereinbelow, applicable embodiments of the invention will be as follows, with the appended drawings. Referring now to the drawings, like reference characters designate like or corresponding parts throughout the several views.

Referring to FIG. 4, a local charge pump of the invention has a stabilization circuit for a switching voltage therein. The stabilization circuit is constructed between an output terminal of oscillator 101 and a switching node 111, including inverter 112 and capacitor 113 serially connected to each other so as to couple an inverse signal .phi.PB of clock pulse .phi.P to the switching node 111. The stabilization circuit causes the voltage at node 111 to discharge when the voltage of clock pulse .phi.P is equivalent to the power supply voltage Vcc. Further, the stabilization circuit supplies charge to the switching node 111, thereby achieving a constant voltage level at the switching node 111 when the clock pulse .phi.P is at ground voltage (i.e. 0 volts).

The .phi.P as output signal of oscillator 101 is also coupled to node 110 through depletion-typed capacitor 102. Between node 110 and switching node 111 a diode-connected NMOS transistor 103 is connected. The gate and drain of transistor 103, connected to node 110, are coupled to high voltage VH output of high voltage generator 105 through NMOS transistor 104 whose gate is connected to switching node 111. Input voltage Vin is transferred to switching node 111 through normally-turned-on NMOS transistor 107 and output terminal 109 for output voltage Vout is isolated from VH by NMOS transistor 108 with the gate connected to the switching node 111. The high voltage generator 105 may be regarded as a main charge pump circuit in the memory. As shown in FIG. 4, switching node 111 is coupled not only to a path including capacitor 102 but also to another path including capacitor 113. Assuming that the coupling ratio of capacitor 102 is about 0.9, a coupling voltage .DELTA.V at node 110 by means of capacitor 102 becomes (0.9.times.Vcc). Preferably, the coupling ratio of capacitor 102 is greater than that of capacitor 113.

The clock pulse .phi.P of high voltage level is applied to capacitor 113 through inverter 112, as well as to capacitor 102. Even when .phi.P is at a high voltage level and capacitor 102 is thereby coupled, capacitor 113 receives an inverse signal .phi.PB of .phi.P from inverter 112 which causes the coupling voltage on switching node 111 to discharge independent from the charging action by .phi.P. Thus, the current voltage level of switching node 111 is decreased by .phi.PB and thereby the duration of back-biasing in transistor 103 is shortened. When .phi.P is at a low voltage level, capacitor 102 is in a decoupled state and .phi.PB is at a high voltage, which provides .DELTA.V2. .DELTA.V2 is the coupling voltage supplied by capacitor 113 to switching node 111 and serves to reduce an increase in the threshold voltage of transistor 104 due to back-biasing. Even when .DELTA.V1 is being reduced in a memory system with low power supply voltage such as 2.4 V or 3.3 V, the coupling voltage .DELTA.V2 by capacitor 113 stabilizes a voltage level at switching node 111.

The overall operation of the charge pump circuit of FIG. 4 will be described hereinafter. At an initial state, switching node 111 is at a precharge voltage Vin-Vtn when input voltage Vin is applied to input terminal 106, where Vtn is the threshold voltage of each of transistors 104, 107 and 108. The output voltage Vout is Vin-2 V tn that is the sum of the threshold voltages of transistors 107 and 108. Hence, the voltage level at node 110 is Vin-2 V tn. Thereafter, if .phi.P goes to the level of the power supply voltage from the ground voltage, node 110 is pulled up to Vin-2 V tn+.DELTA.V1, by means of the capacitive coupling with capacitor 102, that is higher than the precharge voltage level by .DELTA.V1. The voltage at switching node 111 is then at a voltage level lower than that of node 110 through the VTN threshold voltage of transistor 103, and further decreases to Vin-2 V tn+.DELTA.V1-VTN.DELTA.V2 by .DELTA.V2 because of a decoupling action of capacitor 113. As shown in FIG. 5, output voltage Vout itself increases when .phi.PB is at the voltage level of Vcc, i.e., during the period T2 for incrementing .DELTA.V2, so that the body effect induced in transistor 103 for T1 does not occur and an increased voltage at switching node 111 by .DELTA.V2 causes the transconductive performance of transistor 108 to be advanced. The increase of Vout minimizes the body effect of transistor 103 because .DELTA.V1 is coupled to switching node 111. FIG. 6 shows that the output voltage Vout is not affected from a decrease in power supply voltage Vcc i.e., by 0.2 V, to 2.4 V from 3.0 V . FIG. 6 and FIG. 4 illustrate that about 5 microseconds after the onset of pumping, the output voltage Vout in FIG. 6 is about 21 V whereas that of FIG. 3 stays at about 18 V .

As described above, the charge pump circuit according to the present invention supplies a stabilized output voltage over 20 V to a selected word line for a specific operation such a programming mode in a nonvolatile memory, and furthermore provides a high voltage even in a low power memory.

Although three embodiments of the invention have been disclosed and described, it will be appreciable that other embodiments and modification of the invention are possible. For example, it is possible to employ enhancement-typed capacitors instead of the depletion-typed capacitors in the circuit, and to utilize other types of field effect transistors instead of the MOS transistors. The invention is not limited to the described embodiments, for the purpose of controlling the coupling voltage .DELTA.V2, other signals modified from the clock pulse may be used.