Reference Voltage Generating Circuit Having Reduced Power Consumption

The present invention relates to a reference voltage generating circuit and, more particularly, to a reference voltage generating circuit for applying a reference voltage of 1/2 a power source voltage V.sub.CC to a digit line or the like in a semiconductor memory device.

As shown in FIG. 4, a conventional reference voltage generating circuit comprises a resistor R1 having one terminal connected to the power source terminal of a power source voltage V.sub.CC, a resistor R2 having one terminal connected to the ground terminal of a reference potential, an n-type transistor Q3 having the drain and gate connected to the other terminal of the resistor R1, a p-type transistor Q4 having the drain and gate connected to the other terminal of the resistor R2 and the source connected to the source of the transistor Q3, an n-type transistor Q7 having the drain connected to the power source terminal and the gate connected to the drain and gate of the transistor Q3, and a transistor Q8. The transistor Q8 has the drain connected to the ground terminal, the gate connected to the drain and gate of the transistor Q4, and the source connected to the source of the transistor Q7 and used as the output terminal of a reference voltage V.sub.OUT. A current flows in a path of the resistor R1, the transistors Q3 and Q4, and the resistor R2 and a path of the transistors Q7 and Q8, thereby generating a reference voltage of 1/2 a power source voltage V.sub.CC. The reference voltage is applied to a digit line as a precharge voltage or to a counter electrode of a memory cell.

Since the digit line and the counter electrode of the memory cell are regarded as capacitors each having a large capacitance, a reference voltage need not always be applied to the digit line and the counter electrode. However, the above conventional reference voltage generating circuit has a structure in which a current always flows in the path of the resistors R1 and R2 and the transistors Q3 and Q4 and the path of the transistors Q7 and Q8. Therefore, a power is disadvantageously consumed more than necessary.

It is an object of the present invention to provide a reference voltage generating circuit capable of reducing power consumption.

It is another object of the present invention to provide a reference voltage generating circuit capable of generating a stable reference voltage only when it is required.

The present invention achieves these objects with a reference voltage generating circuit including a first series circuit having a first resistor, a first transistor, a second transistor, and a second resistor coupled in series between power source terminals. A second series connection circuit including third and fourth transistors which have control electrodes respectively connected to a connection point between the first resistor and the first transistor and a connection point between the second resistor and the second transistor are connected is series between said power source terminals and have a common connection point serving as a reference voltage output terminal. A control circuit is coupled to the first series circuit for sequentially ON/OFF-controlling the first and second transistors by a control signal. The ON/OFF-controlling of the first and second transistor decreases the current flow in the first series connection circuit and decreases power consumption of the reference voltage generating circuit. A capacitor, connected to a connection point between the first and second transistors, stores a potential of the connection point between the first and second transistors.

FIGS. 1 and 2 are circuit diagrams, respectively, showing the first and second embodiments of the present invention;

FIG. 3 is a timing chart showing signal waveforms for explaining an operation of the embodiment in FIG. 2; and

FIG. 4 is a circuit diagram showing a conventional reference voltage generating circuit.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the first embodiment of the present invention.

In this embodiment, a reference voltage generating circuit comprises a p-type first transistor Q1, an inverter IV1, an n-type second transistor Q2, a first resistor R1, a second resistor R2, an n-type third transistor Q3, a p-type fourth transistor Q4, a capacitor C1, an n-type fifth transistor Q5, a p-type sixth transistor Q6, an n-type seventh transistor Q7, and a p-type eighth transistor. The p-type first transistor Q1 has the source connected to the first power source terminal applied with a power source voltage V.sub.CC and the gate to which a control signal CNT is input. The inverter IV1 inverts the level of the control signal CNT. The n-type second transistor Q2 has the source connected to the ground terminal of the second power source terminal and the gate connected to the output terminal of the inverter IV1. The first resistor R1 has one terminal connected to the drain of the first transistor Q1. The second resistor R2 has one terminal of the transistor Q2. The n-type third transistor Q3 has the drain and gate connected to the other terminal of the first resistor R1. The p-type fourth transistor Q4 has the drain and gate connected to the other terminal of the second resistor R2 and has the source and substrate connected to the source of the third transistor Q3. The capacitor C1 has one terminal connected to the source of the fourth transistor and the other terminal connected to the ground terminal. The n-type fifth transistor Q5 has the source connected to the ground terminal, the drain connected to the gate and drain of the third transistor Q3, and the gate to which the control signal CNT is input. The p-type sixth transistor Q6 has the source connected to the first power source terminal, the drain connected to the gate and drain of the fourth transistor Q4, and the gate connected to the output terminal of the inverter IV1. The n-type seventh transistor Q7 has the drain connected to the first power source terminal and the gate connected to the drain and gate of the third transistor Q3. The p-type eighth transistor Q8 has the drain connected to the ground terminal, the gate connected to the drain and gate of the fourth transistor Q4, and the source and substrate connected to the source of the seventh transistor Q7. The eighth transistor Q8 has the source as the output terminal of a reference voltage V.sub.OUT.

The operation of this embodiment will be described below.

When the control signal CNT goes to low level, the transistor Q1 is turned on, the transistors Q5 and Q6 are turned off, and the transistor Q2 is turned on. Therefore, a current flows from the power source terminal to the ground terminal through a path constituted by the transistor Q1, the resistor R1, the transistor Q3, the transistor Q4, the resistor R2, and the transistor Q2.

At this time, assume that the resistors R1 and R2 have resistances R.sub.1 and R.sub.2, respectively, that each p-type transistor has a threshold value V.sub.TP, and that each n-type transistor has a threshold value V.sub.TN. In this case, a connection point potential V.sub.1 between the sources of the transistors Q3 and Q4 generated by a current I.sub.1 flowing through the above path is stably give by the following equation: ##EQU1## For example, if V.sub.TP =V.sub.TN and R.sub.1 =R.sub.2 then, V.sub.1 =V.sub.CC /2.

At this lime, the transistors Q3 and Q7 have a common gate potential, and the transistors Q4 and Q8 have a common gate potential. Therefore, the connection point potential between the transistors Q3 and Q4 is equal to the potential of the output terminal of the reference voltage V.sub.OUT.

When the control signal goes to high level, the transistor Q1 is turned off, the transistors Q5 and Q6 are turned on, and the transistor Q2 is turned off. The gates of the transistors Q4 and Q8 have a power source voltage V.sub.CC, and the transistors Q4 and Q8 are turned off. Therefore, since the reference voltage generating circuit becomes inactive as a whole, the output terminal of the reference voltage V.sub.OUT is set in a high-impedance state so that the reference voltage generating circuit does not consume any current.

At this time, the capacitor C1 retains a potential V.sub.1 obtained immediately before the circuit is set to be inactive. The capacitor C1 prepares for a case wherein the control signal CNT is input to activate the circuit again.

Note that a switch corresponding to the transistors Q1 and Q2 may be connected in series with the transistors Q7 and Q8 to be ON/OFF-controlled by the control signal CNT. In this case, the transistors Q1 and Q2 can be omitted.

FIG. 2 shows the second embodiment of the present invention.

According to this embodiment, a reference voltage generating circuit comprises a first transistor Q1, a first inverter IV1, a second transistor Q2, a first resistor R1, a second resistor R2, a third transistor Q3, a fourth transistor Q4, a capacitor C1, a p-type fifth transistor Q9, a second inverter IV2, an n-type sixth transistor Q10, an n-type seventh transistor Q7, and a p-type eighth transistor Q8. The first transistor Q1 has the same connection arrangement as in the first embodiment in FIG. 1 except that a first control signal CNT1 is input to the gate of the transistor Q1. The p-type fifth transistor Q9 has the source to which a power source voltage V.sub.CC is supplied and the gate to which a second control signal CNT2 is supplied. The second inverter IV2 converts the level of the second control signal CNT2. The n-type sixth transistor Q10 has the source connected to the ground terminal of the second power source terminal and the gate connected to the output terminal of the second inverter IV2. The n-type seventh transistor Q7 has the drain connected to the drain of the transistor Q9 and the gate connected to the drain and gate of the third transistor Q3. The p-type eighth transistor Q8 has the drain connected to the drain of the sixth transistor Q10, the gate connected to the drain and gate of the fourth transistor Q4, and the source connected to the source of the seventh transistor Q7. The eighth transistor Q8 has the source as the output terminal of a reference voltage V.sub.OUT.

In this embodiment, as shown in FIG. 3, the control signal CNT1 is set to be low level to stabilize the potential of the capacitor C1. Thereafter, the control signal CNT2 is set to be low level, thereby obtaining an output which is stabler than the output obtained in the first embodiment.

In this case, when the potential of the capacitor C1 immediately before the control signal CNT1 is set to be low level is set at a potential V.sub.H, the potential Vt of the capacitor C1 upon a lapse of time t after the control signal CNT1 is set to be low level is given by the following equation: ##EQU2##

The resistances R.sub.1 and R.sub.2 of the resistors R1 and R2 and the capacitance C of the capacitor C1 are determined by this equation, thereby determining a time difference between the control signals CNT1 and CNT2.

As described above, since the reference voltage generating circuit according to the present invention can generate a stable reference voltage only when the voltage is required, waste of power consumption is suppressed, and the power consumption can be decreased.