Constant Voltage Generating Circuit for Selectively Generating a Constant Voltage at a High-Speed

1. Field of the Invention

The present invention relates to a constant voltage generating circuit for selectively generating a constant voltage, and more particularly to a constant voltage generating circuit for quickly generating a constant voltage upon request thereof.

2. Description of the Related Art

Constant voltage generating circuits have been widely used for generating constant voltages which are usually utilized as a reference voltages in various fields. For example, in a dynamic memory device, a constant voltage generating circuit is employed for generating a reference voltage used for precharging bit lines. Namely, in a dynamic memory device employing a one-transistor type memory cell, each pair of bit lines are precharged to a reference voltage having an intermediate level of the logic "1" and "0" levels prior to a read operation. A read-out signal from a selected memory cell is applied to one of a pair of bit lines to compare its potential with the reference voltage precharged to the other bit line of the same pair for determining a logic level of the read-out signal. Since the constant voltage generated by the generating circuit is not continuously utilized but is used for only a predetermined period. Therefore, such a constant voltage generating circuit that produces a constant voltage in a controlled manner when the output of the constant voltage is necessary.

A conventional constant voltage circuit of this type is constructed by an output series circuit having a first field effect transistor connected between a first voltage terminal and an output terminal and a second field effect transistor connected between the output terminal and a second voltage terminal and a control circuit for rendering the first and second transistors conductive thereby to produce a constant voltage at the output terminal in a first mode and non-conductive to set the output terminal at a high impedance state in a second mode. The control circuit includes resistors, field effect transistors and switch elements connected in series between the first an second voltage terminals. The switch elements are made conductive in the first mode so that a DC current flows through the control circuit to bias the gates of the first and second transistors, while the switch elements are made non-conductive in the second mode to disenable the bias circuit so that the gates of the first and second transistors are set at inactive levels. When the constant voltage generating circuit switched from the second mode to the first mode, the gates of the first and second transistors are charged to their predetermined bias voltages through the resistors of the control circuit. However, in order to reduce a power consumption due to a current flowing through the bias circuit, the values of the resistors of the control circuit are made large. It requires a relatively large time to precharge the gates of the first and second transistors after the transistion from the second mode to the first mode. Accordingly, the conventional constant voltage generating circuit has a long response time to generate the constant voltage.

It is an object of the present invention to provide a constant voltage generating circuit which can produce a constant voltage output at a high speed upon request therefor.

It is another object of the present invention to provide a constant voltage generating circuit operable with a low power consumption.

The constant voltage generating circuit according to the present invention comprises first and second voltage terminals receiving first and second voltages, respectively; an output terminal; a first field effect transistor having a source-drain path connected between the first voltage terminal and the output terminal and a gate coupled to a first node; a first series circuit having a first resistor and a first switch element connected in series between the first voltage terminal and the first node; an impedance circuit coupled between the first node and the second voltage terminal; means for receiving a control signal assuming one of first and second levels, a first control circuit coupled to the first switch element for rendering the first switch element conductive thereby to generate a first bias voltage at the first node by causing a current flowing through the first series circuit and the impedance circuit in response to the first level of the control signal and non-conductive in response to the second level of the control signal, the first transistor being rendered conductive in response to the first bias voltage at the first node thereby to generate a constant voltage at the output terminal; a second control circuit coupled to the first node for operatively setting the first node at a second bias voltage in response to the second level of the control signal, the first transistor being rendered non-conductive i response to the second bias voltage at the first node; first and second capacitors each having first and second ends; means for connecting the second end of the first capacitor to one of the first and second voltage terminals; means for connecting the second end of the second capacitor to one of the first and second voltage terminals; a first charge circuit coupled to the first capacitor for operatively charging the first end of the first capacitor to the second voltage in response to the second level of the control signal; a second charge circuit coupled to the second capacitor for operatively charging the first end of the second capacitor to the first voltage in response to the second level of the control signal; a first charge control circuit for operatively short-circuiting the first ends of the first and second capacitors thereby to generate a first equilibrium voltage having a value close to the first bias voltage in response to the first level of the control signal; and means for applying the first equilibrium voltage to the first node.

According to the present invention, the first and second capacitors are charged during a stand-by period when the control signal is at the low level and the equilibrium voltage having the value close to the first bias voltage is generated by short-circuiting the first and second capacitor and applied to the first node as soon as the generating circuit is enabled in response to the first level of the control signal. Accordingly, the first node can be set at the first bias voltage at a high speed by way of the first and second capacitors in response to the first level of the control signal, even though the value of the first resistor is large.

The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic circuit diagram showing a constant voltage generating circuit in the prior art;

FIG. 2 is a timing chart showing the operation of the circuit of FIG. 1;

FIG. 3 is a schematic circuit diagram showing a constant voltage generating circuit according to one embodiment of the present invention;

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3;

FIG. 5 is a schematic circuit diagram of a constant voltage generating circuit according to another embodiment of the present invention; and

FIG. 6 is a timing chart showing the operation of the circuit of FIG. 5.

With reference to FIGS. 1 and 2, the constant voltage generating circuit in the prior art will be explained below.

The constant voltage generating circuit 10 comprises an output stage having an N-channel MOS transistor (NMOST) Q.sub.1 and a P-channel MOS transistor (PMOST) Q.sub.2 connected in series between a power voltage terminal Vcc and a ground voltage terminal (GND), and a bias circuit including a series circuit of a resistor R.sub.1, a PMOST Q.sub.5, a NMOST Q.sub.3, a PMOST Q.sub.4, an NMOST Q.sub.6 and a resistor R.sub.2 connected in series between Vcc and GND and a control circuit having an inverter IV.sub.1 receiving a request signal .phi..sub.0 generated from an utilization circuit 12 using the constant voltage output N.sub.1 through an output line 11, a reset NMOS Q.sub.7 and a reset PMOST Q.sub.8. The utilization circuit 12 generates a low (L) level of the request signal .phi..sub.0 when it requests the circuit 10 to output the constant voltage output V.sub.1, and a high (H) level of .phi..sub.0 otherwise.

Operation of the circuit of FIG. 1 will be described in conjunction with the waveform diagram of FIG. 2. First, so far as .phi..sub.0 stays at the L level during an active period TA, the PMOST Q.sub.5 and the NMOST Q.sub.6 are rendered conductive, whereby a predetermined current flows through the series circuit from Vcc--the resistor R.sub.1 --PMOST Q.sub.5 --NMOST Q.sub.3 --PMOST Q.sub.4 --NMOST Q.sub.6 --the resistor R.sub.2 --GND, and predetermined potentials are applied to connection points N.sub.11 and N.sub.21. Here, the resistors R.sub.1 and R.sub.2 having high resistances are inserted to decrease the current consumed by the series circuit at the time when the constant voltage is supplied from the connection point N.sub.1 to the circuit 12 that uses the constant voltage. If the levels at the connection points N.sub.11 and N.sub.21 are denoted by V.sub.11 and V.sub.21, then the following equation holds:

Further, if the level of the output node N.sub.1 is denoted by V.sub.1, then there holds the following relation,

where V.sub.TN and V.sub.TP denote threshold voltages of the NMOST Q.sub.3 and the PMOST Q.sub.4.

From the above equation, the potential V.sub.1 at the connection point N.sub.1 is given by the following relation,

The circuit 10 supplies this potential as the constant voltage to the circuit 12.

Next, when the signal .phi..sub.0 assumes the H level during a reset period T.sub.R, the NMOST Q.sub.7 and the PMOST Q.sub.8 are rendered conductive, while the PMOST Q.sub.5 and the NMOST Q.sub.6 are rendered nonconductive. Thus, the connecting point N.sub.11 assumes ground level and the connection point N.sub.21 assumes the power sourve Vcc level. Then, the NMOST Q.sub.1 and the PMOST Q.sub.2 are rendered nonconductive, and the connection point N.sub.1 set at the high impedance state (floating condition). Under this condition, therefore, no current is consumed by the circuit 10.

When the signal .phi..sub.0 assumes the L level again, the PMOST Q.sub.5 is rendered conductive, and a current is supplied from Vcc via the resistor R.sub.1, to the connection point N.sub.11 that is assuming the ground level. Therefore, the potential rises at the connection point N.sub.11. Similarly, the NMOST Q.sub.6 is rendered conductive, and the level at the point N.sub.21 drops down to the ground potential via the resistor R.sub.2. After a predetermined period T.sub.d of time has passed, the aforementioned levels V.sub.11 and V.sub.21 are assumed, and the intermediate level V.sub.1 is supplied to the circuit 12.

In the above-mentioned conventional constant voltage generating circuit, the connection points N.sub.11 and N.sub.21 are charged and discharged via resistances of R.sub.1 and R.sub.2 when the reset non-feeding condition of constant voltage is to be shifted to the enabled, feeding condition, and the steady condition is assumed. However, since the resistances of R.sub.1 and R.sub.2 are large to reduce the electric power consumed in the circuit 10, an extended period of time (T.sub.d) is required before the potentials at the connection points N.sub.11 and N.sub.21 are stabilized and the output V.sub.1 becomes unstable during this period T.sub.d. Therefore, the conventional circuit cannot quickly meet the request for obtaining the constant voltage.

With reference to FIGS. 3 and 4, the constant voltage generating circuit according to one embodiment will be explained.

In FIG. 3, the elements or portions corresponding to those in FIG. 1 are denoted by the same or similar references and detailed explanation thereof will be omitted.

The constant voltage generating circuit according to this embodiment is featured by a charge control circuit 20 in addition to the conventional circuit portion 10. The charge control circuit 20 includes capacitors C.sub.1, C.sub.2, C.sub.3, C.sub.4, NMOSTs Q.sub.9, Q.sub.10, Q.sub.11, a PMOST Q.sub.11, and inverters IV.sub.2 and IV.sub.3.

With reference to FIG. 4, the operation of the circuit of FIG. 3 will be explained.

During a first active period TA.sub.1 prior to a time point t.sub.1, the request from the utilization circuit 12 assumes the active, L level and its inverted signal .phi..sub.0 ' by the inverter IV.sub.2 is at the H level. Therefore, the NMOSTs Q.sub.9 and Q.sub.10 are rendered conductive and the PMOST Q.sub.11 and the NMOST Q.sub.12 are rendered nonconductive. Thus, the connection points N.sub.11 and N.sub.22 assume a potential equal to V.sub.12 and the connection points N.sub.21 and N.sub.22 assume a potential equal to V.sub.22.

Next, during a reset period T.sub.R from t.sub.1 to t.sub.2 when .phi..sub.0 has the H level, and the NMOS Q.sub.1 and PMOST Q.sub.2 are nonconductive to set N.sub.1 at the high impedance state (Hi-z). Also, the signal .phi..sub.0 ' assumes the L level and the NMOSTs Q.sub.9 and Q.sub.10 are rendered non-conductive, so that the connection points N.sub.11 and N.sub.12 and the connection points N.sub.21 and N.sub.22 are isolated from each other. At this moment, as described with reference to the prior art, the NMOST Q.sub.7 and the PMOST Q.sub.8 are rendered conductive so that the connection point N.sub.11 assumes the ground level and the connection point N.sub.21 assumes the Vcc level. The PMOST Q.sub.11 and NMOST Q.sub.12 are rendered conductive, too, and the connection point N.sub.12 assumes the Vcc level and the connection point N.sub.22 assumes the ground level. Here, if the amounts of electric charges stored in the capacitors C.sub. 2 and C.sub.3 are denoted by Q.sub.2 and Q.sub.3, and potentials at the consumption points N.sub.12 and N.sub.21 are denoted by V.sub.12 and V.sub.21, then there hold the following relation,

Next, when the condition is changed to a second active period TA.sub.2 from t.sub.2 and .phi..sub.0 is changed to the L level again, the PMOSTs Q.sub.8, Q.sub.11 and the NMOSTs Q.sub.7, Q.sub.12 are rendered non-conductive. When the NMOSTs Q.sub.9 and Q.sub.10 are rendered conductive, the potential at the connection point N.sub.11 approaches that of the point N.sub.12 and the potential at the connection point N.sub.21 approaches that of the point N.sub.22 as the electric charges move from C.sub.2 to C.sub.1 and from C.sub.3 to C.sub.4. At this moment, if a resultant potential at the nodes N.sub.11 and N.sub.12 is denoted by V.sub.11 ' and a resultant potential at the nodes N.sub.21 and N.sub.22 is denoted by V.sub.21 ' then the following relations hold true from the law of conservation of electric charge, i.e.,

Therefore,

Thus, levels at the connection points N.sub.11 and N.sub.12 can be determined instantaneously depending upon the ratios of capacitances of the capacitors C.sub.1, C.sub.2 and the capacitors C.sub.3, C.sub.4. By adjusting the capacitances of C.sub.1 -C.sub.4, therefore, the potentials can be brought to the levels at the connection points N.sub.11 and N.sub.12 determined by the ratio of the resistances R.sub.1 and R.sub.2. That is, referring to FIG. 4, when the request signal .phi..sub.0 is produced, the potentials at the connection points N.sub.11 and N.sub.21 readily reach their stable points and, accordingly, the potential at the output N.sub.1 readily arrives at its specified level V.sub.1.

FIG. 5 shows the constant voltage generating circuit according to another embodiment of the present invention. A charge control circuit 30 is formed by smaller number of elements than those of the circuit 20 of FIG. 3, and is controlled by a control signal .phi..sub.1. FIG. 6 illustrates waveforms of control signals and levels at the internal connection points. The control signal .phi..sub.1 is a one-shot signal that is activated only when .phi..sub.0 changes from H into L during T.sub.d '. So far as .phi..sub.1 remains at the L level, an NMOST Q.sub.13 remains nonconductive. Therefore, so far as .phi..sub.0 remains at the H level during T.sub.R, terminals of the capacitors C.sub.1 ', C.sub.2 ' on the side of the connection points N.sub.11, N.sub.21 assume the ground level and the power source level Vcc, respectively. If now, .phi..sub.0 changes from H to L and .phi..sub.1 assumes the H level during T.sub.d ' whereby the NMOST Q.sub.13 is rendered conductive to give a level V.sub.13 expressed by the following equation to the connection points N.sub.11 and N.sub.21,

Then, the signal .phi..sub.1 readily assumes the L level and the NMOST Q.sub.13 is rendered non-conductive.

Thus, the level V.sub.13 determined by the ratio of capacitances of the capacitors C.sub.1 ', C.sub.2 ' reaches the specified levels V.sub.11 and V.sub.21 through R.sub.1 and R.sub.2 within a very short period T.sub.d ' of time compared with that of the prior art. This embodiment is advantageous in that the control circuit constituted by a decreased number of elements supplies a constant voltage to the circuit 12 at a high speed.

Though ends on one side of the capacitors were grounded in the above-mentioned embodiments, they need not necessarily be connected in a manner as described above but may suitably be connected to the power source terminal V.sub.cc in accordance with the present invention.

According to the present invention as described above, capacitors are connected to connection points to where are connected gates of two transistors that supply an intermediate level of constant voltage, and charge and discharge of electric charge to and from the capacitors are controlled at a moment when the constant voltage is requested. Therefore, the constant voltage of a stable level can be quickly supplied to the circuit without increasing the consumption of electric power by the circuit.