Spindle Motor Driving Control Circuit of Disk Drive Recording Device

This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. .sctn.119 from an application for Spindle Motor Driving Control Circuit Of Disk Drive Recording Device earlier filed in the Korean Industrial Property Office on 27 Apr. 1995 and there assigned Serial No. 10180/1995.

The present invention relates to a disk drive recording device, and more particularly to a spindle motor driving control circuit for driving a disk recording medium.

Since disk drive recording devices, such as hard disk drives, are operating at increasingly high velocities and accommodate higher degrees of data storage capacity, the reliability of data read from and written onto the disk recording medium has become a key concern. As the rotating velocity of a spindle motor in the disk drive recording device has increased, (e.g. 3600 rpm.fwdarw.4500 rpm.fwdarw.5400 rpm, etc.), the structure of the spindle motor has changed and a spindle motor driving control circuit for maintaining stable performance of the Repeatable Run-Out (RRO) and Non-Repeatable Run-Out (NRRO) techniques has improved.

One prior art reference that controls operation of the spindle motor in a disk drive recording device is disclosed in U.S. Pat. No. 5,379,166 entitled Magnetic Disk Drive Device issued to Tsukada et al. on 3 Jan. 1995. In Tsukada et al. '166, specific data is detected at the time of starting the rotation of the magnetic disk, and the speed of the disk is measured on the basis of the data obtained. The spindle motor is thereby controlled to rotate at a constant speed. While conventional art, such as Tsukada et al. '166, has merit in its own right, I believe that an improved spindle motor control device can be contemplated wherein reliable data read and write operations can be consistently performed.

Accordingly, it is an object of the present invention to provide an improved spindle motor driving control circuit in a disk drive recording device.

It is another object to provide a spindle motor driving control circuit in a disk drive recording device that consistently provides a high degree of reliablity during data read and write operations.

It is still another object to provide a spindle motor driving control circuit capable of suppressing errors generated during reading and writing operations due to vibrations of the spindle motor in a disk drive recording device.

It is yet another object to provide a spindle motor driving control circuit in a disk drive recording device capable of controlling a spindle motor to rotate at a constant velocity.

To achieve these and other objects, the present invention provides a spindle motor driving control circuit in a disk drive recording device including a spindle motor for rotating a disk recording medium, a motor driving unit for controlling driving of the spindle motor, and a control unit for controlling the overall operation of the disk drive recording device. The circuit includes: a servo address mark (SAM) detecting unit for detecting a servo address mark (SAM) recording pattern from a signal read from the disk recording medium and generating a servo address mark (SAM) pulse corresponding to detection of the servo address mark (SAM) recording pattern; a first counting unit for starting a first counting operation and generating a first count value in response to the servo address mark (SAM) pulse; a first register for storing a predetermined reference value provided from the control unit; a comparing unit for comparing the predetermined reference value with the first count value and generating an end of servo sector (ENDS) pulse when the two values are equal; a window length counting unit for starting a second counting operation and generating a second count value in response to the end of servo sector (ENDS) pulse, and terminating the second counting operation in response to the servo address mark (SAM) pulse; and an adding unit for generating an added value by adding the second count value to the predetermined reference value. The control unit controls the driving of the spindle motor based on the added value.

A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:

FIG. 1 is a block diagram illustrating a spindle motor driving control circuit of a conventional disk drive recording device;

FIG. 2 is a block diagram illustrating portions of a disk drive recording device constructed according to a preferred embodiment of the present invention;

FIG. 3 is a timing diagram illustrating operations of components in FIG. 2; and

FIGS. 4A through 4C are detailed circuit diagrams illustrating the structures of the spindle motor driving control circuit in FIG. 2.

Turning now to the drawings and referring to FIG. 1, a block diagram of a spindle motor driving control circuit in a conventional disk drive recording device is illustrated. FIG. 1 is comprised of a central processing unit (CPU) 10, a motor driving unit 20, a spindle motor 30, a clock generating unit 40, and a status register 50. The control process of the conventional disk drive recording device shown in FIG. 1 is as follows. First, when power is provided to the disk drive recording device, central processing unit (CPU) 10 transmits an enable signal to motor driving unit 20. Clock generating unit 40 generates a reference clock signal for determining a rotating velocity of spindle motor 30 (e.g., 3600 rpm, 4500 rpm, 5400 rpm, etc.) and provides the reference clock signal to motor driving unit 20. Then, when central processing unit (CPU) 10 transmits a start signal to motor driving unit 20, motor driving unit 20 drives spindle motor 30. When spindle motor 30 is rotating at a constant velocity, motor driving unit 20 outputs a ready signal to status register 50 in response to this sensed condition. Central processing unit (CPU) 10 then senses the ready signal indicating that spindle motor 30 has reached a constant velocity through status register 50, and accordingly performs a data reading or writing operation on the disk recording medium.

In the description above, when the rotating velocity of spindle motor 30 exceeds 3240 rpm (which corresponds to 90% of a prescribed rotating velocity of 3600 rpm), the conventional spindle motor driving control circuit generates the ready signal. Under these conditions, there is often a problem in that errors may be generated due to vibrations of spindle motor 30 while reading data from or writing data onto the disk recording medium due to vibrations of spindle motor 30. Furthermore, there is a disadvantage in that the deviation of a reference signal is too large for central processing unit (CPU) 10 to process the error information due to the vibrations of spindle motor 30.

Hereinafter, a detailed description of a preferred embodiment of the present invention will be provided with reference to the attached drawings.

Referring now to FIG. 2, a block diagram of a portion of the disk drive recording device constructed according to a preferred embodiment of the present invention is shown. In FIG. 2, a central processing unit (CPU) 210 controls the general operation of the disk drive recording device. A spindle motor 230 is a rotary actuator and has a driving axis connected to rotate a disk 240, which acts as a recording medium. A motor driving unit 220 controls the driving of spindle motor 230 under the control of central processing unit (CPU) 210. A head 250 moves horizontally along the surface of disk 240 and reads and writes data thereon. An amplifying unit 260 is connected to head 250, and amplifies signals read from and written onto disk 240. A read/write channel circuit 270 receives input data to be written onto disk 240 and encodes the input data to produce an analog flux converting signal and thereby output an encoded signal to amplifying unit 260. Read/write channel circuit 270 also converts an analog reading signal provided from amplifying unit 260 into encoded read data (ERD). A servo address mark (SAM) detecting unit 310, which is connected to read/write channel circuit 270, receives the encoded read data (ERD) to detect a servo address mark (SAM) on disk 240, and generates and outputs a servo address mark (SAM) pulse corresponding to detection of the servo address mark (SAM). A servo timing generating counter 320 is connected to servo address mark (SAM) detecting unit 310, and starts a counting operation in response to the servo address mark (SAM) pulse to thereby output a first count value. A first register 380 temporarily stores a predetermined reference value provided from central processing unit (CPU) 210. The predetermined reference value represents a period from generation of the servo address mark (SAM) pulse to a middle portion of a synchronization (SYNC) signal of a next servo sector. A comparator 330 compares the reference value from first register 380 with the first count value provided from servo timing generating counter 320. When the predetermined reference value and the first count value are equal, comparator 330 generates and outputs an end of servo sector (ENDS) pulse. A servo address mark (SAM) detection window generating unit 340 is connected to comparator 330 and servo address mark (SAM) detecting unit 310. Servo address mark (SAM) detection window generating unit 340 generates a servo address mark (SAM) detection window signal and provides the servo address mark (SAM) detection window signal to servo address mark (SAM) detecting unit 310 in response to the end of servo sector (ENDS) pulse provided from comparator 330, and disables generation of the servo address mark (SAM) detection window signal in response to generation of the servo address mark (SAM) pulse by servo address mark (SAM) detecting unit 310. A window length counter 350 begins a counting operation in response to receipt of the end of servo sector (ENDS) signal from comparator 330 and outputs a second count value. Window length counter 350 terminates the counting operation in response to receipt of the servo address mark (SAM) pulse. An adder 360 receives the second count value provided from window length counter 350 and the reference value provided from first register 380, adds the two values and outputs an added value. A second register 370 receives and temporarily stores the added value provided from adder 360.

FIG. 3 is a timing diagram illustrating operations of the components of FIG. 2. As shown in FIG. 3, a servo sector on the disk recording medium is generally comprised of a synchronization (SYNC) section containing the synchronization (SYNC) signal, a servo address mark (SAM) section containing the servo address mark (SAM), gray code and a burst section. FIGS. 4A through 4C are detailed circuit diagrams illustrating the structure of the spindle motor driving control circuit of FIG. 2 described above. An explanation of a preferred embodiment of the present invention will now be described in detail with reference to FIGS. 2 through 4C.

First, after power is supplied to the disk drive recording device, central processing unit (CPU) 210 provides a motor enable signal to motor driving unit 220. Motor driving unit 220 then drives spindle motor 230 to a constant rotational velocity. When spindle motor 230 reaches a constant velocity, that is, a velocity that fails within a prescribed range, motor driving unit 220 generates a ready signal. According to an exemplary embodiment, the ready signal is generated when the rotational velocity of spindle motor 230 exceeds 90% of the prescribed rotational velocity. Upon generation, the ready signal is transmitted to second register 370. Central processing unit (CPU) 210 checks second register 370 at every interrupt.

Signals read from the servo sector of disk 240 via head 250 are then provided to read/write channel circuit 270 through amplifying unit 260. Next, the read signals are digitalized by an automatic gain controller (AGC; not shown), a differentiator (not shown) and a peak detector (not shown) within read/write channel circuit 270. Read/write channel circuit 270 then outputs encoded read data (ERD) to servo address mark (SAM) detecting unit 310. When a servo address mark (SAM) is detected from the encoded read data (ERD), servo address mark (SAM) detecting unit 310 generates a servo address mark (SAM) pulse, as shown in FIG. 3, and provides the servo address mark (SAM) pulse to servo timing counter 320 to thereby start the counting operation. Central processing unit (CPU) 210 loads, at the initial state, the prescribed reference value into first register 380. As stated above, the reference value represents a period from the generation of the servo address mark (SAM) pulse to a middle portion of the synchronization (SYNC) signal of a next servo sector. This period is shown as x in FIG. 3. Comparator 330 receives the first count value provided from servo timing generating counter 320 and the reference value provided from first register 380, and compares the two values. When the two values are equal, comparator 330 generates the end of servo sector (ENDS) pulse and provides the end of servo sector (ENDS) pulse to servo address mark (SAM) detecting window generating unit 340 and window length counter 350.

Servo address mark (SAM) detection window generating unit 340 provides the servo address mark (SAM) detection window signal to servo address mark (SAM) detecting unit 310 in response to the end of servo sector (ENDS) pulse. Servo address mark (SAM) detecting unit 310 is enabled by the servo address mark (SAM) detection window signal and responds by performing an operation for detecting the servo address mark (SAM) from the encoded read data (ERD) received from read/write channel circuit 270.

As servo address mark (SAM) detection window generating unit 340 generates the servo address mark (SAM) detection window signal in response to the end of servo sector (ENDS) pulse, window length counter 350 is enabled to begin the counting operation. Window length counter 350 terminates the counting operation in response to the servo address mark (SAM) pulse received from servo address mark (SAM) detecting unit 310. Adder 360 then adds the second count value provided from window length counter 350 and the reference value provided from first register 380, to thereby output the added value to second register 370. Accordingly, central processing unit (CPU) 210 accesses second register 370, and can thereby determine the cycle of the servo sector.

As an example, if the prescribed rotational velocity of the spindle motor is 5400 rpm, a vibration margin for the spindle motor can be obtained by the following equations.

That is, when the rotational velocity is 5400 rpm, one revolution occurs every 11.11 milliseconds (ms). Assuming that the number of servo sectors detected during one revolution is 72, one servo sector interval occurs during rotation every (11.11 ms)/(72)=154.3 microseconds (.mu.s). Therefore, if the vibration tolerance of the spindle motor is determined to be +/-0.1%, this results in a margin equal to 154.3 .mu.s +/-154.3 nanoseconds (ns). Moreover, assuming the clock frequency of the servo timing counter is 24 MHz, one clock cycle occurs every 41.6 ns. Consequently, the vibration margin (in terms of clock cycles) equals (154.3 ns)/(41.6 ns)=3.7 clock cycles.apprxeq.+/-3 clock cycles.

The window length count value (which is the second count value mentioned above) as shown in FIG. 3 can have, for example, a, b and c values. The a and b values of FIG. 3 are both included within the vibration margin of the spindle motor, but when the c value (or z value) is read, central processing unit (CPU) 210 senses that the servo address mark (SAM) is missed (i.e., pseudo SAM) from an interrupt and therefore ignores the c value. Central processing unit (CPU) 210 generally includes the x+y value as shown in FIG. 3, by which the variation value of the vibration can be detected.

The operation of the preferred embodiment of the present invention will now be described in detail with reference to FIGS. 4A through 4C.

During an initial state, power is supplied to the disk drive recording device and a power on reset (POR) signal is provided to servo address mark (SAM) detecting unit 310. Servo address mark (SAM) detecting unit 310 is enabled by the servo address mark (SAM) detection window signal to detect the servo address mark (SAM), and output a servo address mark (SAM) enable signal corresponding to the detected servo address mark (SAM) to a first D flip-flop 401. First D flip-flop 401 then transmits a logic "high" signal to a first AND gate 403 during an input interval of the servo address mark (SAM) enable signal. First AND gate 403, which has received the logic "high" signal, also receives a 24 MHz clock signal (CK24M) to thereby output a clock signal to a clock terminal of servo timing generating counter 320, which acts as a 13-bit counter. Servo timing generating counter 320 counts the clock signals (CK24M) to thereby output the first count value to comparator 330.

Comparator 330 receives the first count value from servo timing generating counter 320 and the reference value from first register 380, and compares the two values. If the two values are equal, comparator 330 outputs a logic "high" signal from an XEQ output terminal. A second flip-flop 405 receives the logic "high" signal from comparator 330 in synchronization with an inverse clock signal (CK24MB), and outputs the synchronized signal as the end of servo sector (ENDS) pulse. The inverse dock signal (CK24MB) can be generated by inverting the clock signal (CK24M) through an inverter 437, as shown in FIG. 4C. The end of servo sector (ENDS) pulse resets servo timing generating counter 320 and servo address mark (SAM) detecting unit 310, and is provided to the clock terminal of a third D flip-flop 407. An inverse power on reset signal (/POR), a reset signal (RST) and an inverse reset signal (RSTB) can be generated from the power on reset (POR) signal and the end of servo sector (ENDS) pulse by using an inverter 431, an OR gate 433, and an inverter 435, as shown in FIG. 4B.

A logic "high" signal output from third D flip-flop 407 is synchronized with the inverse clock signal (CK24MB) in a fourth D flip-flop 409 and is output to a second AND gate 411. Second AND gate 411 receives the latch-output from fourth D flip-flop 409 and the clock signal CK24M and performs a logical AND operation on the two signals. Servo address mark (SAM) detection window generating unit 340, which operates as an 8-bit counter, receives the output from second AND gate 411 at a clock terminal.

Central processing unit (CPU) 210 enables a given reference count value, which represents the length of the servo address mark (SAM) detection window, to be input to a window length comparator 415 through a third register 413 to control the servo address mark (SAM) window length. Window length comparator 415 compares the reference count value with the count value provided from servo address mark (SAM) detection generating unit 340. If the two values are equal, window length comparator 415 outputs a logic "high" signal to a fifth D flip-flop 417. The output from window length comparator 415 is synchronized with the inverse clock signal (CK24MB) in fifth D flip-flop 417. Next, the latched output from fifth D flip-flop 417 is synchronized with the dock signal (CK24M) and the inverse dock signal (CK24MB) in a sixth D flip-flop 419 and a seventh D flip-flop 421, respectively. The output from seventh D flip-flop 421 is provided to a third AND gate 423 where it is logically ANDed with an inverse servo address mark (/SAM) pulse and the inverse reset signal (RSTB). The output from third AND gate 423 is then provided to a reset terminal of servo address mark (SAM) detection window generating unit 340. Moreover, the output from seventh D flip-flop 421 resets third D flip-flop 407 through fourth AND gate 425 to stand-by for the next end of servo sector (ENDS) pulse.

Additionally, the count value from servo address mark (SAM) detection window generating unit 340 is latched in an eighth D flip-flop 427 to thereby be provided to adder 360 in accordance with the servo address mark (SAM) pulse. Adder 360 adds the reference value provided from first register 380 and the latch-output from eighth D flip-flop 427 to thereby output the added value to second register 370.

Finally, central processing unit (CPU) 210 accesses second register 370 and senses the cycle of the servo sector and the velocity of spindle motor 230 based on the added value. Central processing unit (CPU) 210 determines whether a read or write operation is possible based on the sensed velocity of spindle motor 230, and accordingly controls the rotational velocity of spindle motor 230.

As described above, the present invention has an advantage in that the spindle motor can be controlled to rotate at a constant velocity by precisely sensing the range of errors of the motor driving unit generated while rotating the recording disk at a high velocity, and enhance the reliability of the reference signal for determining whether or not the spindle motor rotates at the constant velocity. Furthermore, there is an advantage of enhanced reliability of data in the disk drive recording device rotating at a high velocity by precisely compensating for vibrations by using the digitalized encoded read data (ERD) read out through the head.

While there have been illustrated and described what are considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. In addition, many modifications may be made to adapt a particular situation to the teaching of the present invention without departing from the central scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out the present invention, but that the present invention includes all embodiments falling within the scope of the appended claims.