Spindle Motor Control System for Magnetic Disk Apparatus

The present invention relates to a spindle motor control system for a magnetic disk apparatus and, more particularly, to a spindle motor control system for controlling a plurality of disk apparatuses to be driven in synchronism with each other.

In a conventional spindle motor control system for a magnetic disk apparatus, speed control is performed for each spindle motor within the range of upper and lower limits of the rotation speed of the spindle motor, and then synchronization between the respective spindle motors is controlled. The rotation speeds of the plurality of spindle motors differ from each other and variations in rotation speed also differ from each other because loads acting on the motors are different. Therefore, it is difficult to maintain the rotation speeds and the phases of the plurality of spindle motors coincident with each other for a long period of time.

The present inventor has invented a multi-spindle synchronization control system which eliminates the above drawback of the conventional technique and can easily and accurately synchronize a plurality of magnetic disk units and filed a patent application for the system on June 17, 1988 (U.S. patent application Ser. No. 207,984).

It is a principal object of the present invention to improve the multi-spindle synchronization control system according to the above invention and to provide a higher-performance spindle motor control system.

In order to achieve the above object of the present invention, there is provided a spindle motor control system for a magnetic disk apparatus comprising at least one magnetic disk unit which outputs an index signal upon rotation of a spindle therein and inputs a control signal for controlling rotation of the spindle motor by the clock signal, and control means for inputting the index signal from the at least one magnetic disk unit to output the control signal, the control means comprising a frequency generator for generating a master clock signal of a predetermined frequency, a first frequency divider for frequency-dividing the master clock signal from the frequency generator to generate a plurality of frequency-divided signals, a second frequency divider for frequency-dividing one of the plurality of frequency-divided signals to generate a master index signal upon each rotation of the spindle motor, a time interval detector for detecting a time interval between the master index signal and the index signal output from the at least one magnetic disk unit and outputting a phase control signal and a select signal corresponding to the detected time interval, a data selector for selecting and outputting one of the plurality of frequency-divided signals in accordance with the select signal, a clock window circuit for masking the master clock signal from the frequency generator in accordance with the phase control signal, the master index signal, and an output signal of said data selector, and a third frequency divider for frequency-dividing the output from the clock window circuit to output the clock signal to the magnetic disk unit.

FIG. 1 is a block diagram showing an overall arrangement of an embodiment of the present invention;

FIG. 2 is a block diagram showing an embodiment of a control circuit shown in FIG. 1;

FIG. 3 is a block diagram showing an embodiment of a time interval detector shown in FIG. 2;

FIGS. 4(a) to 4(h) are timing charts for explaining an operation of the circuit shown in FIG. 3;

FIG. 5 is a circuit diagram showing an embodiment of a clock window circuit shown in FIG. 2; and

FIGS. 6(a) to 6(i) are timing charts for explaining an operation of the circuit shown in FIG. 5.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an arrangement of an embodiment of the present invention.

In FIG. 1, a plurality of magnetic disk units #0 to #M having the same arrangement are connected to a control circuit 10.

In a magnetic disk unit #0, a plurality of magnetic disks 2 mounted on a spindle 1 are rotated by a spindle motor 3. Rotation of the spindle motor 3 is controlled by an output signal from a power amplifier 4 for driving the spindle motor, and a rotation state of the spindle motor 3 is detected by a rotation detector 5. The rotation detector 5 outputs a plurality of pulse trains synchronized with rotation of the spindle motor 3. The power amplifier 4 is controlled by a PLL (Phase Locked Loop) circuit 6 for controlling the rotation speed of the spindle motor 3. A servo head 7 reads a servo pattern (not shown) written on the servo surface of the magnetic disk 2 and supplies the read signal to a pattern detector 9 through a servo circuit 8. The pattern detector 9 outputs a disk index pulse #0DI to the control circuit 10 on the basis of the above input signal. Similarly, each of index pulses #1DI to #MDI output from the other magnetic disk units #1 to #M, respectively, is output to the control circuit 10.

FIG. 2 shows an embodiment of the control circuit 10 shown in FIG. 1. Referring to FIG. 2, the control circuit 10 comprises: a frequency generator 11 consisting of a quartz oscillator for generating a signal MASTER 1T CLK of a predetermined frequency; a frequency divider 12 for frequency-dividing the signal MASTER 1T CLK output from the frequency generator 11 into fractions of 2.sup.1, 2.sup.2, . . . , 2.sup.N and outputting frequency-divided signals 2T CLK, 4T CLK, . . . , NT CLK; a frequency divider 14 for frequency-dividing the 1/2.sup.N -frequency-divided signal NT CLK into a signal corresponding to one rotation of the spindle motor 3 and outputting this signal as master index signal MI; a time interval detector 15.sub.i (i=0 to M) for detecting a time interval between the master index signal MI and an index signal #iDI output from the disk unit #i and outputting a phase control signal 18.sub.i and a predetermined select signal 19.sub.i corresponding to the time interval; a data selector 13.sub.i (i=0 to M) for selecting one of the output signals 2T CLK, 4T CLK, . . . , KT CLK (K<N) from the frequency divider 12 in accordance with the select signal 19.sub.i and outputting a selected signal 34.sub.i ; a clock window circuit 16.sub.i (i=0 to M) for receiving the master index signal MI, the signal MASTER 1T CLK from the frequency generator 11, the output signal 34.sub.i from the data selector 13.sub.i and the phase control signal 18.sub.i and outputting a signal GATED 1T CLK 32.sub.i obtained by masking the signal MASTER 1T CLK for a time period in accordance with the signals input therein; and a frequency divider 17.sub.i (i=0 to M) for 1/2.sup.N -frequency-dividing the signal GATED 1T CLK 32.sub.i and outputting a signal #i CLK to the magnetic disk unit #i.

The output signal MASTER 1T CLK from the frequency generator 11 is supplied to the frequency divider 12 and the clock window circuits 16.sub.0, 16.sub.1, . . . , 16.sub.M. The frequency divider 12 frequency-divides the signal MASTER 1T CLK (the frequency of which is generally 10,000 times or more a rotation frequency of the spindle motor 3) and outputs the signals 2.sup.1 T, 2.sup.2 T, . . . , 2.sup.N T CLK. The signals 2.sup.1 T, 2.sup.2 T, . . . , 2.sup.K T CLK (K<N) are commonly supplied to data terminals of the data selectors 13.sub.0, 13.sub.1, . . . , 13.sub.M.

The frequency divider 14 frequency-divides the signal 2.sup.N T CLK, one of the output signals from the frequency divider 12, and outputs the master index signal MI which has a pulse generated for each rotation of the spindle motor 3. The master index signal MI is supplied to the time interval detectors 15.sub.0, 15.sub.1, . . . , 15.sub.M.

The time interval detector 15.sub.i (i=0 to M) detects a time interval .DELTA.T between the master index signal MI and the drive index signal #iDI from the disk unit #i and checks whether the time interval .DELTA.T falls within the range of desired time interval 0 to t.sub.0. If the time interval .DELTA.T falls outside the desired range, the time interval detector 15.sub.i outputs the phase control signal 18.sub.i and the predetermined select signal 19.sub.i corresponding to the time interval .DELTA.T.

FIG. 3 is a circuit diagram showing an embodiment of the time interval detector 15.sub.0 shown in FIG. 2. FIGS. 4(a) to 4(h) are timing charts for explaining an operation of the circuit shown in FIG. 3. Referring to FIGS. 3 to 4h, in the time interval detector 15.sub.0, the master index signal MI is supplied to the data terminal of a flip-flop (to be referred to as an FF hereinafter) 20 and the drive index signal #0DI from the disk unit #0 is supplied to the clock terminal of the FF 20 and one input terminal of an AND gate 21. A Q output signal from the FF 20 is supplied to the other input terminal of the AND gate 21. In this manner, if the drive index signal #0DI does not rise while the master index signal MI is active ("1"), the AND gate 21 outputs the drive index signal #0DI as the phase control signal 18.sub.0. The phase control signal 18.sub.0 is supplied to the clock window circuit 16.sub.0 and the clock terminal of an FF 22 in the time interval detector 15.sub.0. A Q output from the FF 22 is supplied to the data terminal and the clear terminal of an FF 23. The master index signal MI is supplied to the clock terminal of the FF 23. A Q output from the FF 23 is supplied to the clear terminal of the FF 22. In this manner, a signal which is kept active from the rise of the phase control signal 18.sub.0 (drive index signal #0DI) to the rise of the master index signal MI, i.e., a .DELTA.T detection signal 24 is obtained at the Q output of the FF 22. A microprocessor 25 receives the .DELTA.T detection signal 24 and outputs a select signal 19.sub.0 corresponding to the duration of the input signal. For example, assume that a time period T.sub.0 of one rotation of a disk is equally divided into eight time intervals. In this case, the microprocessor 25 outputs a select signal 19.sub.0--1 if 0<.DELTA.T.ltoreq.T.sub.0 /8, a select signal 19.sub.0 -2 if T.sub.0 /8<.DELTA.T.ltoreq.T.sub.0 /4, a select signal 19.sub.0 -3 if T.sub.0 /4<.DELTA.T.ltoreq.T.sub.0 /2, and a select signal 19.sub.0 -4 if T.sub.0 /2<.DELTA.T<T.sub.0, and supplies the select signal to a select terminal SEL of the data selector 13.sub.0 shown in FIG. 2. The arrangements and operations of the time interval detectors 15.sub.1 to 15.sub.M are the same as those of the time interval detector 15.sub.0.

Referring to FIG. 2, the data selector 13.sub.0 outputs one of the clocks 2T CLK to 2KT CLK in accordance with the select signal 19.sub.0. For example, the data selector 13.sub.0 selects the signals 2T CLK, 4T CLK and 8T CLK in accordance with the select signals 19.sub.0 -1, 19.sub.0 -2 and 19.sub.0 -3, respectively. That is, if the time interval represented by the .DELTA.T detection signal 24 is long, a low-frequency clock which is frequency-divided by a large number is selected, and if it is short, a high-frequency clock which is frequency-divided by a small number is selected. The output signal from the data selector 13.sub.0 is supplied to the clock window circuit 16.sub.0. The clock window circuit 16.sub.0 operates in accordance with the phase control signal 18.sub.0 and the master index signal MI in addition to the output signal from the data selector 13.sub.0 and masks the signal MASTER 1T CLK for a time period corresponding to the pulse width of the output signal 34.sub.0 from the data selector 13.sub.0. The other data selectors 13.sub.1 to 13.sub.M similarly operate.

FIG. 5 is a circuit diagram showing an embodiment of the clock window circuit 16.sub.0 shown in FIG. 2. FIGS. 6(a) to 6(i) are timing charts for explaining an operation of the circuit shown in FIG. 5. Referring to FIG. 5, the phase control signal 18.sub.0, the master index signal MI, and the output signal 34.sub.0 from the data selector 13.sub.0 are supplied as clocks to the clock terminal of an FF 26, the clock terminal of an FF 27, and the clock terminals of FFs 28 and 29, respectively, of the clock window circuit 16.sub.0. A Q output from the FF 26 is supplied to the data terminal of the FF 27 and the clear terminals of the FFs 27, 28 and 29. A Q output from the FF 29 is supplied to the clear terminal of the FF 26. By ANDing a Q output from the FF 28 and the MASTER 1T CLK from the frequency generator 11, a pulse train from which pulses corresponding to one period of the output signal 34.sub.0 from the data selector 13.sub. 0 are masked, i.e., a signal GATED 1T CLK 32.sub.0 is obtained. The signal GATED 1T CLK 32.sub.0 is frequency-divided by the frequency divider 17 and supplied as a reference clock pulse #0 CLK of a PLL circuit 6 of the magnetic disk unit #0. The phase of the reference clock pulse #0 CLK is delayed at masked portions by time intervals (t.sub.1 and t.sub.2 in FIG. 6(i)) corresponding to the numbers of masked pulses of the MASTER 1T CLK. As the number of masked pulses is increased, the phase delay is increased. Upon a known operation of the PLL circuit 6, a portion to be controlled, i.e., a rotation phase of the spindle motor 3 of the disk unit #0 is delayed. That is, the rotation phase of the spindle motor 3 can be controlled by controlling the phase of the reference clock pulse #0CLK of the PLL circuit 6 by the above means.

The arrangements and operations of the clock window circuits 16.sub.1 to 16.sub.M are identical to those of the clock window circuit 16.sub.0.

As has been described above, according to the present invention, the time interval between the master index signal and the drive index signal is detected, and is changed in accordance with the detected time interval, thereby changing the degree of phase delay of the reference clock pulse of the PLL circuit for controlling rotation of the spindle motor. As a result, without reducing precision of phase matching between drive indexes of a plurality of disk units, synchronous drive can be effectively performed while a time period required for a phase matching is reduced.