US 5,654,665 AGrant
Programmable Logic Bias Driver
Issue Date:1997-08-05
•3 Claims
•3 Drawing Sheets
Abstract
A biasing system for a differential amplifier includes an NMOS current source and a gate bias voltage generator. The gate bias voltage generator produces a bias voltage VNCS to control the NMOS current source. The gate bias generator includes a reference current generator to produce a reference current relatively independent of supply voltage variations. A temperature compensator regulates the reference current to provide a temperature compensated current. A current mirror duplicates the temperature compensated current to a bias voltage generator. The bias voltage generator generates the bias voltage.
Metadata
Assignee
- Dynachip Corporation
Inventors
- Suresh M. Menon
- Tsung Chuan Whang
Application Information
Application Number:US 4441117
Filing Date:1995-05-18
Priority Date:1995-05-18
Art Unit:254
Classifications
IPC:
G05F 302
Field of Search:
327323538;540;541;543;545;546;539312;313;315
Patent Drawings (3 sheets)
Description
Cross-Reference to Related Applications
The following applications, assigned to the present Assignee, HIGH SPEED PROGRAMMABLE LOGIC ARCHITECTURE, Ser. No. 08/188,499, Filed Jan. 27, 1994, and BiCMOS REPEATER CIRCUIT FOR A PROGRAMMABLE LOGIC DEVICE, Ser. No. 08/352,402, Filed Dec. 8, 1994, are hereby expressly incorporated by reference for all purposes.
Background of the Invention
This invention relates to programmable logic, and in particular to a simple bias driver for a current source that has no feedback and provides good supply rejection.
As described in the incorporated patent applications, programmable logic devices include thousands of repeaters, buffers and logic blocks distributed across a fairly large semiconductor structure. Many of the elements making up various programmable logic circuits described in the co-pending patent applications use bipolar differential amplifiers.
FIG. 1 is a schematic diagram of one example of a conventional differential amplifier 10. Differential amplifier 10 is a common configuration designed to amplify a difference voltage between two input signals. Differential amplifier 10 includes two NPN transistors (T.sub.1 and T.sub.2), two collector resistors (R.sub.C1 and R.sub.C2) coupling collectors of the transistors to a first reference voltage, and a current source 12 coupling emitters of the transistors to a second reference voltage. The input signals are provided to the bases of transistors T.sub.1 and T.sub.2. An output taken at the collector of transistor T.sub.2 provides a voltage that depends upon the difference of the input signal voltages.
The prior art recognized that the use of current source 12 as a bias current provides differential amplifier 10 with a common-mode gain that is about zero. There are many types of possible current sources that could be used with differential amplifier 10.
FIG. 2 is a schematic diagram of one typical type of current source 12. Current source 12 includes an NPN transistor T.sub.3 and an emitter resistor R.sub.E. Resistor R.sub.E couples the emitter of transistor T.sub.3 to the second reference voltage. To control current source 12, a bias circuit must provide both a base bias current and a base bias voltage.
There are a number of drawbacks when using current source 12, or similar types of current sources. These drawbacks relate to bias signal distribution, size, and operation. The large size of typical programmable logic devices and the use of differential amplifiers across the entire semiconductor structure requires distribution of the bias current and the bias voltage. There are many well-known problems with distribution of bias signals, not the least of which is compensation of capacitive loading of long lead lines that interconnect the bias circuit and the current sources used with each of the thousands of differential amplifiers.
With respect to the size drawback, current source 12 includes transistor T.sub.3 and resistor R.sub.E. Together these elements require a relatively large amount of space on the semiconductor structure. When the number of current sources is large, the space required for each current source becomes significant.
Regarding the operational drawback, under particular conditions, transistor T.sub.3 can go into saturation. For a circuit integrated on a single semiconductor structure, it is undesirable for a bipolar transistor to operate in its saturation region as charge gets dumped into a substrate of the semiconductor structure. It is undesirable to dump charge into the substrate. The likelihood of a transistor going into saturation is increased when turning the transistor on and off. Programmable logic devices include the ability to turn various differential amplifiers on and off, typically by turning its associated current source on and off.
Summary of the Invention
The present invention provides an improved current source for differential amplifiers used in logic elements of a programmable logic device, as well as an improved master bias system for control of the improved current source.
According to one aspect of the invention, a current source for a differential amplifier includes a single NMOS transistor. The NMOS transistor includes a source, a drain and a gate. The NMOS transistor current source requires only a gate bias voltage to control operation. Distribution difficulties of the gate bias voltage are minimized because the gate has a very large input impedance, meaning that virtually no gate bias current is required. Thus, effects from capacitive loading of distribution lines is minimized. The other drawbacks of the bipolar current source are reduced or eliminated. The NMOS transistor takes up less space than the bipolar transistor and resistor combination, and the NMOS transistor will not go into saturation and dump charge into the substrate.
According to another embodiment of the present invention, an improved and simplified bias voltage generator is disclosed that provides for temperature regulation and supply rejection without use of feedback. The improved bias voltage generator includes a circuit for biasing a plurality of differential amplifiers distributed across a semiconductor device having a programmable logic array. The circuit includes a plurality of NMOS transistor current sources coupled to each of the plurality of differential amplifiers, each NMOS transistor current source coupled to a particular one differential amplifier and having a gate terminal for receiving a bias voltage for controlling a bias current in the particular one differential amplifier. A bias voltage generator, coupled to each of the plurality of NMOS transistor current sources, generates the bias voltage in response to a regulated current. A current generator generates a reference current. A temperature compensator, coupled to the current generator, produces a regulated current from the reference current. A current mirror, coupled to the temperature compensator and to the bias voltage generator, mirrors the regulated current produced in the temperature compensator to the bias voltage generator.
Reference to the remaining portions of the specification, including the drawing and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawing. In the drawing, like reference numbers indicate identical or functionally similar elements.
Brief Description of the Drawings
FIG. 1 is a schematic diagram of a conventional differential amplifier that uses a current source;
FIG. 2 is a schematic diagram of a conventional current source;
FIG. 3 is a block diagram of a preferred embodiment of the present invention including an NMOS current source for a differential amplifier and a bias circuit for the NMOS current source;
FIG. 4 is detailed schematic diagram of the bias circuit for the NMOS current source; and
FIG. 5 is a block diagram illustrating a preferred bias distribution system according to the present invention.
Description of the Preferred Embodiment
FIG. 3 is a block diagram of a preferred embodiment of the present invention including an NMOS current source 100 for a differential amplifier 105 and a bias circuit 110 for NMOS current source 100. NMOS current source 100 includes an NMOS transistor having a source coupled to a ground potential and a drain coupled to differential amplifier 105. Differential amplifier 105 may be configured as shown by transistors T.sub.1 and T.sub.2 and resistors R.sub.C1 and R.sub.C2 in FIG. 1, or may include other configurations, some of which are well known in the prior art. A gate bias voltage (V.sub.NCS) applied to a gate of the NMOS transistor controls a bias current of differential amplifier 105. Bias circuit 110 generates the gate bias voltage to control NMOS current source 100.
Bias circuit 110 includes a reference current generator 120, a temperature compensator 130, a current mirror 140, and a bias voltage generator 150 to generate the gate bias voltage. Reference current generator produces a reference current I.sub.REF from a reference voltage (e.g., +V.sub.cc). The preferred embodiment of the present invention operates using voltage levels for V.sub.cc appropriate for emitter-coupled logic (ECL). Here, V.sub.cc is 4.50 volts .+-.7%. It is important that the reference current I.sub.REF not vary due to variations in V.sub.cc. Reference current generator 120 is designed to provide reference current I.sub.REF having little variation due to changes in V.sub.cc.
Additionally, process variations in resistor components of differential amplifier 105 will affect the differential gain it experiences. Reference current generator 120 is designed to adjust the reference current I.sub.REF to adjust for resistor variations. Details regarding the supply rejection and process variation adjustment are provided below.
Temperature compensator 130 is responsive to the reference current to produce a temperature-compensated current (I.sub.TEMP). It is well-known that temperature changes will affect operation of semiconductor elements, such as those used in the preferred embodiment. In semiconductor devices, especially those integrated together on a single monolithic semiconductor structure, it is possible to wholly or partially compensate for temperature variations. Temperature compensator 130 regulates I.sub.TEMP to compensate for temperature variations. In the preferred embodiment, temperature compensator 130 includes two parts: a first part that adjusts I.sub.TEMP inversely as temperature changes, and a second part that varies I.sub.TEMP directly as temperature changes. The contributions of these two parts are dependent upon the overall design requirements. It is possible to balance the two parts so that I.sub.TEMP has minimal or zero change due to temperature variations. For other embodiments, the contribution of one of the parts will be greater than the other part to provide a net change to I.sub.TEMP in response to temperature variations. The change in I.sub.TEMP can be directly or inversely related to temperature changes, depending upon which part has the larger contribution.
Current mirror 140 responds to I.sub.TEMP to establish a mirrored current I.sub.MIRROR where I.sub.MIRROR equals I.sub.TEMP * CONSTANT. In the preferred embodiment, the constant is about equal to one, so I.sub.MIRROR equals I.sub.TEMP . Depending upon particular designs, I.sub.MIRROR may be made larger or smaller than I.sub.TEMP.
Bias voltage generator 150 responds to I.sub.MIRROR to generate the gate bias voltage for NMOS current source 100. Thus, the gate bias voltage 150 is a derived from a regulated and process-variation-adjusted reference current. The magnitude of the gate bias voltage affects the current in NMOS current source 100, compensating for temperature or process variations. The gate bias voltage varies little with variations in supply voltage, and there is no feedback from current source 100 or differential amplifier 102 to control the magnitude of the gate bias voltage.
FIG. 4 is detailed schematic diagram of the bias circuit 110 for generation of the gate bias voltage for NMOS current source 100 shown in FIG. 3. Reference current generator 120 includes three NPN bipolar transistors (Q.sub.1, Q.sub.2, and Q.sub.3), two resistors (R.sub.1 and R.sub.REF), and a PMOS current mirror including two PMOS transistors (Q.sub.4 and Q.sub.5).
A first terminal of resistor R.sub.1 is coupled to a first voltage reference V.sub.cc. Transistor Q.sub.1 and transistor Q.sub.2 each have a collector, an emitter and a base with the base coupled to the collector. The emitter of transistor Q.sub.1 is coupled to a second voltage reference V.sub.EE. The emitter of transistor Q.sub.2 is coupled to the collector of transistor Q.sub.1. The collector of transistor Q.sub.2 is coupled to a second terminal of resistor R.sub.1. In the preferred embodiment, first reference voltage V.sub.cc is about 4.50 volts, and second reference voltage V.sub.EE is about 0.00 volts.
A first terminal of resistor R.sub.REF is coupled to the second voltage reference V.sub.EE. An emitter of transistor Q.sub.3 is coupled to a second terminal of resistor R.sub.REF. A base of transistor Q.sub.3 is coupled to the collector of transistor Q.sub.2.
PMOS transistor Q.sub.4 and PMOS transistor Q.sub.5 each include a gate, a source and a drain. The sources of transistor Q.sub.4 and transistor Q.sub.5 are coupled to the first reference voltage. The gate of transistor Q.sub.4 is coupled to the gate of transistor Q.sub.5, with the drain of transistor Q.sub.4 coupled to the collector of transistor Q.sub.3.
In operation, the voltage level present at the base of transistor Q.sub.3 is about equal to two V.sub.be (voltage drop from base to emitter in a bipolar transistor), as established by the stack of the two diode-connected transistors Q.sub.1 and Q.sub.2 There is a voltage drop of one V.sub.be between the base of transistor Q.sub.3 to the emitter of transistor Q.sub.3. Therefore, at node A, the voltage potential is about one V.sub.be above the voltage level of second voltage reference V.sub.EE. Thus, resistor R.sub.REF establishes a current I.sub.x that is about equal to V.sub.be divided by the resistance of R.sub.REF. This configuration of the reference current generator results in small variations in current I.sub.x due to changes in the power supply voltage. As described, I.sub.x varies as the value of V.sub.be changes. In the preferred embodiment, V.sub.be varies by about 60 mV per decade change in current at 27.degree. C. Over temperature this variation is governed by the thermal voltage V.sub.T. Thus I.sub.x established by V.sub.be and the resistance of R.sub.REF, is stable.
The current mirror responds to current I.sub.x and establishes the reference current I.sub.REF from the drain of transistor Q.sub.5. I.sub.REF is about equal to I.sub.x multiplied by a constant. In this case, the constant is a number representing the ratio of the gate areas of transistor Q.sub.5 to transistor Q.sub.4. In other words, letting a.sub.4 represent the area of the gate of transistor Q.sub.4 and letting a.sub.5 represent the gate area of transistor Q.sub.5, the constant is about equal to a.sub.5 divided by a.sub.4. Typically, a.sub.4 equals a.sub.5, making the constant equal to one, providing that I.sub.REF about equals I.sub.x.
Temperature compensator 130 includes four NPN bipolar transistors (Q.sub.6, Q.sub.7, Q.sub.8 and Q.sub.9), and resistor R.sub.2. Transistor Q.sub.6 includes a collector and a base coupled to the source of transistor Q.sub.5 of reference current generator 120. An emitter of transistor Q.sub.6 is coupled to V.sub.EE. Transistor Q.sub.7 and transistor Q.sub.8 each include a collector coupled to a summing node (node B), and a base coupled to the base of transistor Q.sub.6. An emitter of transistor Q.sub.8 is coupled to second voltage reference V.sub.EE, with an emitter of transistor Q.sub.7 coupled to a first terminal of resistor R.sub.2. A second terminal of resistor R.sub.2 is coupled to second voltage reference V.sub.EE. Transistor Q.sub.9 is diode-connected, with a base terminal coupled to a collector terminal. An emitter of transistor Q.sub.9 is coupled to the summing node.
In operation, reference current I.sub.REF establishes a bias level (a base bias voltage and a base bias current) for transistor Q.sub.6. Transistor Q.sub.7 and transistor Q.sub.8 operate as special current mirrors to each produce a current (I.sub.7 and I.sub.8, respectively). These are special current mirrors because they are balanced and designed to provide temperature compensation for current I.sub.TEMP. Current I.sub.7 and current I.sub.8 will each be about equal to a constant multiplied by I.sub.REF, similar to the current mirror described above.
However, these constants will be a function of the temperature compensation. As well known, bipolar transistors experience an inverse relationship between current and temperature, referred to as having negative temperature coefficient. Current I.sub.8 will experience a total inverse relationship to temperature as the value of the current is established solely by transistor Q.sub.8. Current I.sub.7 on the other hand, is dependent upon the voltage difference (V.sub.be Q.sub.6 -V.sub.be Q.sub.7) and resistor R.sub.2. By designing the combination of (V.sub.be Q.sub.6 -V.sub.be Q.sub.7) and resistor R.sub.2 appropriately allows for positive temperature coefficient for current I.sub.7.
The summing node adds current I.sub.7 and current I.sub.8 to produce a temperature compensated current I.sub.TEMP. Designing the relative values of the mirroring constants of transistor Q.sub.7 and transistor Q.sub.8, I.sub.TEMP can be made to be relatively invariant with respect to temperature, or to have a net change (either direct or inverse) depending upon the desired implementation.
Transistor Q.sub.9 reduces the voltage seen across transistors Q.sub.8 and Q.sub.7. This minimizes breakdown conditions for these transistors. Breakdown of the collector to emitter junction is process dependent. Transistor Q.sub.9 is optional and used for specific embodiments. In some embodiments, transistor Q.sub.9 may be sized differently or eliminated.
Current mirror 140 includes two PMOS transistors (Q.sub.10 and Q.sub.11). Transistor Q.sub.10 includes a source coupled to first voltage reference V.sub.cc, and a gate and a drain both coupled to the collector of transistor Q.sub.9. Transistor Q.sub.11 includes a source coupled to first voltage reference V.sub.cc and a gate coupled to the gate of transistor Q.sub.10.
Current mirror 140 is responsive to the current I.sub.TEMP produced from temperature compensator 130 to produce a mirror current I.sub.MIRROR. Current I.sub.TEMP generates a gate voltage (V.sub.PCS) at transistor Q.sub.10. The gate voltage V.sub.PCS at transistor Q.sub.11 causes transistor Q.sub.11 to produce current I.sub.MIRROR at the drain terminal. As described above, current I.sub.MIRROR is related to current I.sub.TEMP by a ratio of the gate areas of transistor Q.sub.11 to transistor Q.sub.10. In the preferred embodiment, the areas are made about equal, providing that current I.sub.MIRROR about equals current I.sub.TEMP ,
Bias voltage generator 150 includes an NMOS transistor Q.sub.12. Transistor Q.sub.12 includes a gate and a drain coupled to the drain of transistor Q.sub.11, and a source coupled to second voltage reference V.sub.EE. Current I.sub.MIRROR causes transistor Q.sub.12 to generate the gate bias voltage V.sub.NCS at the drain of transistor Q.sub.12. The gate bias voltage V.sub.NCS is distributed to the gates of the NMOS current sources 100 coupled to differential amplifiers 105.
FIG. 5 is a block diagram illustrating a preferred bias distribution system 200 according to the present invention. Bias distribution system 200 provides the gate bias voltage V.sub.NCS to all of the NMOS current sources of the thousands of differential amplifiers (not shown) in a logic array 205. Logic array 205 is an m.times.n array of logic blocks (not shown) that comprise the programmable logic device. In the preferred embodiment, n and m equal sixteen, making a total of 256 logic blocks. There are m columns (210.sub.i, i equals 1 to m), and n rows (215.sub.j, j equals 1 to n). To further compensate for temperature variations beyond those features described above, bias distribution system 200 implements bias circuit 110 as a first plurality of master bias circuits 220 and as a second plurality of slave bias circuits 230. In the preferred embodiment, there are four master bias circuits 220, two positioned along a left side of logic array 205, and two positioned along a right side of logic array 205. There is one slave bias circuit 230 for each side of each row of logic array 205, for a total of thirty-two slave bias circuits 230.
Each slave bias circuit 230 includes an equivalent to transistor Q.sub.11 and transistor Q.sub.12 shown in FIG. 4. Each master bias circuit 220 includes an equivalent to each of the transistors Q1-10, and resistors R.sub.1, R.sub.2, and R.sub.REF. Master bias circuit 220 distributes the PMOS gate bias voltage V.sub.PCS to selected slave bias circuits 230, which in turn distribute the gate bias voltage to the NMOS current sources 100 shown in FIG. 3. The two master bias circuits 220 on each side provides V.sub.PCS to the slave bias circuits 230 on the same side. Signal lines 250 carry the V.sub.PCS voltage from each master bias circuit 220, with lines 250 from master bias circuits 220 on the same side of logic array 205 being connected to each other. For distribution of the gate bias voltage V.sub.NCS, the outputs of all slave bias circuits 230 are interconnected, providing an interconnection net to the NMOS current sources 100 shown in FIG. 3.
In conclusion, the present invention provides a simple, efficient solution to a problem of bias signal distribution in programmable logic devices. While the above is a complete description of the preferred embodiments of the invention, various alternatives, modifications, and equivalents may be used. Therefore, the above description should not be taken as limiting the scope of the invention which is defined by the appended claims.
Claims
What is claimed is:
1. A circuit for biasing a plurality of differential amplifiers distributed across a semiconductor device having a programmable logic array, wherein each of the differential amplifiers includes an NMOS transistor current source that has a gate terminal for receiving a bias voltage that controls a bias current in the differential amplifier and wherein each of the differential amplifiers includes a load resistor having a resistance that varies due to a semiconductor processing variation effect that occurs during fabrication such that a gain of each of the plurality of differential amplifiers is subject to a variation from an expected value, comprising: a bias voltage generator, coupled to each of the plurality of NMOS transistor current sources, for generating the bias voltage in response to a regulated current; a current generator for generating a reference current, said current generator including a resistor subject to the semiconductor processing variation effect to adjust said reference current to compensate for the variation in the gain; a temperature compensator, coupled to said current generator, for producing said regulated current from said reference current, said temperature compensator further including a first and a second bipolar transistor, each said bipolar transistor including a base, a collector and an emitter, with said collectors of said bipolar transistors coupled to a summing node, and said emitter of said first bipolar transistor coupled to a reference voltage; a resistor, having a first terminal coupled to said emitter of said second bipolar transistor and a second terminal coupled to said reference voltage, and a third bipolar transistor, having a base coupled to a collector thereof and an emitter coupled to said reference voltage, said collector of said third bipolar transistor coupled to said current generator for establishing a base voltage and base current; wherein said bases of said first and second bipolar transistors are each coupled to said base of said third bipolar transistor, and said first bipolar transistor and said second bipolar transistor are responsive to said base current and said base voltage to generate, respectively, a first current through said first bipolar transistor and a second current through said second bipolar transistor and said resistor such that said regulated current is produced at said summing node as a sum of said first current and said second current with said first current having an inverse relationship to a temperature variation of the semiconductor device and said second current having a direct relationship to said temperature variation; and a current mirror, coupled to said temperature compensator and to said bias voltage generator, for mirroring said regulated current produced in said temperature compensator to said bias voltage generator.
2. The biasing circuit of claim 1 wherein said first current and said second current are balanced such that a magnitude of a temperature-induced variation of said first current about equals a magnitude of a temperature-induced variation of said second current so that said regulated current has a minimal variation due to temperature.
3. The biasing circuit of claim 1 wherein said first current and said second current are balanced such that a magnitude of a temperature-induced variation of said first current is less than a magnitude of a temperature-induced variation of said second current so that said regulated current has a net variation that is directly related to temperature.
Patent Citations (11)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4251743 | 1981-02-01 | Hareyama | |
| US4325018 | 1982-04-01 | Schade, Jr. | |
| US4763021 | 1988-08-01 | Stickel | |
| US4849684 | 1989-07-01 | Sonntag et al. | |
| US4897596 | 1990-01-01 | Hughes | |
| US4912347 | 1990-03-01 | Morris | |
| US5087830 | 1992-02-01 | Cave et al. | |
| US5109187 | 1992-04-01 | Guliani | |
| US5235222 | 1993-08-01 | Kondoh et al. | |
| US5245273 | 1993-09-01 | Greaves et al. | |
| US5434534 | 1995-07-01 | Lucas |