US 5,568,071 AGrant
Pulse Phase Difference Encoding Circuit
Issue Date:1996-10-22
•65 Claims
•8 Drawing Sheets
Abstract
A pulse phase difference encoding circuit provides a digital signal indicating a phase difference between a first input pulse and a second input pulse. The first input pulse is provided to and circulated in a ring signal delay circuit having a plurality of signal delay elements that are connected in series. Intermediate points between the delay elements provide delayed pulses having different delay times. Upon receiving the second input pulse, a selector selects one delay pulse provided by the delay element at which the first input pulse has arrived, and generates a digital positional signal indicating a position of the selected delay element. The number of rounds of circulation of the first input pulse in the ring signal delay circuit is separately counted. According to the number of rounds of circulation of the first pulse and the positional signal, the digital signal indicating the phase difference between the first and second input pulses is formed.
Metadata
Assignees
- Nippon Soken Inc.
- Nippondenso Co., Ltd.
Inventors
- Kouichi Hoshino
- Takamoto Watanabe
- Yoshinori Ohtsuka
Application Information
Application Number:US 3752526
Filing Date:1995-01-19
Priority Date:1990-01-25
Art Unit:254
Classifications
IPC:
H03K 2100
Field of Search:
37732830732432736844;46;54;55;75;76;111;42;43133;5551776.82265;269;270;3120
Patent Drawings (8 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a circuit for detecting a phase difference between two pulse signals having optional phases, and particularly to a pulse phase difference encoding circuit that can accurately detect the phase difference over a wide range.
2. Description of the Related Art
A prior art technique encodes a phase difference between two pulses PA and PB into a digital signal composed of a plurality of bits that represent a positive or negative shift (difference) between phases of the two pulses PA and PB. The detection range of the phase shift of this technique can be expanded without deteriorating the detection accuracy by increasing the number of bits of the digital signal.
The increase in the number of bits, however, increases circuit scale. If the circuit scale must be kept as it is, the detection range is expandable only by sacrificing the detection accuracy.
When phases of two pulses PA and PB change in response to a change in a physical quantity, it is possible to find the change in the physical quantity by detecting a difference between the phases. Based on this idea, a sensor can be made. This sort of sensor must have a wide detection range and high detection accuracy to respond to sensing elements that cause large phase changes or have a variety of characteristics to cause a large phase difference. Further, for the sake of compactness and economy, the size of the sensor must not be increased excessively:
Summary of the Invention
An object of the present invention is to provide a pulse phase difference encoding circuit for encoding and detecting a phase difference between two pulses, having a wide detection range, compact circuit scale, and high detection accuracy.
In order to accomplish the object, the present invention provides a pulse phase difference encoding circuit comprising a delayed pulse generating ring circuit (1) composed of many signal delay circuits that are connected to one another in a ring shape. A first pulse PA is provided at optional timing to the signal delay circuits and is circulated in the signal delay circuits. The signal delay circuits repeatedly provide a plurality of delayed pulses when the first pulse PA passes through the respective signal delay circuits. The delayed pulses sequentially follow one after another with a delay time of each signal delay circuit.
A counter (2, 21, 22) counts the number of rounds of circulation of the first pulse PA in the delayed pulse generating ring circuit (1).
A pulse selector (3) has a plurality of input lines for receiving the delayed pulses from the delayed pulse generating ring circuit (1), and a plurality of output lines respectively corresponding to the delayed pulses. When a second pulse PB forming an optional phase difference relative to the first pulse PA is provided to the pulse selector (3), the pulse selector selects one delayed pulse that has a special temporal relationship with the second pulse PB out of the delayed pulses provided by the delayed pulse generating ring circuit (1), and changes the voltage of one output line corresponding to the selected delayed pulse.
An encoder (4) receives output signals from the output lines of the pulse selector (3), and provides a binary digital signal indicating the one delayed pulse selected by the pulse selector (3).
The number of rounds of circulation of the first pulse PA in the delayed pulse generating ring circuit at the time when the second pulse PB is provided forms upper bits, and the binary digital signal provided by the encoder (4) forms lower bits. The upper and lower bits form a digital signal indicating a phase difference between the first and second pulses PA and PB.
According to the present invention, the first pulse PA is circulated in the signal delay circuits that are connected to one another in a ring shape. Even if the number of the signal delay circuits is small, i.e., even with a small circuit scale, the counter (2) counts the number of rounds of circulation of the first pulse PA in the signal delay circuits, and the counted number of rounds forms upper bits of a digital signal having a high resolution for indicating a phase difference.
Brief Description of the Drawings
FIG. 1 is a view schematically showing an embodiment of the present invention;
FIG. 2 is a combination of FIGS. 2A and 2B
FIGS. 2A and 2B are circuit diagrams showing a first embodiment of the present invention;
FIG. 3 is a view showing waveforms appearing at various parts of the circuit of FIG. 2;
FIG. 4 is a block diagram showing a second embodiment of the present invention;
FIG. 5 is a block diagram showing a circuit for measuring a physical quantity in response to resistance values, according to the embodiment of the present invention;
FIG. 6 is a view showing waveforms appearing at various parts of the circuit of FIG. 5; and
FIG. 7 is a circuit diagram showing the details of a comparator circuit of FIG. 5.
Description of the Preferred Embodiments
Firstly, an outline of the present invention will be explained with reference to the drawings.
FIG. 1 schematically shows an arrangement of a pulse phase difference encoding circuit according to the present invention. The circuit comprises a delayed pulse generating ring circuit 1 having many signal delay circuits (sometimes referred to as gate delays), a counter 2, a pulse selector 3, and an encoder 4. A terminal 6 receives a first input pulse PA. The delayed pulse generating ring circuit 1 provides a plurality of delayed pulses. A delay time of any one of the delayed pulses is determined by the number of the signal delay circuits (gate delays) passed by the first pulse PA to generate the one delayed pulse.
The pulse selector 3 receives the delayed pulses, as well as a second pulse PB through a terminal 8. The second pulse PB is delayed behind the first pulse PA. Upon receiving the second pulse PB, the pulse selector 3 selects one input corresponding to one delayed pulse just triggered by the first pulse PA in the delayed pulse generating ring circuit 1, and provides the encoder 4 with a signal indicating the selected input. The encoder 4 then generates a binary digital signal indicating the selected input.
At end point 5 of the delayed pulse generating ring circuit 1 is connected to an OR circuit 1a, thereby connecting the signal delay circuits to one another in a ring shape. With a cumulative delay time of all the signal delay circuits, the first pulse PA again appears at the start (a left end in FIG. 1) of the delayed pulse generating ring circuit 1.
A clock terminal of the counter 2 receives an output from the end point 5, and the counter 2 divides a frequency of the received output and produces an output indicating the number of rounds of circulation of the first signal PA. Namely, an output 10 of the counter 2 provides upper bits for an output 9 of the encoder 4.
The delayed pulse generating ring circuit 1 is reset by zeroing an input 7 of a NAND gate.
The delayed pulse generating ring circuit 1 and pulse selector 3 correspond to a delayed pulse generating circuit and a synchronous pulse detecting circuit disclosed in "Magnetic Detection Device and Physical Quantity Detection Device Using Same " of U.S. Patent Application Ser. No. 5,134,371.
Unlike the disclosure of this U.S. Patent Application, the end point 5 of the delayed pulse generating ring circuit 1 of the present invention is connected to the start of the same circuit 1 to repeatedly use the signal delay circuits of the ring circuit 1. This is the reason why the present invention can expand a detection range without considerably increasing a circuit scale. By increasing the number of frequency divisions of the counter 2, it is possible to further expand the detection range. The expansion of the detection range may not deteriorate the detection accuracy of the circuit because the accuracy is determined only by the delay time of each signal delay circuit of the delayed pulse generating ring circuit.
The present invention expresses a phase difference between two pulses as a binary digital signal. A time resolution of the binary digital signal is determined by a delay time of each delay stage of the delayed pulse generating ring circuit 1. By shortening the delay time of each delay stage, a phase difference detection resolution may remarkably improve. For example, if each delay stage comprises an inverter which determines the delay time, the detection resolution of phase difference will be less than several nanoseconds.
A resolution in encoding a pulse phase difference is inversely proportional to the encoding range. For example, if the resolution improves two times, the encoding range decreases by half. According to the pulse phase difference encoding circuit of the present invention, however, an output of the counter 2 forms upper bits of an encoded phase difference, so that the encoding range may be expanded by increasing the number of bits of the counter output, without increasing to circuit scale.
The pulse phase difference encoding circuit of the present invention will be explained next in more detail.
According to the present invention, the pulse phase difference encoding circuit for producing a digital signal that indicates a time difference between a first pulse and a second pulse, comprises:
delayed pulse generating means having a plurality of delay elements connected in series to form a series circuit, one end of the series circuit receiving the first pulse, the means generating a plurality of delayed pulses while the first pulse is passing through the delay elements;
positional signal generating means for selecting the latest one of the delayed pulses upon receiving the second pulse that occurs after the first pulse, and generating a positional signal indicating a position of the selected delayed pulse among the other not-selected delayed pulses;
output means for receiving the positional signal and producing a digital signal indicating the time period between a time of input of the first pulse and a time of input of the second pulse;
means for connecting the one end of the series circuit to the other end thereof to repeatedly circulate the first pulse from the one end toward the other end through the delay elements of the series circuit;
counting means for counting the number of rounds of circulation of the first pulse in the series circuit; and
means for supplementing the digital signal provided by the output means with the number of rounds of circulation counted by the counting means, thereby having the digital signal represent the phase difference between the first and second pulses.
FIGS. 2A and 2B combined in FIG. 2 show a pulse phase difference encoding circuit according to the first embodiment of the present invention. The circuit receives a first pulse PA and then a second pulse PB, and encodes a difference between rise times of the two pulses into a binary digital signal. FIG. 3 is a timing chart of signals produced in the circuit. The circuit will be explained with reference to FIGS. 2A, 2B and 3.
In FIGS. 2A and 2B, a delayed pulse generating ring circuit 1 repeatedly generates delayed pulses P00 to P31 each having a delay time corresponding to the number of inverters 101 through which the first pulse PA has passed to generate the delayed pulse in question. A delay time of each delay stage (inverter) determines a phase difference detection resolution. By shortening the delay time of each delay stage, the detection resolution improves. In the embodiment, the delay time is equal to the delay time of each inverter 101.
In FIG. 3, the delayed pulses P00 to P31 are inverted relative to one another (for example, the delayed pulse P01 is inverted relative to the preceding delayed pulse P00), and delayed behind one preceding delayed pulse by the delay time produced by one inverter.
In this embodiment, the number of the inverters of the delayed pulse generating ring circuit 1 is odd, and an inverter 1011 and a NAND gate 102 are interposed between the delayed pulses P31 and P00 to produce a delay time corresponding to two inverters.
When a rise of the first pulse PA is supplied to the delayed pulse generating ring circuit 1, the delayed pulse P00 rises after a delay time of the NAND gate 102. Thereafter, the delayed pulse P01 falls after a delay time determined by the NAND 102 and one inverter 101. Then, the delayed pulses P02 to P31 sequentially and alternately rise and fall. After the delayed pulse P31, the second delayed pulses P00 to P31 occur.
Since there are an odd number of the inverters in one round of the ring delay pulse generating circuit 1, the second delayed pulses P00 to P31 are inverted relative to the first delayed pulses P00 to P31 and provided with an additional delay time corresponding to one round of the ring delay pulse generating circuit 1.
For example, in FIG. 3, the delayed pulse P00 rises at time t1 in the first round and falls at time t4 in the second round. In this way, the delayed pulses P00 to P31 alternately rise and fall in every round of the delayed pulse generating ring circuit 1.
In FIGS. 2A and 2B, a pulse selector 3 has D-type flip-flops (Dffs) 301 for receiving the delayed pulses P00 to P31 respectively from the delayed pulse generating ring circuit 1. The D-type flip-flops 301 use the second pulse PB as a clock pulse. When the second pulse PB rises, the D-type flip-flops 301 select one of the delayed pulses just triggered by the first pulse PA, as well as one of pulse selector outputs ER0 to ER31 corresponding to the selected delayed pulse.
For example, in FIG. 3, the second pulse PB rises at time t2, and one delayed pulse just caused by the first pulse PA is selected. As a result, outputs of the D-type flip-flops 301 corresponding to the delayed pulses P01 and P02 are simultaneously zeroed. The delayed pulses P01 and P02 are provided to inputs of corresponding EXORs (exclusive OR circuits) 302 to zero only the output ER02 of the pulse selector 3.
There are an even number of delayed pulses P00 to P31 in the embodiment of FIGS. 2A and 2B. This is why an inverter 105 is inserted. If this inverter 105 is not provided, there is a danger of zeroing the output ER00 of the pulse selector 3 not only when the first pulse PA produces the delayed pulse P31, but also on other occasions.
In FIGS. 2A and 2B, a known encoder 4 receives the 32 outputs ER00 to ER31 of the pulse selector 3. When one of the 32 outputs ER00 to ER31 becomes zero, the encoder 4 provides a binary digital signal comprising five digits EC1 to EC5 indicating the zeroed output of the pulse selector 3.
For example, in FIG. 3, the second pulse PB rises at time t3, and the D-type flip-flops 301 corresponding to the delayed pulses P17 and P18 are zeroed. As a result, among the outputs ER00 to ER31 of the pulse selector 3, only the output ER18 of the EXOR circuit that has received the delayed pulses P17 and P18 becomes zero. The output ER18 is an 18th pulse selector output with the output ER00 being a 0th output. Consequently, the encoder 4 provides a binary digital signal having five digits of 10010 indicating the 18th pulse.
In this way, the delayed pulse generating ring circuit 1, pulse selector 3, and encoder 4 provide a binary digital signal of five digits (00000 to 11111) that specify a position of the first pulse PA in the delayed pulse generating ring circuit at the time when the second pulse PB is input.
In FIG. 2B, counters 21 and 22 count the number of rounds of circulation of the first pulse PA in the delayed pulse generating ring circuit 1, and provide a binary digital signal indicating the counted value.
The first counter 21 has a clock input 211 that is connected to an output point 103 of the delayed pulse P15 in the delayed pulse generating ring circuit 1. The second counter 22 has a clock input 221 that is connected to an output point 104 of the delayed pulse P31. The first and second counters 21 and 22 count how many times the first pulse PA has passed through the output points 103 and 104.
At the output points 103 and 104, rises and falls of the first pulse PA alternately appear whenever the first pulse PA passes through the output points 103 and 104. The first and second counters 21 and 22 count the rises of the pulse. The first and second counters 21 and 22 have, therefore, pulse rise generating circuits 23 and 24, respectively, for converting a pulse fall signal into a pulse rise signal. With this arrangement, either a rise or a fall of the first pulse PA at the output points 103 and 104 can be counted by the first and second counters 21 and 22.
D-type flip-flops 25 and 26 receive outputs C11 to C14 of the first counter 21 and outputs C21 to C24 of the second counter 22 respectively, as well as the second pulse PB.
A multiplexer 27 provides outputs D11 to D14 of the first counter 21 side when a most significant bit (MSB) EC5 of the output of the encoder 4 is zero, and D21 to D24 of the second counter 22 side when the MSB EC5 is one. Namely, if the second pulse PB occurs when the first pulse PA triggers one of the delayed pulses P00 to P15 in the delayed pulse generating ring circuit 1, a corresponding one of the outputs ER00 to ER15 of the pulse selector 3 is zeroed. In this case, the output of the encoder 4 will be smaller than 15, i.e., smaller than 01111 as binary representation. This means that the MSB EC5 of the output of the encoder 4 is zero. As a result, an output of the counter 21 for counting the number of rounds of circulation of the first pulse PA passing through the output point 103 of the delayed pulse generating ring circuit 1 is provided as output bits CO1 to CO4 of the multiplexer 27.
On the other hand, if the second pulse PB occurs when the first pulse PA causes one of the delayed pulses P16 to P31, the MSB EC5 of the output of the encoder 4 becomes one, so that an output of the second counter 22 for counting the number of rounds of circulation of the first pulse PA passing through the output point 104 of the delayed pulse generating ring circuit 1 is provided as output bits CO1 to CO4 of the multiplexer 27.
In this way, the number of rounds of circulation of the first pulse PA is completely counted when the second pulse PB occurs, and an output of any one of the counters is correctly grasped.
For example, in FIG. 3, when the second pulse PB rises at time t3, the multiplexer 27 provides the output bits C21 to C24 of the second counter 22 that has not started counting a new round of circulation of the first pulse PA, instead of the output bits C11 to C14 of the counter 21 that has started counting a new round of circulation of the first pulse PA after the first pulse PA caused the delayed pulse P15. When the second pulse PB rises at time t5, the first pulse PA is in the next circulation in the delayed pulse generating ring circuit 1, so that the multiplexer 27 provides the output bits C11 to C14 of the first counter 21 that has already counted the number of rounds of circulation of the first pulse PA.
In FIG. 2A, a D-type flip-flop 11 receives the output bits EC1 to EC5 of the encoder 4 as first to fifth bits, and the output bits CO1 to CO4 of the multiplexer 27 as sixth to ninth bits. The D-type flip-flop 11 combines the two inputs and provides a binary digital signal having bits D0 to D8 as an output of the pulse phase difference encoding circuit in response to a clock signal DCK.
In this way, a phase difference between the first and second pulses PA and PB is detected based on the 32 delayed pulses produced in the delayed pulse generating ring circuit 1, and represented by an encoder output, i.e., a digital signal of five bits. Added to this encoder output are upper four bits provided by the counter that has counted the number of rounds of circulation of the first pulse PA in the delayed pulse generating ring circuit 1.
In FIG. 2B the clock input DCK is supplied to the D-type flip-flop 11 that is the last stage of the pulse phase difference encoding circuit. To stabilize data to be supplied to the D-type flip-flop 11, a sufficient time is interposed after the second pulse PB occurs until the clock input DCK is supplied to the D-type flip-flop 11.
In FIG. 2A, a reset pulse RGCR resets (zeroes) the first and second counters 21 and 22 (FIG. 2B) after outputs of the counters 21 and 22 are latched in response to the second pulse PB and before the next first pulse PA occurs.
In the above embodiment, the two output points 104 and 105 of the delayed pulse generating ring circuit 1 provide count pulses for counting the number of rounds of circulation of the first pulse PA. According to the present invention, it is possible to arrange, if required, more than two output points to provide count pulses. In this case, the number of counters must be increased accordingly.
In the embodiment of FIGS. 2A and 2B, the outputs of the delayed pulse generating ring circuit 1 and counters are continuously coupled together. To achieve this, the number of output lines of the delayed pulse generating ring circuit 1 must be 2.sup.n. On the other hand, to sequentially alter delayed pulses generated in the delayed pulse generating ring circuit 1 round by round, the number of inverters 101 forming one round of the delayed pulse generating ring circuit 1 must be odd. Due to this, a delay time between certain two adjacent delayed pulses must be produced by two inverters. This is the reason why the inverter 1011 and NAND circuit 102 are interposed between the delayed pulses P31 and P00 to produce the delay time of two stages.
If the operation speed of each inverter has a sufficient margin, the operation speed of each inverter may be set such that a delay time for the section of the two-inverter stage is equal to a delay time of a single inverter stage. This arrangement prevents detection accuracy from deteriorating. In this case, a detecting resolution to be realized without deteriorating the detection accuracy is determined by the delay time of the two inverters.
To solve this problem, the present invention provides another embodiment shown in FIG. 4. The resolution of a pulse phase difference encoding circuit of this embodiment is determined by the delay time of a single inverter.
The pulse phase difference encoding circuit of FIG. 4 provides a binary digital signal of nine bits indicating a phase difference between a first pulse PA and a second pulse PB. Similar to the first embodiment of FIG. 2, the circuit of FIG. 4 comprises a delayed pulse generating ring circuit 1, a pulse selector 3, an encoder 4, and a counter 2. An output of the encoder 4 provides a lower five bits of the binary digital signal of nine bits, while an output of the counter 2 provides an upper four bits of the binary digital signal.
In FIG. 4, a D-type flip-flop 256 reads an output of the counter 2, and a D-type flip-flop 11 reads output bits EC1 to EC5 from the encoder 4 as well as output bits C1 to C4 from the D-type flip-flop 256. The first pulse PA, second pulse PB, and clock input DCK are the same as those of the first embodiment of FIG. 2.
The embodiment of FIG. 4 differs from the first embodiment of FIG. 2 in that the number of output lines for delayed pulses P00 to P30 of the delayed pulse generating ring circuit 1 is only 31. The number of the delayed pulses P00 to P30 is odd, namely the number of inverters connected in a ring shape is odd. It is not necessary, therefore, to arrange two inverters for a delay time between certain two adjacent delayed pulses. Namely, detection resolution of this embodiment is determined by a delay time of a single inverter without deteriorating the phase difference detection accuracy. Since the number of the output lines of the delayed pulse generating ring circuit 1 is not 2.sup.n, some operation is needed to continuously couple the outputs of the delayed pulse generating ring circuit 1 and counter 2 together in providing a digital signal.
Referring again to FIG. 2A, the output bits EC1 to EC5 from the encoder 4 form the bits D0 to D4 of an output of the D-type flip-flop 11, and the output bits CO1 to CO4 from the multiplexer 27 form the bits D5 to D8 of the output of the D-type flip-flop 11. Supposing the output bits EC1 to EC5 express a decimal number n (integer of 0 to 31) and the output bits CO1 to CO4 represent a decimal number N (integer of 0 to 15), the output bits D0 to D8 from the D-type flip-flop 11 express a decimal number of n+32N.
On the other hand, the embodiment of FIG. 4 has the 31 output lines for delayed pulses P00 to P30 from the ring delay pulse generating circuit 1 to express a decimal number n, i.e., a integer positive of 0 to 30. This means that an output of the D-type flip-flop 11 must be n+31N with the N being an output from the counter 2 side. However, if the D-type flip-flop 11 reads the output bits EC1 to EC5 as a lower five bits and the output bits C1 to C4 as an upper four bits, the output bits D0 to D8 of the D-type flip-flop 11 of FIG. 4 represent a decimal number of n+32N. To solve this problem, a subtracter 12 is arranged to subtract N from the output bits D0 to D8 of the D-type flip-flop 11, thereby providing a correct output of n+31N.
With the above arrangement, resolution can be improved without deteriorating detection accuracy.
If the pulse selector 3 of FIG. 4 is the same as the pulse selector 3 of FIG. 2, the embodiment of FIG. 4 can omit the inverter 105 of FIG. 2 for preventing the output ER00 from being zeroed not only when the first pulse PA reaches the output line for delayed pulse P30 but also on other occasions, because the number of the output lines for delayed pulses P00 to P30 of the delayed pulse generating ring circuit 1 of FIG. 4 is odd.
With the above arrangement, a delay time of one delay stage of the delayed pulse generating ring circuit is equal to a delay time of a single inverter. In this case, resolution of phase difference detection can be improved by increasing the operational speed of each inverter. For example, instead of usual silicon CMOS inverters, inverters made of high-speed compound semiconductor transistors may be used to form a delayed pulse generating ring circuit to further improve the resolution of phase difference detection. Since operation speeds of circuits other than the delayed pulse generating ring circuit do not influence the detection resolution, wafer integration, selective epitaxial growing, etc., may be employed to form high-speed devices only for the delayed pulse generating ring circuit on a silicon IC chip, thereby reducing cost.
The above arrangements realize a pulse phase difference encoding circuit having an excellent resolution, and are applicable for the following apparatuses and systems.
A first application is a system for finding a distance to an object. The system emits a laser beam, detects a reflected wave from the object, and detects a phase difference between a pulse generated at the time the beam is emitted and a pulse generated at the time the reflected wave is detected, thereby finding the distance. This system can employ the above-mentioned pulse phase difference encoding circuit of the present invention to measure the distance at high resolution. For example, if a phase difference of pulses can be detected at a resolution of 1 ns, a distance can be measured at a resolution of 15 cm.
A measuring circuit employing the pulse phase difference encoding circuit of the present invention will be explained next.
FIG. 5 is a block diagram showing a resistance change detecting circuit employing the pulse phase difference encoding circuit. In the figure, numerals 201 and 202 are resistance elements whose resistances change. The resistance elements may be magnetic resistance elements (MREs) for forming a sensor circuit for detecting magnetism. The magnetic resistance elements may be strain gauge resistance wires of a sensor circuit for detecting pressure. Various resistance elements are employable to realize sensor circuits in which resistance values change in response to certain physical quantities.
The circuit of FIG. 5 detects a change in a difference between resistance values of the resistance elements 201 and 202. When the difference of the resistance values of the two resistance elements changes in response to a change in a certain physical quantity, the circuit can detect the change in the physical quantity. When the resistance values of the two resistance elements change opposite to each other, a maximum sensitivity is obtainable.
Numerals 203 and 204 are oscillators whose oscillation frequencies change in response to changes in the resistance values of the resistance elements 201 and 202 respectively. The oscillators 203 and 204 have waveform shaping circuits and provides pulse signals CKB and CKA shown in FIG. 6 whose frequencies are determined by the resistance values of the resistance elements 201 and 202.
Numerals 205 and 206 are known counters for counting the pulse signals CKB and CKA provided by the oscillators 203 and 204 and providing count signals C0B to C3B and C0A to C3A as shown in FIGS. 5 and 6.
Numerals 207 and 208 are decoders. When the counter 205 reaches a predetermined count value (nine in this embodiment), the decoder 207 provides reset signals RSTB and RSTA shown in FIG. 6 to the counters 205 and 206 respectively. At the same time, to synchronize the start of the next counting of the counters 205 and 206, the decoder 207 provides the oscillator 204 with a synchronizing signal SYNC. When the counter 205 reaches a count of nine, the decoder 207 provides a frequency dividing pulse signal PB as shown in FIG. 6.
Similar to the decoder 207, the decoder 208 provides a frequency dividing pulse signal PA when a count of the counter 206 reaches nine. Namely, when the counters 205 and 206 count the same number (nine in FIG. 6) of pulse signals CKB and CKA, the decoders 207 and 208 provide the frequency dividing pulse signals PB and PA, so that a difference between rise times of the frequency dividing pulse signals PB and PA may correspond to a time that represents cumulative phase differences between the respective pulse signals. This arrangement has an improved detection sensitivity with respect to a change in a certain physical quantity, and can detect a slight change in an oscillation frequency due to a change in the physical quantity. The pulses PA and PB of this example correspond to the first and second pulses PA and PB of the first embodiment.
Numeral 209 is a pulse phase difference encoding circuit according to any one of the embodiments of the present invention. The pulse phase difference encoding circuit 209 provides a binary signal having "i" bits D0 to Di-1 (i being a positive integer) indicating a phase difference between the pulse signals PA and PB. The pulse signal PB is delayed behind the pulse signal PA by a certain delay time.
Numeral 210 is a comparator circuit for comparing a difference between previous binary digital data provided by the pulse phase difference encoding circuit 209 and present binary digital data provided by the same, and providing a pulse signal Pout. The pulse signal Pout is inverted respectively between 1 to 0 at a maximal value and a minimal value of the difference.
FIG. 7 shows the details of the comparator circuit 210. The comparator circuit 210 has a storage circuit 41 for storing previous binary digital data D-10 to D-li-1 (present binary digital data being D0 to Di-1) provided by the pulse phase difference encoding circuit 209. The comparator circuit 210 further has a digital subtracter 42 for calculating a difference between the previous binary digital data D-10 to Dli-1 stored in the storage circuit 41 and the present binary digital data D0 to Di-1. The comparator circuit 210 further has a flip-flop 43 for receiving a bit signal indicating whether a result of the operation in the digital subtracter 42 is positive or negative, and providing the pulse signal Pout.
When the binary digital data D0 to Di-1 indicating the phase difference of the two frequency dividing pulse signals PA and PB change from increasing to decreasing or from decreasing to increasing, the pulse signal Pout changes from 1 to 0 or from 0 to 1.
In the above circuit for detecting a change in a difference in resistance values of a pair of resistance elements in response to a certain physical quantity, the resistance elements should have the same temperature coefficient to omit a special temperature compensating circuit. Since the circuits for handling frequencies that have been produced in response to changes in resistance values of the resistance elements are all digital circuits, the circuit of FIG. 5 is advantageous in operating under a high temperature.
The pulse phase difference encoding circuit encodes a phase difference between two pulses representing the difference between the resistance values of the two resistance elements into binary digital data signals, and the encoded signals are compared with each other for every sampling to detect a change in the phase difference between the pulses. Even when the resistance values of the pair of resistance elements fluctuate so that a center value of the changes in the phase difference of the two pulses fluctuates, the phase difference can correctly be detected. Accordingly, it is not necessary to precisely align the resistance values of the two resistance elements.
Although the detection circuit of FIG. 5 employs resistance elements, alternatively, it is possible to employ detection elements whose electrostatic capacitances change in response to a change in a certain physical quantity to easily convert changes in the electrostatic capacitance into changes in frequencies with use of known RC oscillators. In this way, the circuit of the present invention is applicable in various ways.
Claims
We claim:
1. An apparatus for producing an indication indicative of a time difference between first and second indicia, said apparatus comprising: a recirculating delay line, receiving said first indicia, formed of multiple delay elements connected together such that a delay element at a second end is connected to a delay element at a first end, and generating an output indicative of a position of said first indicia in said delay line, said output having a plurality of possible states each of which represents a different position of said first indicia in said delay line; a counter, connected to said recirculating delay line, counting a number of times that said first indicia recirculates between said delay element at said second end and said delay element at said first end; and a latch, receiving said second indicia, latching said delay line output and an output indicative of contents of said counter, when said second indicia occurs.
2. An apparatus as in claim 1, further comprising an encoder, coupled to receive outputs from each said elements of said recirculating delay line and encoding a position of said first indicia within said element outputs into a binary representation, said latch receiving an output of said encoder.
3. An apparatus for producing an indication of a time difference between first and second indicia, according to claim 1, wherein said recirculating delay line forms a delay signal generating means in which a plurality of delay elements, each having a predetermined delay time, are serially connected to each other, and an output of the last delay element of said delay signal generating means is connected to an input of the first delay element thereof, for, after said first indicia is input to the first delay element, transferring said first indicia through each one of said delay elements in turn, so as to circulate in said delay signal generating means, and sequentially outputting delay signals from outputs of respective delay elements when said first indicia passes through said respective delay elements.
4. An apparatus for producing an indication indicative of a time difference between first and second indicia, said apparatus comprising: a recirculating delay line, receiving said first indicia, formed of multiple delay elements connected together such that a delay element at a second end is connected to a delay element at a first end; a counter, connected to said recirculating delay line, counting a number of times that said first indicia recirculates between said delay element at said second end and said delay element at said first end; an encoder, coupled to receive outputs from each of said elements of said recirculating delay line and encoding a position of said first indicia within said outputs into a binary representation; and a latch, receiving said second indicia, latching said binary representation from said encoder and an output indicative of contents of said counter, when said second indicia occurs; wherein said encoder forms least significant bits of a digital word indicative of said time difference, and said counter forms most significant bits of said digital word indicative of said time difference.
5. An apparatus as in claim 4, wherein said counter comprises two separate counter structures, one of which counts a number of times that said first indicia recirculates between said delay element at said second end and said delay element at said first end, and the other of which counts a number of times that said first indicia recirculates between two other delay elements in said recirculating delay line.
6. An apparatus as in claim 5, further comprising a multiplexer, receiving outputs of said one and said other counter structures on two inputs thereof and producing one output indicative of a commanded input.
7. An apparatus as in claim 1, wherein said low resolution output producing means counts a number of times that said first pulse travels between said one portion of said delay line and said another portion thereof.
8. An apparatus as in claim 7, wherein said low resolution output producing means is a counter.
9. An apparatus for producing an indication of a time difference between two pulses, said apparatus comprising: delay means, adapted to receive a first pulse, for delaying said first pulse in increments between its input and its output, said output of said delay means being connected to said input of said delay means to recirculate the first pulse, and for generating an increment output indicative of an increment status of said delay means, said increment output having a plurality of possible states each of which represents a different increment of said delay line; counting means for counting a number of times said delay means recirculates said first pulse; and receiving means, adapted to receive a second pulse, for producing an output indicative of both a count of said counting means and said delay means increment output, at a time of receiving said second pulse, wherein said counting means includes first and second counters counting a number of times said delay means recirculates said first pulse through first and second parts of said delay means, respectively, said first and second parts being different from one another.
10. An apparatus as in claim 9, wherein said counting means includes an counter.
11. An apparatus as in claim 9, wherein said receiving means includes a latch which is clocked by said second pulse to store an increment output of the delay means and a count of the counting means.
12. An apparatus as in claim 9, wherein said delay means comprises multiple delay elements, each of said multiple delay elements including an inverter.
13. An apparatus as in claim 9, further comprising an encoder, coupled to said receiving means.
14. An apparatus for determining a time difference between first and second pulses, said apparatus comprising: a delay line, receiving the first pulse as an input thereof, and delaying said first pulse by increments from a beginning of the delay line toward one end of the delay line, including a recirculating portion connecting one portion of the delay line to another portion of the delay line, and generating an output indicative of an increment of said delay line, said output having a plurality of possible states each of which represents a different increment of said delay line; and means, coupled to said recirculating portion, for producing a low resolution output, having a lower resolution than a resolution between said increments, at a time when said second pulse is received; and a latch, latching the delay line output and the low resolution output upon receipt of the second pulse.
15. A method of determining a time difference between first and second pulses, comprising the steps of: incrementally delaying the first pulse a number of times as it passes downstream toward a first delayed portion; connecting the first delayed portion to a second delayed portion, upstream of the first delayed portion; counting a number of times that said first pulse recirculates between the first delayed portion and second delayed portion using a digital count; detecting when said second pulse occurs and using, at that time, a count of the number of times as a low resolution measure of said time difference; determining a position in the first through second delayed portions as a high resolution measure of said time difference; latching said low resolution measure; combining said latched low resolution measure and said high resolution measure to provide an overall time difference; and adjusting a number of bits of output by changing a number of bits used in the counting step to change a dynamic range of the method.
16. The method of claim 15, said adjusting step comprising a step of increasing a number of bits in the counting step to increase the dynamic range of the system.
17. A method of determining a time difference between first and second pulses, said method comprising the steps of: incrementally delaying the first pulse a number of times as it passes downstream toward a first delayed portion; connecting the first delayed portion to a second delayed portion, upstream of the first delayed portion; counting a number of times that said first pulse recirculates between the first delayed portion and the second delayed portion using a digital count; detecting when said second pulse occurs and using, at that time, a count of the number of times as a low resolution measure of said time difference; determining a position in the first through second delayed portions as a digital high resolution measure of said time difference; latching said low resolution measure; combining said latched low resolution measure and said high resolution measure to provide an overall time difference; and adjusting a number of bits of output by changing a number of bits in the counting step to change a dynamic range of the system.
18. The method of claim 17, said adjusting step comprising a step of increasing a number of bits in the counting step to increase the dynamic range of the system.
19. A system for measuring a timing of an input signal applied thereto, said system comprising: a recirculating delay line, including a plurality of delay elements, propagating a delay pulse sequentially through said plurality of delay elements and generating a plurality of delay outputs each representative of a different position of said delay pulse in said recirculation delay line; a plurality of latch elements each having a first input connected to a respective one of said delay outputs of said recirculating delay line and a second input receiving said input signal, each of said plurality of latch elements latching one of its first and second inputs responsive to the other of said first and second inputs, and generating a latch output responsive thereto; a plurality of counters, each having an input connected to an output of a preselected one of said delay elements in said recirculating delay line, each of said counters providing an additional timing measurement of said input signal; wherein latch outputs of said plurality of latch elements collectively represent a timing measurement of said input signal.
20. The system of claim 19, further comprising selection means for, responsive to at least one of said plurality of latch outputs, selecting an output of one of said plurality of counters as a coarse timing measurement.
21. A system for measuring a timing of an input signal applied thereto, said system comprising: a delayed pulse generating circuit sequentially generating a plurality of fine timing signals during a fine timing cycle on corresponding ones of a plurality of delayed pulse generating circuit outputs based on a position of a delay pulse within a delay line, said delay line including a plurality of delay elements; a signal processing section connected to said delayed pulse generating circuit generating, responsive to said input signal, a fine timing output representative of said plurality of fine timing signals; first counter means, connected to said delayed pulse generating circuit, receiving therefrom a first signal corresponding to one of said plurality of fine timing signals as a first clock signal, for generating a first count responsive to said input signal based on said first clock signal; second counter means, connected to said delayed pulse generating circuit, for generating a second count responsive to said input signal based on a second signal corresponding to one of said plurality of fine timing signals as a second clock signal; a multiplexer receiving said first count and said second count and selectively providing one of said first and second counts as a multiplexer output; wherein said multiplexer output is a coarse timing measurement of said input signal and said fine timing output is a fine timing measurement of said input signal.
22. The system of claim 21, wherein said delay line includes a feedback signal generator generating a feedback signal based on an output of said delay line and providing said feedback signal to an input of said delay line.
23. The system of claim 21, further comprising a plurality of delayed pulse output elements having inputs connected to corresponding outputs of said delay line and generating said plurality of fine timing signals at corresponding outputs thereof, said plurality of delayed pulse output elements being of a same type as said plurality of delay elements.
24. The system of claim 23, wherein said plurality of delay elements and said plurality of delayed pulse output elements are inverters.
25. The system of claim 21, wherein each of said delay elements in said delay line includes an inverter.
26. The system of claim 21, wherein said delay pulse generation circuit has a periodic signal applied to an input thereof.
27. The system of claim 26, wherein said periodic signal is said output of an end delay element in said delay line.
28. The system of claim 21, wherein each of said plurality of fine timing signals is indicative of a different position of said delay pulse in said delay line.
29. The system of claim 21, said signal processing section comprising: a pulse selector receiving said input signal, latching signals on said plurality of delayed pulse generating circuit outputs responsive to said input signal, and generating a pulse selection output representative of said latched signals; and an encoder receiving said pulse selection output and generating a binary-coded representation thereof as said fine timing output.
30. The system of claim 29, said pulse selector comprising: a pulse selection latch latching signals on said plurality of delayed pulse generating circuit outputs responsive to said input signal as a pulse selection latch output; and a priority encoder receiving said pulse selection latch output and generating said pulse selection output based thereon.
31. The system of claim 30, wherein said pulse selection latch output comprises a first portion of contiguous bits each having a first binary value and a second portion of contiguous bits having a second binary value different from said first binary value.
32. The system of claim 30, wherein said pulse selection output comprises a plurality of outputs having a first value and a single output having a second value different from said first value, said single output being indicative of said position of said delay pulse in said delay line.
33. The system of claim 21, wherein: said first counter means includes a first latch, connected to a first counter generating said first count, receiving said input signal, latching said first count responsive thereto and generating a first latch output representative of said latched first count; said first counter means generates said first count based on said first latch output; said second counter means includes a second latch, connected to a second counter generating said second count, receiving said input signal, latching said second count responsive thereto, and generating a second latch output representative of said latched second count; and said second counter means generates said second count based on said second latch output.
34. The system of claim 21, wherein said second clock signal lags said first clock signal by half a fine timing cycle.
35. The system of claim 34, wherein at least one inverter delays said first clock signal to provide said second clock signal.
36. The system of claim 21, wherein said multiplexer selectively provides said first count during a first portion of said fine timing cycle, and selectively provides said second count during a second portion of said fine timing cycle.
37. The system of claim 21, wherein said multiplexer selectively provides said first count as said multiplexer output when a most significant bit of said fine timing output has a first value and selectively provides said second count as said multiplexer output when the most significant bit has a second value different from said first value.
38. The system of claim 21, further comprising a latch latching said multiplexer output and said fine timing output to provide a timing measurement of said input signal.
39. A method of measuring a timing of an input signal, said method comprising the steps of: sequentially generating a plurality of fine timing signals during a fine timing cycle based on a position of a delay pulse within a delay line, said delay line including a plurality of delay elements; generating, responsive to said input signal, a fine timing output representative of said plurality of fine timing signals; generating a first count responsive to a first clock signal corresponding to one of said plurality of fine timing signals; generating a second count responsive to a second clock signal corresponding to one of said plurality of fine timing signals; and selectively providing one of said first count and said second count as a coarse count output; wherein said coarse count output is a coarse timing measurement of said input signal and said fine timing output is a fine timing measurement of said input signal.
40. The method of claim 39, wherein said sequential generating step includes a step of generating a feedback signal based on an output of said delay line and providing said feedback signal to an input of said delay line.
41. The method of claim 39, said fine timing signal generating step including a step of generating each of said fine timing signals to represent a different position of said delay pulse within said delay line.
42. The method of claim 39, further comprising the steps of: generating said second clock signal to lag said first clock signal by half a fine timing signal cycle.
43. The method of claim 39, said selective providing step comprising the step of: providing said first count as said count output when a most significant portion of bits of said fine timing output has a first set of values; and providing said second count as said count output when the most significant portion of bits has a second set of values different from said first set of values.
44. The method of claim 43, wherein said most significant portion of bits of said fine timing output is a most significant bit of said fine timing output; and said first set of values is a binary value.
45. A method of measuring a timing of an input signal, said method comprising the steps of: sequentially generating, in a delay line including a plurality of delay elements, a plurality of fine timing signals at outputs of said delay elements during a fine timing cycle based on a position of a delay pulse within the delay line; generating first timing information, responsive to said input signal, based on at least one delay element output in a first portion of said delay element outputs; generating second timing information, responsive to said input signal, based on at least one delay element output in a second portion of said delay element outputs; presenting said first timing information and said second timing information to an output latch; and latching said first timing information and said second timing information with said output latch to provide a timing measurement of said input signal.
46. The method of claim 45, wherein said sequential generating step includes a step of generating a feedback signal based on an output of said delay line and providing said feedback signal to an input of said delay line.
47. The method of claim 45, said fine timing signal generating step including a step of generating each of said fine timing signals to represent a different position of said delay pulse within said delay line.
48. The method of claim 45, said fine timing signal generating step comprising the steps of: latching said plurality of fine timing signals responsive to said input signal as a pulse selection latch output; and generating a pulse selection output representative of said pulse selection latch output.
49. The method of claim 48, wherein said pulse selection latch output comprises a first portion of contiguous bits each having a first binary value and a second portion of contiguous bits each having a second binary value different from said first binary value.
50. The method of claim 48, wherein said pulse selection output comprises a plurality of outputs having a first value and a single output having a second value different from said first value, said single output being indicative of said position of said delay pulse in said delay line.
51. The method of claim 45, wherein said first and second timing information latching step comprises the steps of: latching said first timing information at a first time; and latching said second timing information at a second time different from said first time.
52. The method of claim 45, wherein said first and second timing information latching step includes a step of selectively presenting said first and second timing information at an output of said output latch at different times.
53. A method of measuring a timing of an input signal, said method comprising the steps of: sequentially generating, in a delay line including a plurality of delay elements, a plurality of fine timing signals at outputs of said delay elements during a fine timing cycle based on a position of a delay pulse within the delay line, each of said fine timing signals representing a different position of said delay pulse within said delay line; generating, responsive to said input signal, fine timing information indicative of a position of said delay pulse in a portion of said delay line, said fine timing information corresponding to a least significant portion of a timing measurement of said input signal; generating, responsive to said input signal, coarse timing information corresponding to a most significant portion of said timing measurement based on at least one of said plurality of delay element outputs; and latching said coarse timing information.
54. The method of claim 53, said fine timing information generating step comprising the steps of: latching said plurality of fine timing signals responsive to said input signal as a pulse selection latch output; and generating a pulse selection output representative of said pulse selection latch output.
55. The method of claim 54, wherein said pulse selection latch output comprises a first portion of contiguous bits each having a first binary value and a second portion of contiguous bits each having a second binary value different from said first binary value.
56. The method of claim 54, wherein said pulse selection output comprises a plurality of outputs having a first value and a single output having a second value different from said first value, said single output being indicative of said position of said delay pulse in said delay line.
57. The method of claim 53, further comprising the steps of: latching said fine timing information.
58. An apparatus for producing an indication of a time difference between two pulses, said apparatus comprising: delay means, adapted to receive a first pulse, for delaying said first pulse in increments between its input and its output, said output of said delay means being connected to said input of said delay means to recirculate the first pulse, and for generating an increment output indicative of an increment status of said delay means, said increment output having a plurality of possible states each of which represents a different increment of said delay line; counting means for counting a number of times said delay means recirculates said first pulse; and receiving means, adapted to receive a second pulse, for producing an output indicative of both a count of said counting means and said delay means increment output, at a time of receiving said second pulse, wherein said receiving means includes a latch which is clocked by said second pulse to store an increment output of the delay means and a count of the counting means.
59. The apparatus of claim 58, wherein said counting means includes two counters.
60. The apparatus of claim 58, wherein each of said multiple delay elements includes an inverter.
61. The apparatus of claim 58, further comprising an encoder coupled to said receiving means.
62. A method of measuring a timing of an input signal, said method comprising the steps of: sequentially generating, in a delay line including a plurality of delay elements, a plurality of fine timing signals at outputs of said delay elements during a fine timing cycle based on a position of a delay pulse within the delay line, each of said fine timing signals representing a different position of said delay pulse within said delay line; generating, responsive to said input signal, a pulse selection output comprising a plurality of outputs having a first value and a single output having a second value different from said first value, said single output being indicative of said position of said delay pulse in said delay line; generating, based on said pulse selection output, fine timing information corresponding to a least significant portion of a timing measurement of said input signal; and generating, responsive to said input signal, coarse timing information corresponding to a most significant portion of said timing measurement based on at least one of said plurality of delay element outputs.
63. The method of claim 62, wherein the pulse selection output generating step comprises the step of latching said plurality of fine timing signals responsive to said input signal as a pulse selection latch output.
64. The method of claim 63, wherein said pulse selection latch output comprises a first portion of contiguous bits each having a first binary value and a second portion of contiguous bits each having a second binary value different from said first binary value.
65. The method of claim 62, further comprising the step of: latching said fine timing information and said coarse timing information with an output latch.
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