Method of Aligning Layers in an Integrated Circuit Device

The present invention relates in general to semiconductor device fabrication processes and more particularly to a method of aligning layers in an integrated circuit device.

In semiconductor device fabrication processes, different layers are formed on each other to create the desired integrated circuit device. In order that connections can be made for proper device operation, each layer should be properly aligned with another corresponding layer. In conventional alignment procedures, vernier marks were associated with each layer so that a fabrication operator could manually align each layer based on the position of corresponding vernier marks. However, imprecise human eye alignment techniques resulted in a great deal of alignment errors during device fabrication.

Scanning techniques were developed to increase the accuracy of layer alignment by measuring certain points associated with layers selected for alignment and comparing displacement of those points to ensure that the points fell within a certain tolerance. These scanning processes have historically used a single scan at each of several sites to determine and verify the alignment points of the wafer. These scanning processes also have difficulty finding the alignment points when there was signal distortion in the scanning zone due to extraneous material buildup during layer formation. Increasing the confidence level of the alignment method required making redundant, time consuming scans of the alignment points at each site, or of making single scans at ever increasing numbers of sites. Both approaches are unacceptable time consuming techniques for today's competitive market place. Therefore, it is desirable to have an aligning method with increased accuracy, less scanning time, and that overcomes material build up in the scanning zone as a result of layer formation.

From the foregoing, it may be appreciated that there continues to be a need for alignment methods that perform a single scan for alignment determination. A need has arisen for an alignment target that can be accurately scanned despite build up of extraneous material in the scanning zone during layer formation. Therefore, a need has arisen for an alignment target with multiple edges to increase alignment accuracy.

In accordance with the present invention, a method of aligning layers in an integrated circuit device is provided which substantially eliminates or reduces disadvantages and problems associated with conventional alignment procedures.

According to an embodiment of the present invention, there is provided a method of aligning layers in an integrated circuit device that includes associating each layer with an alignment target that has at least four edges on a single axis. Each layer and associative alignment target are successively formed onto a semiconductor material. After each layer is formed, the edges of the alignment targets of corresponding aligned layers are measured to determine whether proper layer alignment occurs.

The method of the present invention provides various technical advantages over conventional alignment procedures. For example, one technical advantage is in providing multiple edges in an alignment target to increase alignment accuracy. Another technical advantage is in having multiple edges in an alignment target to overcome scanning signal shifts due to build up of extraneous materials that may occur along one of the edges in the scanning zone during layer formation. Yet another technical advantage is in reducing the number of scanning runs required to determine proper alignment. Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

FIG. 1 illustrates a schematic diagram of one half of an alignment target;

FIG. 2 illustrates a schematic diagram of the other half alignment target for a correspondingly aligned layer;

FIG. 3 illustrates a simplified diagram of alignment targets on reticles associated with a series of layers;

FIG. 4 illustrates a simplified schematic diagram of a side view of an alignment structure formed during fabrication of an integrated circuit device; and

FIG. 5 illustrates a schematic diagram of both halves of an alignment structure seen by a scanning device to determine proper layer alignment.

FIG. 1 is a schematic diagram of an alignment target 10. Alignment target 10 includes a first set of vernier marks 12 along a vertical plane and a second set of vernier marks 14 along a horizontal plane. Alignment target 10 also includes a first boxed frame 16 and a second boxed frame 18. First boxed frame 16 has outer edges 20 and 22 and inner edges 24 and 26. Second boxed frame 18 has outer edges 30 and 32 and inner edges 34 and 36. Though alignment target 10 is shown to have two boxed frames, a single boxed frame, or multiple boxed frames as space permits, may be used in order to select the desired number of edges for scanning. Also, since any structure that gives a series of edges suitable for scanning may be used, the edges of the alignment target do not have to meet and form a continuous, boxed frame.

FIG. 2 is a schematic diagram of an alignment target 50 for a correspondingly aligned layer. Alignment target 50 includes a first set of vernier marks 52 along a vertical plane and a second set of vernier marks 54 along a horizontal plane. Alignment target 50 also includes a third boxed frame 56 and a fourth boxed frame 58. Third boxed frame 56 has outer edges 60 and 62 and inner edges 64 and 66. Fourth boxed frame 58 has outer edges 68 and 70 and inner edges 72 and 74. As with alignment target 10, alignment target 50 may employ a single boxed frame, multiple boxed frames, or any other multiple-edged structure according to space limitations, to select a desired number of edges for scanning. Boxed frames 56 and 58 of alignment target 50 have greater dimensions than boxed frames 16 and 18 of alignment target 10.

FIG. 3 is a simplified diagram of alignment marks on a series of reticles corresponding to a series of layers. Reticle 80 has alignment targets corresponding to layer 1, reticle 82 has alignment targets corresponding to layer 2, reticle 84 has alignment targets corresponding to layer 3, reticle 86 has alignment targets corresponding to layer 4, and reticle 88 has alignment targets corresponding to layer 5. Each reticle has alignment targets that are used to align one layer to one of the other layers as predetermined for the design of the integrated circuit device. For example, reticle 80 for layer. 1 has an alignment target 90 that corresponds to an alignment target 92 of reticle 82 for layer 2 to be used when aligning layer 1 with layer 2. Reticle 80 for layer 1 also has an alignment target 94 that corresponds to an alignment target 96 of reticle 84 for layer 3 to be used when aligning layer 1 with layer 3. Reticle 80 for layer 1 also has an alignment target 98 corresponding to an alignment target 100 of reticle 86 for layer 4 to be used when aligning layer 1 with layer 4. Reticle 82 for layer 2 also has an alignment target 102 corresponding to an alignment target 104 of reticle 86 for layer 4 to be used when aligning layer 2 with layer 4. Reticle 84 for layer 3 also has an alignment target 106 that corresponds to an alignment target 108 of reticle 88 for layer 5 to be used when aligning layer 3 with layer 5. Additional alignment targets may be included to align additional layers.

The reticles are used for the formation of each layer during the semiconductor fabrication process. Each reticle is successively applied during the fabrication process to successively form each layer on appropriate portions of a semiconductor wafer. An alignment structure containing the alignment targets is also formed on the semiconductor wafer during the fabrication process. After each layer and corresponding alignment structure is formed on a semiconductor wafer, a scanning process is performed on the alignment targets of correspondingly aligned layers at the alignment structure formed on the semiconductor wafer to determine if proper alignment exists.

FIG. 4 is a simplified cross-sectional diagram of an alignment structure 20 formed on the semiconductor wafer. The alignment structure formed during fabrication of each layer includes the alignment targets according to the reticle associated with each layer. Layer 1 was formed with alignment targets 90, 94, and 98. Layer 2 was formed with alignment targets 92 and 102. Layer 3 was formed with alignment targets 96 and 106. Layer 4 was formed with alignment targets 100 and 104. Layer 5 was formed with alignment target 106. Since materials used in the formation of each layer is transparent or opaque, positive or negative tones of the alignment structure are used on the reticle to allow visual inspection of the alignment targets through the alignment structure.

As previously discussed, conventional alignment techniques were performed on vernier marks associated with each layer such that an operator could visually inspect the vernier marks to determine if the layers have been properly aligned. With the use of alignment targets having multiple edge configurations, more accurate scanning equipment can be used to determine if layers are properly aligned. Vernier marks 12, 14, 52, and 54 remain in the alignment target to allow for optional manual alignment. Though each alignment target is shown as being formed on each corresponding layer, the alignment targets may be etched into the layers such that grooves are created in each layer instead of raised edges that correspond to the boxed frame configuration of the alignment targets.

FIG. 5 is a schematic diagram of one portion of alignment structure 200 having alignment targets for two correspondingly aligned layers. The alignment targets formed within alignment structure 200 for correspondingly aligned layers are scanned to determine if the layers are properly aligned. The scanning process performs a scan on all the frames for the inner and outer boxes at one time. From the scan of inner boxed frames 16 and 18 along an x-axis plane, edges 20, 22, 24, 26, 30, 32, 34, and 36 are found. Processing circuitry takes the information from the scanning process and calculates a center point for the alignment target represented by boxed frames 16 and 18. During the previously discussed scan of the inner boxed frames, the scanning process also performs a scan along the x-axis plane on outer boxed frames 56 and 58 in order to find edges 60, 62, 64, 66, 68, 70, 72, and 74. The processing circuitry calculates a center position for the alignment target of boxed frames 56 and 58 according to the information received from the scanning process. If the center positions of the two alignment targets coincide, then the layers are properly aligned along the x-axis plane. The scanning process is then performed on the alignment targets along the y-axis plane to determine if the calculated center points of each alignment target coincide. If the alignment targets coincide on both the x-axis plane and the y-axis plane, then the layers are properly aligned.

By having multiple edges for which to scan, a single scan can be performed along each axis for each alignment target, reducing the amount of time necessary to obtain equivalent data by performing multiple scans on one or two edges. Further, any error in scanning an edge based on inaccurate readings due to build up of material along any edge during layer formation is overcome by having redundant edges upon which to base the center point calculation. If an edge produces a measurement disproportionate to other edge measurements, then the analysis algorithm can discard that edge for the center point calculation.

In summary, a method of aligning layers of an integrated circuit device include using alignment targets that have multiple edges such as a boxed frame configuration in order to accurately determine proper layer alignment. An alignment structure containing alignment targets for each layer is formed on the semiconductor wafer during device fabrication. A scanning process is performed on the alignment structure to determine if the center points of the alignment targets for correspondingly aligned layers coincide according to the position of the multiple edges of each alignment target. If the center points coincide, then the layers have been properly aligned.

Thus, it is apparent that there has been provided, in accordance with the present invention, a method of aligning layers in an integrated circuit device that satisfies the advantages set forth above. Although the preferred embodiment has been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention as defined by the following claims.