Bright Field Wafer Target

This invention relates generally to processing integrated circuits and more particularly to auto alignment marks used to align layer placement during processing of wafers.

When processing wafers, targets are placed to assure each layer is properly aligned with respect to prior layers. Within the targets, alignment marks are placed. Layers placed subsequent to the alignment marks, utilize the alignment marks for proper placement. The subsequent layer can then be aligned to the mark within an alignment error. The alignment error results from the error tolerances of the processing devices. See for example, Canon Reticle Alignment for Canon I-2000/I-2500 Stepper Model, available from Canon U.S.A. having a business address of 2051 Mission College Blvd., Santa Clara, Calif. 95054.

For example, in a first layer, master marks may be placed in each target. Subsequent layers are all aligned to these first layer master marks. This assures that every layer subsequent to the first layer will be aligned to the first layer within the alignment error. However, one problem with such a master mark alignment system is that the total alignment errors between layers other than the first layer is the square root of two times the alignment error. Thus immediately adjacent layers may be misaligned an amount up to the square root of two times the alignment error. In some processes this amount of error between adjacent layers may be excessive.

Alternately, each layer may include alignment marks for each target. Each layer is aligned using alignment marks composed of material from the immediately prior layer. This guarantees that immediately adjacent layers are misaligned at most an amount equal to the alignment error. However, use of such a sequential mark alignment system may result in a "walking error" wherein misalignment between layers which are not immediately adjacent to one another can be significantly larger than the alignment error.

In accordance with the preferred embodiment of the present invention, a target used in alignment of layers on a wafer is presented. Within a target area, alignment marks are placed. The alignment marks are composed of material from a first layer placed on the wafer. Also within the target area, as subsequent layers are placed on the wafer, alignment marks composed of material from the subsequent layers are placed within the target area. For example, alignment marks composed of material from a second layer are each placed adjacent to one of the alignment marks composed of material from the first layer. Alignment marks composed of material from a third layer are each placed adjacent to one of the alignment marks composed of material from the second layer. Alignment marks composed of material from a fourth layer are each placed adjacent to one of the alignment marks composed of material from the third layer. And so on. In the preferred embodiment of the present invention, the alignment marks are each rectangular in shape.

The resulting composite target utilizes visible alignment marks for a multitude of layers. This combines the advantages inherent in a master mark alignment scheme and a sequential mark alignment scheme. The present invention is advantageous over the sequential mark alignment scheme as the present invention does not require a new target for every layer, thus saving space in the scribe lines.

FIG. 1 shows two targets on the scribe lines of the device area on a wafer in accordance with the prior art.

FIG. 2 shows alignment marks from a first layer placed on a target in accordance with the preferred embodiment of the present invention.

FIG. 3 shows alignment marks from a second layer added to the target shown in FIG. 1 in accordance with the preferred embodiment of the present invention.

FIG. 4 shows alignment marks from a third layer added to the target shown in FIG. 1 in accordance with the preferred embodiment of the present invention.

FIG. 5 shows alignment marks from a fourth layer added to the target shown in FIG. 1 in accordance with the preferred embodiment of the present invention.

FIG. 6 shows alignment marks from a fifth layer added to the target shown in FIG. 1 in accordance with the preferred embodiment of the present invention.

FIG. 1 shows a target 9 and a target 10 on the scribe line of device area 8 of a wafer being processed in accordance with the prior art. Each of target 9 and target 10 are, for example, 120 micrometers by 50 micrometers.

In the preferred embodiment, a composite wafer target is partially built at each layer where an etch is performed. For example the layers may be composed of oxide, polysilicon, metal or some other material used in processing wafers. FIGS. 2 through 6 show processing stages of the composite wafer target in accordance with the preferred embodiment of the present invention. The particular composite wafer target shown being processed is for a process in which five layers are etched.

FIG. 2 shows target area 10 after a first layer is etched. After etching the first layer, alignment marks 11 are exposed within target area 10. Outside lines 22 from the first layer are also exposed. Each of alignment marks 11, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, Alignment marks 11 are separated from each other by a distance of, for example, 20 micrometers. While only 20 of alignment marks 11 are shown, a typical target may have, for example, more (or less) than twenty alignment marks for each layer.

FIG. 3 shows target area 10 after a second layer is etched. After etching the second layer, alignment marks 12 are exposed within target area 10. Outside lines 23 from the second layer are also exposed. Outside lines 23 are placed directly over outside lines 22. Each of alignment marks 12, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 12 is immediately adjacent to one of alignment marks 11.

FIG. 4 shows target area 10 after a third layer is etched. After etching the third layer, alignment marks 13 are exposed within target area 10. Outside lines 24 from the second layer are also exposed. Outside lines 24 are placed directly over outside lines 23. Each of alignment marks 13, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 13 is immediately adjacent to one of alignment marks 12.

FIG. 5 shows target area 10 after a fourth layer is etched. After etching the fourth layer, alignment marks 14 are exposed within target area 10. Outside lines 25 from the second layer are also exposed. Outside lines 25 are placed directly over outside lines 24. Each of alignment marks 14, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 14 is immediately adjacent to one of alignment marks 13.

FIG. 6 shows target area 10 after a fifth layer is etched. After etching the fifth layer, alignment marks 15 are exposed within target area 10. Outside lines 26 from the second layer are also exposed. Outside lines 26 are placed directly over outside lines 25. Each of alignment marks 15, for example, has a width of 1.2 micrometers and a height of 4 micrometers. In the shown example, each of alignment marks 5 is immediately adjacent to one of alignment marks 14.

Embodiments of targets in accordance with the present invention may vary significantly. For example, the exact size of each alignment mark is not significant. Therefore, the height and/or width of alignment marks can vary from layer to layer. Likewise, the distance between the alignment can be varied to account for the addition alignment marks from more than (or less than) five layers.

The outside lines on the left and the right of the alignment marks are used to minimize resist pile up over the target. These all overlap at each masking layer. Even if the lines are broken, this will not impact the alignment of the layers.

The present invention presents a composite target in which alignment marks for each layer are visible for use in the alignment of subsequent layers. This system combines the advantages inherent in a master mark alignment scheme and a sequential mark alignment scheme.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.