US 5,444,648 AGrant
Analog Multiplier Using Quadritail Circuits
Issue Date:1995-08-22
•18 Claims
•16 Drawing Sheets
Abstract
A multiplier having first and second quadritail circuits, each of which has two pairs of transistors whose capacities are the same, respectively, and is driven by a constant current source. In the first quadritail circuit, input ends of a first pair are respectively applied with voltages .+-.(V.sub.1 +V.sub.2), and input ends of a second pair are connected in common to be biased by a middle point voltage of the voltage applied between the input ends of the first pair. In the second quadritail circuit, input ends of a third pair are respectively applied with voltages .+-.(V.sub.1 -V.sub.2), and input ends of a fourth pair are connected in common to be biased by a middle point voltage of the voltage applied between the input ends of the third pair. Common-connected output ends of the first and fourth pairs are respectively connected in common to form one of differential output ends, and common-connected output ends of the second and third pairs are connected in common to form the other of the differential output ends. Simplification of circuit configuration and reduction of current consumption are accomplished.
Metadata
Assignee
- NEC Corporation
Inventor
- Katsuji Kimura
Application Information
Application Number:US 1204629
Filing Date:1993-09-14
Priority Date:1992-10-30
Art Unit:236
Classifications
IPC:
G06G 716
Field of Search:
364307328841529;498144;160
Patent Drawings (16 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates a multiplier and more particularly, to a multiplier for analog signals using quadritail cells or circuits formed of bipolar transistors or metal-oxide-semiconductor (MOS) transistors, which is formed on semiconductor integrated circuits.
2. Description of the Prior Art
It is well known that an analog multiplier is composed of an adder 1, a first subtracter 2, a first squarer 3, a second squarer 4 and a second subtracter 5, as shown in FIG. 1. In FIG. 1, a first analog input signal (voltage V.sub.1) and a second analog input signal (voltage V.sub.2) are respectively applied in parallel to the adder 1 and the first subtracter 2. The adder 1 outputs a voltage (V.sub.1 +V.sub.2) which is the sum of the first and second input voltages V.sub.1 and V.sub.2, the first subtracter 2 outputs a voltage (V.sub.1 -V.sub.2) which is the difference thereof. The output of the adder 1 is squared in the first squarer 3 and the output of the subtracter 2 is squared in the second square 4, and then the outputs of the first and second squarer 3 and 4 are sent to the second subtracter 5. In the second subtracter 5, since an operation such as (V.sub.1 +V.sub.2).sup.2 -(V.sub.1 -V.sub.2).sup.2 is carried out, an output voltage V.sub.0 of 4V.sub.1 V.sub.2 can be obtained. This means that the circuit shown in FIG. 1 has a function of multiplying the first and second input signals.
The inventor has developed a squarer composed of two differential pair each of which has two MOS transistors different in capacity from each other. Here, the "capacity" of the MOS transistor means that a ratio of the gate width W to the gate length L, or (W/L). Besides, the inventor has filed a Japanese patent application about a multiplier as shown in FIG. 2, in which the inventor's squarer is used as the first and second squarers 2 and 3 respectively and the adder 1 and the first subtracter 2 are respectively composed of differential pairs of MOS transistors (see Japanese Non-Examined Patent Publication 3-210683 and its correslonding U.S. Pat. No. 5,107,150).
The prior art multiplier shown in FIG. 2 is composed of MOS transistors. An adder 6 is comprised of four MOS transistors M51, M52, M53 and M54 whose capacities are the same, and two constant current sources (current I.sub.0) which drive the pair of the transistors M51 and M52 and that of the transistors M53 and M54, respectively. The first input voltage V.sub.1 is applied between the input ends or gates of the transistors M51 and M52. The second input voltage V.sub.2 is applied between the input ends or gates of the transistors M53 and M54.
A first subtracter 7 has a similar configuration to the adder 6, however, is different therefrom in input voltage. The subtracter 7 is comprised of four MOS transistors M59, M60, M61 and M62 whose capacities (W/L) are the same, and two constant current sources (current I.sub.0) which drive the pair of the transistors M59 and M60 and that of the transistors M61 and M62, respectively. The first input voltage V.sub.1 is applied between the input ends or gates of the transistors M59 and M60 with the same polarity as that of the transistors M51 and M52 of the adder 6. The second input voltage V.sub.2 is applied between the input ends or gates of the transistors M61 and M62 with the opposite polarity as that of the transistors M53 and M54 of the adder 6.
The first squarer 8 is comprised of four MOS transistors M55, M56, M57 and M58 and two constant current sources (current I.sub.01) which drive the pair of the transistors M55 and M56 and that of the transistors M57 and M58, respectively. The transistors M55 and M56 are different in capacity from each other and the transistors M57 and M58 are also different in capacity from each other. When the capacities of the transistors M55, M56, M57 and M58 are defined as (W55/L55), (W56/L56), (W57/L57) and (W58/L58), respectively,
is established, where K>1.
The gates of the transistors M55 and M58 are connected to the drains of the transistors M52 and M54, the gates of the transistors M56 and M57 are connected to the drains of the transistors M51 and M53.
The second squarer 9 has a similar configuration to that of the first squarer 8. The second squarer 9 is comprised of four MOS transistors M63, M64, M65 and M66 and two constant current sources (current I.sub.01) which drive the pair of the transistors M63 and M64 and that of the transistors M65 and M66, respectively. The transistors M63 and M64 are different in capacity from each other and the transistors M65 and M66 are also different in capacity from each other. Similar to the first squarer 8, the capacities (W63/L63), (W64/L64), (W65/L65) and (W66/L66) of the respective transistors M63, M64, M65 and M66 has the following relationships as
where K>1.
In the second squarer 9, the gates of the transistors M63 and M66 are connected to the drains of the transistors M60 and M62 of the first subtracter 7, and the gates of the transistors M64 and M65 are connected to the drains of the transistors M63 and M65 thereof. Further, the gates of the transistors M64 and M65 are connected to the drains of the transistors M59 and M61 of the first subtracter 7, on the one hand, and connected to the drains of the transistors M56 and M58 of the first squarer 8, on the other hand.
The drains of the transistors M55 and M57 of the first squarer 8 and the drains of the transistors M66 and M64 of the second squarer 9 are connected in common to form one of output ends. The drains of the transistors M56 and M58 of the first squarer 8 and the drains of the transistors M65 and M63 of the second squarer 9 are connected in common to form the other of the output ends. These output ends thus formed are respectively connected to the input ends of the second subtracter 10.
Next, the operation principle of the prior art multiplier as above will be described below.
With the adder 6, since the four MOS transistors M51, M52, M53 and M54 are equal in capacity (W/L) to each other, they have the same transconductance parameters, respectively. Then, the transconductance parameter .alpha..sub.1 is expressed as
using the capacity (W51/L51) of the transistor M51, where .mu..sub.n is the carrier mobility, C.sub.0X is the gate oxide capacitance per unit area, so that the drain currents I.sub.d1, I.sub.d2, I.sub.d3 and I.sub.d4 of the respective transistors M51, M52, M53 and M54 are expressed as the following equations 1--1, 1-2, 1-3 and 1-4, respectively, where V.sub.GS1, V.sub.GS2, V.sub.GS3 and V.sub.GS4 are the gate-source voltages of the transistors M51, M52, M53 and M54, respectively, and V.sub.TH is the threshold voltage of these transistors.
Besides, I.sub.d1 +I.sub.d2 =I.sub.0, I.sub.d3 +I.sub.d4 =I.sub.0, V.sub.GS1 -V.sub.GS2 =V.sub.1, V.sub.GS3 -V.sub.GS4 =V.sub.2 are established, and the current differences (I.sub.d1 -I.sub.d2) and (I.sub.d3 -I.sub.d4) are expressed as the following equations 2 and 3, respectively, so that the differential output current (I.sub.A -I.sub.B) can be obtained as the following equation 4. ##EQU1##
The equations 2 and 3 show the transfer characteristics of the differential pair of the MOS transistors. From the equations 2 and 3, it is seen that the current differences (I.sub.d1 -I.sub.d2) and (I.sub.d3 -I.sub.d4) are in proportion to the input voltages V.sub.1 and V.sub.2 in small signal applications, respectively. Therefore, from the equation 4, the differential output current (I.sub.A -I.sub.B) has an adding characteristic with good linearity when the input voltages V.sub.1 and V.sub.2 are small in value.
In order to use the adder 6 as a subtracter, the second input voltage V.sub.2 is required to be applied thereto with opposite polarity. Then, in the first subtracter 7, the second input voltage V.sub.2 is applied thereto with such polarity.
With the first subtracter 7, the drain currents of the respective transistors M59, M60, M61 and M62 are defined as I.sub.d11, I.sub.d12, I.sub.d13 and I.sub.d14, respectively, the current differences (I.sub.d11 -I.sub.d12) and (I.sub.d13 -I.sub.d14) are expressed as the following equations 5 and 6, respectively, and the differential output current (I.sub.c -I.sub.D) is expressed as the following equation 7. ##EQU2##
Accordingly, the differential output voltage V.sub.A of the adder 6 and the differential output voltage V.sub.B of the first subtracter 7 are expressed as the following equations 8 and 9, respectively. ##EQU3##
With the first squarer 8, since the capacity ratios (W56/L56)/(W55/L55) and (W58/L58)/(W57/L57) of the MOS transistors M55 and M56 and the transistors M57 and M58 are K. The transconductance parameter .alpha..sub.2 is expressed as
using the capacity (W55/L55) of the transistor M55, so that the drain currents I.sub.d5, I.sub.d6, I.sub.d7 and I.sub.d8 of the respective transistors M55, M56, M57 and M58 are expressed as the following equations 10-1, 10-2, 10-3 and 10-4, respectively, where V.sub.GS5, V.sub.GS6, V.sub.GS7 and V.sub.GS8 are the gate-source voltages of the transistors M55, M56, M57 and M58, respectively, and V.sub.TH is the threshold voltage of these transistors.
Besides, I.sub.d5 +I.sub.d6 =I.sub.01, I.sub.d7 +I.sub.d8 =I.sub.01, V.sub.GS5 -V.sub.GS6 =V.sub.GS8 -V.sub.GS7 =V.sub.A are established, and the current differences (I.sub.d5 -I.sub.d6) and (I.sub.d7 -I.sub.d8) are expressed as the following equations 11 and 12, respectively. ##EQU4##
Then, the differential output current (I.sub.E -I.sub.F) can be expressed as the following equation 13. From the equation 13, it is seen that the differential output current (I.sub.E -I.sub.F) is in proportion to the square of the input voltage V.sub.A. ##EQU5##
With the second squarer 9, the differential output current (I.sub.G -I.sub.H) can be expressed as the following equation 14, in the same way, where I.sub.d15, I.sub.d16, I.sub.d17 and I.sub.d18 are the drain currents of the respective transistors M63, M64, M65 and M66. From the equation 14, it is seen that the differential output current (I.sub.G -I.sub.H) is in proportion to the square of its input voltage V.sub.B. ##EQU6##
In the second subtracter 10, the differential output currents I.sub.z (=I.sub.E -I.sub.F) and I.sub.2 (=I.sub.G -I.sub.H) of the first and second squarers 9 and 10 are added with their polarity being opposite, so that the differential current (I.sub.1 -I.sub.2) is expressed as the following equation 15. ##EQU7##
By substituting the equations 8 and 9 into the equation 15 to replace V.sub.A and V.sub.B, the following equation 16 can be obtained. ##EQU8##
Then, by ignoring the terms of V.sub.1.sup.2 and V.sub.2.sup.2 in the equation 16, the following equation 17 can be given. From the equation 17, it is seen that the circuit shown in FIG. 2 has a multiplying function. ##EQU9##
FIG. 3 shows a result of computer simulation, which is carried out under the condition that R.sub.L =5 k.OMEGA., I.sub.0 =100 .mu.A, I.sub.01 = 10 .mu.A, W51=20 .mu.m, L51=5 .mu.m, W55=10 .mu.m, L55=5 .mu.m, K=5, C.sub.0X =320 .ANG..
FIG. 3 shows the relations between the differential output current and the first input voltage V.sub.1 with the second input voltage V.sub.2 as a parameter, however, the same result is obtained by replacing the first input voltage V.sub.1 with the second input voltage V.sub.2, and vice versa.
The prior art multiplier shown in FIG. 2 is comprised of MOS transistors, however, the same multiplying operation can be obtained by using bipolar transistors in place of the MOS transistors. In the case, each squarer is composed of a differential pair of transistors whose emitter area are different from each other.
It is well known that there is the minimum unit (area) of a transistor formed on semiconductor integrated circuits in order to generate desired functions, so that it is preferable to form all transistors as the minimum unit considering its current consumption. However, with the prior art multiplier shown in FIG. 2, since each differential pair of the first and second squarers is comprised of two MOS transistors whose capacities or (W/L) are different each other, all the transistors cannot be formed as the minimum unit, and as a result, there arises a problem that current consumption of the integrated circuits is made large.
In addition, with the prior art multiplier, each differential pair is provided with a constant current source, so that four constant current sources are required in total for the first and second squarers. As a result, there arises another problem that the configuration of the integrated circuits is complex.
Summary of the Invention
An object of the present invention is to provide a multiplier in which its circuit configuration can be simplified and its current consumption can be reduced.
A multiplier according to a first aspect of the present invention comprises first and second quadritail circuits. Each of the quadritail circuits has two pairs of transistors whose capacities are the same and whose output ends are connected in common, respectively, and is driven by a constant current source.
In the first quadritail circuit, input ends of a first pair of the transistors are respectively applied with voltages which are opposite in phase to each other and equal in absolute value to the sum of first and second input voltages. Input ends of a second pair of the transistors are connected in common to be applied with a middle point voltage of the voltage applied between the input ends of the first pair.
In the second quadritail circuit, input ends of a third pair of the transistors are respectively applied with voltages which are opposite in phase to each other and equal in absolute value to the difference of the first and second input voltages. Input ends of a fourth pair of the transistors are connected in common to be applied with a middle point voltage of the voltage applied between the input ends of the third pair.
The common-connected output ends of the first pair of the first quadritail circuit and the common-connected output ends of the fourth pair of the second quadritail circuit are connected in common to form one of differential output ends. Similarly, the common-connected output ends of the second pair of the first quadritail circuit and the common-connected output end of the third pair of the second quadritail circuit are connected in common to form the other of the differential output ends. An output signal showing a result of multiplication is derived from the differential output ends thus formed.
A multiplier according to a second aspect of the present invention also comprises first and second quadritail circuits, similar to the multiplier according to the first aspect, and the connections of their first to fourth pairs of the transistors are the same as that of the first aspect. However, input voltages to the first and second quadritail circuits are different from those of the first aspect.
In the multiplier according to the second aspect, input ends of the first pair of the transistors of the first quadritail circuit are respectively applied with first and second input voltages. One input end of the third pair of the second quadritail circuit is applied with the first input voltage with the same phase or polarity as that of the first quadritail circuit. The other input end of the third pair are applied with the second input voltage with the opposite phase or polarity to the first quadritail circuit.
A multiplier according to a third aspect of the present invention comprises first, second and third quadritail circuits. Each of the quadritail circuits has two pairs of transistors whose output ends are connected in common, respectively, and is driven by a constant current source.
In the first quadritail circuit, a first input voltage is applied between input ends of a first pair of the transistors, and input ends of a second pair of the transistors are connected in common to be applied with a middle point voltage of the voltage applied between the input ends of the first pair.
In the second quadritail circuit, a second input voltage is applied between input ends of a third pair of the transistors, and input ends of a fourth pair of the transistors are connected in common to be applied with a middle point voltage of the voltage applied between the input ends of the third pair.
In the third quadritail circuit, the difference of the first and second input voltages is applied between input ends of a fifth pair of the transistors, and input ends of a sixth pair of the transistors are connected in common to be applied with a middle point voltage of the voltage applied between the input ends of the fifth pair.
The common-connected output ends of the first pair of the first quadritail circuit, the common-connected output ends of the third pair of the second quadritail circuit and the common-connected output ends of the sixth pair of the third quadritail circuit are connected in common to form one of differential output ends. Similarly, the common-connected output ends of the second pair of the first quadritail circuit, the common-connected output ends of the fourth pair of the second quadritail circuit and the common-connected output ends of the fifth pair of the third quadritail circuit are connected in common to form the other of the differential output ends. An output signal showing a result of multiplication is derived from the differential output ends thus formed.
In the multiplier according to the first to third aspects of the present invention, bipolar transistors or MOS transistors may be used. In case of the bipolar transistors being used, preferably, the four transistors constituting each of the quadritail circuits have diodes or resistors at their emitters, respectively.
With the multipliers of the first and second aspects of the present invention, each of the first and second quadritail circuits contains four transistors whose capacities are the same and one constant current source to obtain the square-law characteristic accurately or approximately. As a result, the number of current sources required is reduced by half compared with the prior art multiplier, so that the circuit configuration can be simplified.
In addition, since the transistors with the same capacities are used, all of the transistors can be made as the minimum unit, and as a result, the current consumption can be largely reduced.
With the multiplier of the third aspects of the present invention, the same configuration is employed as those of the first and second aspects excepting that the first to third quadritail circuits are provided, so that the same effects of advantages are obtained as those of the first and second aspects.
Brief Description of the Drawings
FIG. 1 is a block diagram showing a prior art multiplier.
FIG. 2 is a circuit diagram showing a prior art multiplier.
FIG. 3 is a graph showing input-output characteristics of a squarer used in the prior art multiplier.
FIG. 4 is a circuit diagram of a quadritail circuit composed of bipolar transistors.
FIG. 5 is a diagram showing input-output characteristics of the quadritail circuit shown in FIG. 4.
FIG. 6 is a circuit diagram of a multiplier according to a first embodiment of the present invention.
FIG. 7 is a diagram showing input-output characteristics of the multiplier shown in FIG. 6.
FIG. 8 is a circuit diagram of a quadritail circuit composed of MOS transistors.
FIG. 9 is a diagram showing input-output characteristics of the quadritail circuit shown in FIG. 8.
FIG. 10 is a circuit diagram of a multiplier according to a second embodiment of the present invention.
FIG. 11 is a diagram showing input-output characteristics of the multiplier shown in FIG. 10.
FIG. 12 is a diagram showing gain characteristics of the multiplier shown in FIG. 10.
FIG. 13 is a block diagram showing a multiplier using two quadritail circuits.
FIG. 14 is a circuit diagram of a multiplier according to a third embodiment of the present invention.
FIG. 15 is a circuit diagram of a multiplier according to a fourth embodiment of the present invention.
FIG. 16 is a block diagram showing a multiplier using three quadritail circuits.
FIG. 17 is a circuit diagram of a multiplier according to a fifth embodiment of the present invention.
FIG. 18 is a circuit diagram of a multiplier according to a sixth embodiment of the present invention.
FIG. 19 is a circuit diagram of a quadritail circuit used for a multiplier according to a seventh embodiment of the present invention.
FIG. 20 is a circuit diagram of a quadritail circuit used for a multiplier according to a eighth embodiment of the present invention.
Detailed Description of the Preferred Embodiments
Preferred embodiments of the present invention will be described below referring to FIGS. 4 to 20.
As described above, in the prior art multiplier shown in FIG. 2 which was developed by the inventor, each of the first and second squarers is comprised of two pairs of the MOS transistors whose capacities or (W/L) ratios are different from each other, and is required for two constant current sources. Accordingly, it is desirable that the squarer is comprised of MOS or bipolar transistors whose capacities are the same and a single constant current source for driving these transistors. An example of a circuit having such configuration was disclosed in the Japanese Examined Patent Publication 3-47770 and its corresponding U.S. Pat. No. 4,724,337, which is a full-wave rectifier composed of bipolar transistors. An operation of a full-wave rectifier can be roughly approximated to that of a squarer, in general.
FIG. 4 shows the full-wave rectifier disclosed by the Japanese Examined Patent Publication 3-47770, in which four bipolar transistors Q1", Q2", Q3" and Q4" having the same capacities are provided. The emitters of the transistors Q1", Q2", Q3" and Q4" are connected in common to a constant current source (current I.sub.0) for driving them. The bases of the transistors Q1" and Q2" are connected in common. A first input voltage (1/2)V.sub.IN is applied between the common-connected bases of the transistors Q1" and Q2" and the base of the transistor Q3". A second input voltage -(1/2)V.sub.IN is applied between the common-connected bases of the transistors Q1" and Q2" and the base of the transistor Q4". The collectors of the transistors Q1" and Q2" are connected in common to form one of output ends, and the collectors of the transistors Q3" and Q4" are connected in common to form the other of the output ends.
With the circuit shown in FIG. 4, since the bases of the transistors Q1" and Q2" are biased by a common direct current (DC) voltage, the collector currents I.sub.C1 and I.sub.C2 of the respective transistors Q1" and Q2" can be expressed as the following equation 18.
where I.sub.S is the saturation current, V.sub.BE is the base-emitter voltage of the transistor Q1" and Q2" and V.sub.T is the thermal voltage. The thermal voltage V.sub.T is expressed as V.sub.T =kT/q where k is Boltzmann's constant, T is the absolute temperature in degrees Kelvin and q is the charge of an electron.
Since the bases of the transistors Q3" and Q4" are respectively applied with the voltages +(1/2)V.sub.IN and -(1/2)V.sub.IN with the common-connected bases of the transistors Q1" and Q2" as a reference, the collector currents I.sub.C3 and I.sub.C4 of the respective transistors Q3" and Q4" can be expressed as the following equations 19-1 and 19-2.
Besides, currents I.sub.E and I.sub.L are defined as I.sub.C1 +I.sub.C2 =I.sub.E, I.sub.C3 +I.sub.C4 =I.sub.L and I.sub.E +I.sub.L =.alpha..sub.F I.sub.O is established, where .alpha..sub.F is the DC common-base current gain factor. Then, the currents I.sub.R and I.sub.L are expressed as the following equations 20 and 21, respectively. ##EQU10##
FIG. 5 shows the curves of the currents I.sub.E and I.sub.L and their differential current (I.sub.L -I.sub.E). From FIG. 5, it is seen that if the voltage V.sub.IN is limited is value, or if the absolute value of the voltage V.sub.IN is about 3 V.sub.T or less, the square-law characteristic is approximately obtained. This means that the circuit shown in FIG. 4 can be used as a squarer for a multiplier.
Therefore, in the present invention, a circuit having such a configuration as shown in FIG. 4 is called as a "quadritail circuit", and a multiplier is obtained by using two of the quadritail circuits. The quadritail circuit may be composed of bipolar transistors or MOS transistors.
First Embodiment
First, a multiplier composed of two bipolar quadritail circuits is described below.
FIG. 6 shows a multiplier according to a first embodiment of the present invention. In this multiplier, two voltages of +(V.sub.1 +V.sub.2) and -(V.sub.1 +V.sub.2) which are opposite in phase to each other and equal in absolute value to the sum of a first input voltage V.sub.1 and a second input voltage V.sub.2, which are to be multiplied, and two voltages of +(V.sub.1 -V.sub.2) and -(V.sub.1 -V.sub.2) which are opposite in phase to each other and equal in absolute value to the difference of the first input voltage V.sub.1 and the second input voltage V.sub.2. Any circuit can be used to obtain these voltages .+-.(V.sub.1 +V.sub.2) and .+-.(V.sub.1 -V.sub.2), for example, an adder and a subtracter having the same configurations as those of the adder 6 and the first subtracter 7 as shown in FIG. 2 may be used.
In FIG. 6, a second quadritail circuit on the upper side, which is composed of bipolar transistors Q3, Q4, Q5 and Q6 and a constant current source (current I.sub.0), has a function corresponding to that of the second squarer 9 shown in FIG. 2. A first quadritail circuit on the lower side, which is composed of bipolar transistors Q9, Q10, Q11 and Q12 and a constant current source (current I.sub.0), has a function corresponding to that of the first squarer 8 shown in FIG. 2.
In the second quadritail circuit, the collectors of the transistors Q3 and Q4 are connected in common. The base of the transistor Q4 is applied with the voltage (V.sub.1 -V.sub.2) and the base of the transistor Q3 is applied with the voltage -(V.sub.1 -V.sub.2) opposite in phase to the voltage (V.sub.1 -V.sub.2). The collectors of the transistors Q5 and Q6 are connected in common to the base of the transistor Q3 through a resistor (resistance R.sub.2), on the one hand, and to the base of the transistor Q4 through a resistor (resistance R.sub.2), on the other hand; and as a result, the common-connected bases of the transistor Q5 and Q6 are applied with a DC bias voltage, respectively. This DC bias voltage is equal to the voltage at a middle point of the voltage applied between the bases of the transistors Q3 and Q4.
The emitters of the transistors Q3, Q4, Q5 and Q6 are connected in common to the current source for driving them.
Similarly, in the first quadritail circuit, the collectors of the transistors Q9 and Q10 are connected in common. The base of the transistor Q10 is applied with the voltage (V.sub.1 +V.sub.2) and the base of the transistor Q9 is applied with the voltage -(V.sub.1 +V.sub.2) opposite in phase to the voltage (V.sub.1 +V.sub.2). The collectors of the transistors Q11 and Q12 are connected in common to the base of the transistor Q9 through a resistor (resistance R.sub.2), on the one hand, and to the base of the transistor Q10 through a resistor (resistance R.sub.2), on the other hand; and as a result, the common-connected bases of the transistor Q11 and Q12 are applied with a DC bias voltage, respectively. This DC bias voltage is also equal to the voltage at a middle point of the voltage applied between the bases of the transistors Q9 and Q10.
The emitters of the transistors Q9, Q10, Q11 and Q12 are connected in common to the current source for driving them.
Between the first and second quadritail circuits, the collectors of the transistors Q3 and Q4 and the collectors of the transistors Q11 and Q12 are connected in common to form one of differential output ends. The collectors of the transistors Q5 and Q6 and the collectors of the transistors Q9 and Q10 are connected in common to form the other of the differential output ends.
Here, collector currents of the transistors Q3, Q4, Q5 and Q6 are defined as I.sub.C3, I.sub.C4, I.sub.C5 and I.sub.C6, and collector currents of the transistors Q9, Q10, Q1 and Q12 are defined as I.sub.C9, I.sub.C10, I.sub.C11 and I.sub.C12, respectively. Then, the sum (I.sub.C3 +I.sub.C4) of the currents I.sub.C3 and I.sub.C4, the sum (I.sub.C5 +I.sub.C6) of the currents I.sub.C5 and I.sub.C6, the sum (I.sub.C9 +I.sub.C10) of the currents I.sub.C9 and I.sub.C10 and the sum (I.sub.C11 +I.sub.C12) of the currents of I.sub.C11 and I.sub.C12 are expressed as the following equations 22, 23, 24 and 25, respectively. ##EQU11##
As a result, the differential output current .DELTA.I {=(I.sub.C3 +I.sub.C4 +I.sub.C11 +I.sub.C12)-(I.sub.C5 +I.sub.C6 +I.sub.C9 +I.sub.C10)} of the multiplier can be expressed as the following equation 26. ##EQU12##
FIG. 7 shows a relation between the differential output current .DELTA.I and the voltage V.sub.1 with the voltage V.sub.2 as a parameter. From FIG. 7, it can be seen that multiplying characteristics are obtained in the range that the absolute value of the voltage V.sub.1 is about 1.5 V.sub.T or less.
Second Embodiment
FIG. 8 shows a quadritail circuit composed of MOS transistors M1, M2, M3, and M4, which is equivalent to that in FIG. 4.
Drain currents of the transistors M1, M2, M3 and M4 are defined as I.sub.D1, I.sub.D2, I.sub.D3 and I.sub.D4, and the sums of the drain currents are defined as I.sub.D1 +I.sub.D2 =I.sub.E and I.sub.D3 +I.sub.D4 =I.sub.L, then I.sub.E +I.sub.L =I.sub.0 is established. In the first embodiment using the bipolar transistors, the transconductance parameter is expressed by .alpha..sub.1 or .alpha..sub.2 in the prior art multiplier, it is expressed by .beta. here. The drain currents I.sub.D1 and I.sub.D2 are expressed as the following equation 27.
The gates of the transistors M3 and M4 are respectively applied with the voltages (1/2)V.sub.IN and -(1/2)V.sub.IN, so that the drain currents I.sub.D3 and I.sub.D4 can be given as the following equations 28-1 and 28-2, respectively.
Therefore, the currents I.sub.E and I.sub.L can be expressed as the following equations 29-1 and 29-2, respectively. From these equations, the both currents I.sub.E and I.sub.L have square-law characteristics with respect to the voltage V.sub.IN.
In fact, the input-output characteristics of the quadritail circuit in FIG. 8 is obtained as shown in FIG. 9. It can be seen from FIG. 9 that the currents I.sub.E and I.sub.L respectively show ideal square-law characteristics in the input voltage range of .vertline.V.sub.IN .vertline..ltoreq.(2I.sub.0 /3.beta.).sup.1/2.
As described above, an approximate square-law characteristic can be realized in each quadritail circuit shown in FIG. 4, however, an accurate square-law characteristic can be realized in each quadritail circuit shown in FIG. 8.
A multiplier according to a second embodiment of the present invention is shown in FIG. 10, which are composed of two MOS quadritail circuits shown in FIG. 8.
In FIG. 10, a first quadritail circuit on the left side, which is composed of MOS transistors M1, M2, M3 and M4 and a constant current source (current I.sub.0), has a function corresponding to the first squarer 8 shown in FIG. 2, and a second quadritail circuit on the right side, which is composed of MOS transistors M5, M6, M7 and M8 and a constant current source (current I.sub.0), has a function corresponding to the second squarer 9 shown in FIG. 2.
The first quadritail circuit on the left side has the same configuration as that of the MOS quadritail circuit shown in FIG. 8. The drains of the transistors M1 and M2 are connected in common, and the drains of the transistors M3 and M4 are connected in common. The gate of the transistor M3 is applied with the voltage (V.sub.1 +V.sub.2) and the gate of the transistor M4 is applied with the voltage -(V.sub.1 +V.sub.2) equal in absolute value and opposite in phase to the voltage (V.sub.1 +V.sub.2), with the common-connected gates of the transistors M1 and M2 as a reference. The common-connected gates of the transistor M1 and M2 are applied with a DC bias voltage, respectively, which is equal to the voltage at a middle point of the voltage applied between the gates of the transistors M3 and M4.
The sources of the transistors M1, M2, M3 and M4 are connected in common to the current source for driving them.
Similarly, a second quadritail circuit on the right side, the drains of the transistors M5 and M6 are connected in common, and the drains of the transistors M7 and M8 are connected in common. The gate of the transistor M7 is applied with the voltage (V.sub.1 -V.sub.2) and the gate of the transistor M8 is applied with the voltage -(V.sub.1 -V.sub.2) equal in absolute value and opposite in phase to the voltage (V.sub.1 -V.sub.2), with the common-connected gates of the transistors M5 and M6 as a reference. The common-connected gates of the transistor M5 and M6 are applied with a DC bias voltage, respectively, which is equal to the voltage at a middle point of the voltage applied between the gates of the transistors M7 and M8.
The sources of the transistors M5, M6, M7 and M8 are connected in common to the current source for driving them.
Between the first and second quadritail circuits, the common-connected gates of the transistors M1 and M2 are connected to the common-connected gates of the transistors M5 and M6. The drains of the transistors M1 and M2 and the drains of the transistors M7 and M8 are connected in common to form one of differential output ends. The drains of the transistors M3 and M4 and the drains of the transistors M5 and M6 are connected in common to form the other of the differential output ends.
In the multiplier having the above-described configuration, from the equations 29-1 and 29-2, a differential output current .DELTA.I as shown in FIG. 10 is expressed as .DELTA.I=4.beta.V.sub.1 V.sub.2 in the range of .vertline.V.sub.1 .+-.V.sub.2 .vertline..ltoreq.(1/2)(2I.sub.0 /3.beta.).sup.1/2. This means that the differential output current .DELTA.I shows a result of multiplication of the input voltages V.sub.1 and V.sub.2.
The relation between the current .DELTA.I and the voltage V.sub.1 with the voltage V.sub.2 as a parameter is shown in FIG. 11, and the gain characteristics of this multiplier is shown in FIG. 12.
Third Embodiment
Next, a multiplier according to a third embodiment on the present invention is described, in which the circuits for generating the voltages (V.sub.1 +V.sub.2) and (V.sub.1 -V.sub.2) are not required.
The multiplier of this embodiment is composed of two squarers 11 and 12 and a subtracter 13, as shown in FIG. 13. Each of the squarers 11 and 12 is composed of the above-described quadritail circuit. Also in the configuration, V.sub.0 =(V.sub.1 +V.sub.2).sup.2 -(V.sub.1 -V.sub.2).sup.2 =4V.sub.1 V.sub.2 is established, so that a result of multiplication of the voltage V.sub.1 and V.sub.2 can be obtained.
The reason for being able to cancel the circuits for generating the voltages (V.sub.1 +V.sub.2) and (V.sub.1 -V.sub.2) is as follows: The squarers 11 and 12 have differential input ends, respectively, so that the difference voltage (V.sub.1 -V.sub.2) can be obtained by applying the voltages V.sub.1 and V.sub.2 to the differential input ends of the each squarer, respectively, and the sum voltage (V.sub.1 +V.sub.2) can be obtained by applying the voltage V.sub.1 and the voltage -V.sub.2 opposite in phase of the voltage V.sub.2 to the differential input ends thereof.
To obtain an output signal opposite in phase to an input signal, it is required for an inverting amplifier. However, an inverting amplifier is simpler in configuration than an adder and a subtracter, so that it is very significant that the circuits for generating the sum and difference of the voltages V.sub.I and V.sub.2 can be cancelled.
FIG. 14 shows a multiplier according to a third embodiment of the present invention using the configuration as shown in FIG. 13, which comprises two bipolar quadritail circuits. This multiplier is composed of the circuit shown in FIG. 6 and two differential pair of bipolar transistors Q1 and Q2, and Q7 and Q8. Therefore, a description about the circuit shown in FIG. 6 is omitted for the sake of simplification by attaching the same reference numerals to the corresponding elements, and the configuration about the differential pairs is only described here.
In FIG. 14, the second differential pair comprises the transistor Q1 and Q2 whose emitters are connected in common to a constant current source (current I.sub.01) for driving them and whose collectors are connected through two load resistors (resistance R.sub.1) to each other. The voltage V.sub.1 is differentially applied between the bases of the transistors Q1 and Q2, and the inverted output voltage -V.sub.1 and the non-inverted output voltage V.sub.1 are generated at their collectors, respectively. Only the non-inverted output voltage V.sub.1 is applied to the bases of the transistors Q3 and Q9 belonging to the second and first quadritail circuits, respectively.
Similarly, the first differential pair comprises the transistor Q7 and Q8 whose emitters are connected in common to a constant current source (current I.sub.01) for driving them and whose collectors are connected through two load resistors (resistance R.sub.1) to each other. The voltage V.sub.2 is differentially applied between the bases of the transistors Q7 and Q8, and the inverted output voltage -V.sub.1 and the non-inverted output voltage V.sub.1 are generated at their collectors, respectively. The inverted output voltage -V.sub.2 is applied to the base of the transistor Q10 belonging to the first quadritail circuit, and the non-inverted output voltage V.sub.2 is applied to the base of the transistor Q4 belonging to the second quadritail circuit.
The second quadritail circuit has differential input ends, so that the middle point voltage which is obtained by dividing the voltage applied between the bases of the transistors Q3 and Q4 through the two resistor (resistance R.sub.2) is applied to the common-connected bases of the transistors Q5 and Q6. About the first quadritail circuit, similarly, the middle point voltage obtained by dividing the voltage applied between the bases of the transistors Q9 and Q10 through the two resistor (resistance R.sub.2) is applied to the common-connected bases of the transistors Q11 and Q12.
Accordingly, in the second quadritail circuit, with the middle point voltage at the common-connected bases of the transistors Q5 and Q6 as a reference, the voltages +(1/2) (V.sub.1 -V.sub.2) and -(1/2)(V.sub.1 -V.sub.2) are applied to the bases of the transistors Q3 and Q4, respectively. In the first quadritail circuit, with the middle point voltage at the common-connected bases of the transistors Q11 and Q12 as a reference, the voltages +(1/2)(V.sub.1 +V.sub.2) and -(1/2) (V.sub.1 +V.sub.2) are applied to the bases of the transistors Q9 and Q10, respectively.
Comparing the quadritail circuits of this embodiment with those of the first embodiment in FIG. 6, their input voltages are opposite in polarity or phase to each other. However, since the quadritail circuits serve to provide the square-law characteristics, there arises no problem due to the opposition in polarity or phase.
It should be noted that the input voltage in the multiplier of the third embodiment in FIG. 14 is half as much as that in the first embodiment in FIG. 6. In other words, the operating input voltage of the first embodiment is about 1.5 V.sub.T or less in absolute value, as shown in FIG. 7, however, in the third embodiment, it is increased to about 3 V.sub.T.
From the equation 26, in this embodiment, the differential output current .DELTA.I showing a result of multiplication is expressed as the following equation 30. ##EQU13##
Fourth Embodiment
FIG. 15 shows a multiplier according to a fourth embodiment using two MOS quadritail circuits. This multiplier comprises the multiplier of the second embodiment shown in FIG. 10 and resistors (resistance R.sub.1), so that the description about the circuit shown in FIG. 10 is omitted for the sake of simplification by attaching the same reference numerals to the corresponding elements. Also in the embodiment, the circuits for generating the voltages (V.sub.1 +V.sub.2) and (V.sub.1 -V.sub.2) are not required.
In FIG. 15, the common-connected gates of the transistors M1 and M2 is connected through a resistor (resistance R.sub.1) to the gate of the transistor M3, on the one hand, and is connected through a resistor (resistance R.sub.1) to the gate of the transistor M4, on the other hand. Similarly, the common-connected gates of the transistors M5 and M6 is connected through a resistor (resistance R.sub.1) to the gate of the transistor M7, on the one hand, and is connected through a resistor (resistance R.sub.1) to the gate of the transistor M8, on the other hand.
The gates of the transistors M3 and M7 are connected in common to be applied with the voltage V.sub.1. The gate of the transistors M4 is applied with the opposite-phase voltage -V.sub.2, and the gate of the transistor M8 is applied with the voltage V.sub.2. The common-connected gates of the transistors M1 and M2 are applied with the middle point voltage (1/2) (V.sub.1 -V.sub.2), and the common-connected gates of the transistors M5 and M6 are applied with the middle point voltage (1/2) (V.sub.1 +V.sub.2).
In the multiplier of the fourth embodiment, the differential output current .DELTA.I showing a result of multiplication can be expressed as .DELTA.I=2.beta.V.sub.1 V.sub.2 in the range of .vertline.V.sub.1 .+-.V.sub.2 .vertline..ltoreq.(2I.sub.0 /3.beta.).sup.1/2. Similar to the third embodiment, the operating input voltage range is increased to be twice as much as that of the first embodiment shown in FIG. 6.
Fifth Embodiment
A multiplier using three squarers is shown in FIG. 16, in which .gamma. shows the transconductance parameter. A first squarer 15 has differential input ends to be applied with the first input voltage V.sub.1, a second squarer 16 has differential input ends to be applied with the second input voltage V.sub.2, and a third squarer 17 has differential input ends to be applied with the difference (V.sub.1 -V.sub.2) of the first and second input voltages V.sub.1 and V.sub.2.
The positive-phase output end of the first squarer 15, the positive-phase output end of the second squarer 16 and the negative-phase output end of the third squarer 17 are connected in common to form one of differential output ends. The negative-phase output end of the first squarer 15, the negative-phase output end of the second squarer 16 and the positive-phase output end of the third squarer 17 are connected in common to form the other of the differential output ends. The differential output current .DELTA.I is derived from the differential output ends thus formed.
The differential output current .DELTA.I can be expressed as the following equation 31, from which the circuit shown in FIG. 16 has a multiplication characteristics is seen.
In FIG. 16, the respective negative-phase output ends of the first and second squarers 15 and 16 are connected in common, however, these output ends may be disconnected or floating. If they are made floating, there is an advantage that such differential input voltages as in the first to fourth embodiments are not required.
Besides, since the differential output current of the quadritail circuit does not contain a DC component, there arises no offset current in it even if a multiplier is composed of an odd number of the quadritail circuits. As a result, there is another advantage that no additional circuit is required for cancelling the offset at the output ends of the multiplier.
FIG. 17 shows a multiplier according to a fifth embodiment of the present invention in which three bipolar quadritail circuits are used. The multiplier is composed of first, second and third quadritail circuits each of which has the same configuration as that shown in FIGS. 6 and 14. A first quadritail circuit on the upper side acts as the first squarer 15 shown in FIG. 16, the second quadritail circuit in the middle acts as the second squarer 16, and the third quadritail circuit on the lower side acts as the third squarer 17.
The first quadritail circuit is composed of bipolar transistors Q1', Q2', Q3' and Q4', a constant current source (current I.sub.0) and resistor (resistance R.sub.2 '), the second quadritail circuit is composed of bipolar transistors Q5', Q6', Q7' and Q8', a constant current source (current I.sub.0) and resistor (resistance R.sub.2 '), and the third quadritail circuit is composed of bipolar transistors Q9', Q10', Q11' and Q12', a constant current source (current I.sub.0) and resistor (resistance R.sub.2 ').
In the first quadritail circuit, The collectors of the transistors Q1' and Q2' are connected in common, and the collectors of the transistors Q3' and Q4' are connected in common. The voltage V.sub.1 is applied between the bases of the transistors Q1' and Q2'. The bases of the transistors Q3' and Q4' are connected in common to the base of the transistor Q1' through the resistor (resistance R.sub.2 '), on the one hand, and to the base of the transistor Q2' through the resistor (resistance R.sub.2 '), on the other hand; and as a result, the common-connected bases of the transistor Q3' and Q4' are applied with a DC bias voltage, respectively. This DC bias voltage is equal to the voltage at a middle point of the voltage applied between the bases of the transistors Q1' and Q2' , or (1/2)V.sub.1.
The emitters of the transistors Q1', Q2', Q3' and Q4' are connected in common to the current source for driving them.
Similarly, in the second quadritail circuit, the collectors of the transistors Q5' and Q6' are connected in common, and the collectors of the transistors Q7' and Q8' are connected in common. The voltage V.sub.2 is applied between the bases of the transistors Q5' and Q6'. The bases of the transistors Q7' and Q8' are connected in common to the base of the transistor Q5' through the resistor (resistance R.sub.2 '), on the one hand, and to the base of the transistor Q6' through the resistor (resistance R.sub.2 '), on the other hand; and as a result, the common-connected bases of the transistor Q7' and Q8' are applied with a DC bias voltage, respectively. This DC bias voltage is equal to the voltage at a middle point of the voltage applied between the bases of the transistors Q5' and Q6', or (1/2)V.sub.2.
The emitters of the transistors Q5', Q6', Q7' and Q8' are connected in common to the current source for driving them.
In the third quadritail circuit, the collectors of the transistors Q9' and Q10' are connected in common, and the collectors of the transistors Q11' and Q12' are connected in common. The difference voltage (V.sub.1 -V.sub.2) is applied between the bases of the transistors Q9' and Q10'. The bases of the transistors Q11' and Q2' are connected in common to the base of the transistor Q9' through the resistor (resistance R.sub.2 '), on the one hand, and to the base of the transistor Q10' through the resistor (resistance R.sub.2 '), on the other hand; and as a result, the common-connected bases of the transistor Q7' and Q8' are applied with a DC bias voltage, respectively. This DC bias voltage is equal to the voltage at a middle point of the voltage applied between the bases of the transistors Q9' and Q10', or (1/2)(V.sub.1 -V.sub.2).
The emitters of the transistors Q9', Q10', Q11' and Q12' are connected in common to the current source for driving them.
Among the first, second and third quadritail circuits, the common-connected collectors (positive-phase side) of the transistors Q1' and Q2', the common-connected collectors (positive-phase side) of the transistors Q5' and Q6' and the common-connected collectors (negative-phase side) of the transistors Q9' and Q10' are connected in common to form one of differential output ends. Similarly, the common-connected collectors (negative-phase side) of the transistors Q3' and Q4', the common-connected collectors (negative-phase side) of the transistors Q7' and Q8' and the common-connected collectors (positive-phase side) of the transistors Q11' and Q12' are connected in common to form the other of the differential output ends. The differential output currents .DELTA.I showing a result of multiplication is derived from the differential output ends thus formed (see the equation 31).
As described above, the bipolar quadritail circuit has the square-law characteristic as shown in FIG. 5, so that the operating input voltage range which can be considered to have the square-law characteristic is determined with respect to each quadritail circuit. Therefore, the multiplier of the fifth embodiment shown in FIG. 16 is narrower in operating input voltage range than that of the third embodiment shown in FIG. 14.
Sixth embodiment
FIG. 18 shows a multiplier according to a sixth embodiment of the present invention in which three MOS quadritail circuits are used. This multiplier is similar in configuration to that of the fourth embodiment shown in FIG. 15.
In FIG. 18, a first quadritail circuit on the left side is composed of MOS transistors M1', M2', M3' and M4' and a constant current source (current I.sub.0). The drains of the transistors M1' and M2' are connected in common, and the drains of the transistors M3' and M4' are connected in common. The gates of the transistors M3' and M4' are respectively applied with the voltages V.sub.1 and V.sub.2. The common-connected gates of the transistors M1' and M2' are connected to the gate of the transistor M3' through a resistor (resistance R.sub.1 '), on the one hand, and to the gate of the transistors M4' through a resistor (resistance R.sub.1 '), on the other hand. The common-connected gates of the transistors M1' and M2' are applied with the middle point voltage (1/2)V.sub.1.
The sources of the transistors M1', M2', M3' and M4' are connected in common to the constant current source.
A second quadritail circuit in the middle is composed of MOS transistors M5', M6', M7' and M8' and a constant current source (current I.sub.0). The drains of the transistors M5' and M6' are connected in common, and the drains of the transistors M7' and M8' are connected in common. The gates of the transistors M7' and M8' are respectively applied with the voltages V.sub.1 and V.sub.2. The common-connected gates of the transistors M5' and M6' are connected to the gate of the transistor M7' through a resistor (resistance R.sub.1 '), on the one hand, and to the gate of the transistors M8' through a resistor (resistance R.sub.1 '), on the other hand. The common-connected gates of the transistors M5' and M6' are applied with the middle point voltage (1/2) V.sub.2.
The sources of the transistors M5', M6', M7' and M8' are connected in common to the constant current source.
Similarly, a third quadritail circuit on the right side is composed of MOS transistors M9', M10', M11' and M12' and a constant current source (current I.sub.0). The drains of the transistors M9' and M10' are connected in common, and the drains of the transistors M11' and M12' are connected in common. The gates of the transistors M11' and M12' are respectively applied with the voltages V.sub.1 and V.sub.2. The common-connected gates of the transistors M9' and M10' are connected to the gate of the transistor M11' through a resistor (resistance R.sub.1 '), on the one hand, and to the gate of the transistors M12' through a resistor (resistance R.sub.1 '), on the other hand. The common-connected gates of the transistors M9' and M10' are applied with the middle point voltage (1/2)(V.sub.1 -V.sub.2).
The sources of the transistors M9', M10', M11' and M12' are connected in common to the constant current source.
Among the first, second and third quadritail circuits, the common-connected drains (positive-phase side) of the transistors M1' and M2', the common-connected drains (positive-phase side) of the transistors M5' and M6' and the common-connected drains (negative-phase side) of the transistors M11' and Q12' are connected in common to form one of differential output ends. The common-connected drains (negative-phase side) of the transistors M3' and M4', the common-connected drains (negative-phase side) of the transistors M7' and M8' and the common-connected drains (positive-phase side) of the transistors M11' and M12' are connected in common to form the other of the differential output ends. The differential output currents .DELTA.I showing a result of multiplication is derived from the differential output ends thus formed (see the equation 31).
The square-law characteristic of the MOS quadritail circuit is determined by the ratio (W/L) of the gate-width W and gate-length L and the current value of the constant current source, as shown in FIG. 6. Therefore, to drive the multiplier of this embodiment by using the same constant current sources and to ensure the operating input voltage range equivalent to that of the multiplier in FIG. 14, the ratio (W/L) is required to be small. Concretely, the gate-width W is made narrower, and/or the gate-length L is made longer.
Seventh Embodiment
FIG. 19 shows a quadritail circuit used for a multiplier according to a seventh embodiment of the present invention. The quadritail circuit has the same configuration as that in FIG. 4, excepting that each of the bipolar transistors Q1", Q2", Q3" and Q4" has series-connected n diodes D.sub.1l to D.sub.1n, D.sub.2l to D.sub.2n, D.sub.3l to D.sub.3n and D.sub.4l to D.sub.4n at their emitters, where n is a natural number. In this quadritail circuit, the operating input voltage range which can be considered to have the square-law characteristic is increased to be n times as much as that shown in FIG. 4.
Therefore, if the quadritail circuit shown in FIG. 19 is applied into the multiplier of the fifth embodiment using three bipolar quadritail circuits shown in FIG. 17 in place of that in FIG. 4, the operating input voltage range of the multiplier can be increased to be n times. However, its operating power source voltage is increased by (0.6.times.n) volts.
Eighth Embodiment
FIG. 20 shows a quadritail circuit used for a multiplier according to a eighth embodiment of the present invention. The quadritail circuit also has the same configuration as that in FIG. 4, excepting that each of the bipolar transistors Q1", Q2", Q3" and Q4" has an resistor (resistance R.sub.1) at its emitter.
It is well known that the operating input voltage range can be increased corresponding to the product R.sub.E I.sub.O of the resistance value E.sub.E and the current value I.sub.O. In this quadritail circuit, the square-law characteristic is realized approximately, so that there is a particular value of the product R.sub.E I.sub.O in which the square-law characteristic is made better. Practically, it can be said that the particular value of the product R.sub.E I.sub.O is about 10 V.sub.r if some tolerance is acceptable. Therefore, the operating input voltage range is increased to be about 5 times as much as that shown in FIG. 4.
In the above-described embodiments, there are provided with two or three quadritail circuits each of which are connected in common at their output ends to form a pair of differential output ends, and the output current is derived from the pair of the output ends differentially. However, output currents may be derived from either differential output ends to input a subtracter, and then a result of multiplication may be obtained from the subtracter.
In addition, in the quadritail circuit, two transistors of one differential pair have emitters, bases and collectors connected in common, respectively, or have sources, gates and drains connected in common, respectively. As a result, one transistor which is twice in capacity as much as one of these two transistors may be used in place of the differential pair.
Claims
What is claimed is:
1. A multiplier comprising: a first quadritail circuit containing a first pair of first and second transistors whose capacities are the same and whose output ends are connected in common, a second pair of third and fourth transistors whose capacities are the same and whose output ends are connected in common, and a first constant current source for driving said first pair and said second pair; and a second quadritail circuit containing a third pair of fifth and sixth transistors whose capacities are the same and whose output ends are connected in common, a fourth pair of seventh and eighth transistors whose capacities are the same and whose output ends are connected in common, and a second constant current source for driving said third pair and said fourth pair; wherein in said first quadritail circuit, input ends of said first pair are respectively applied with voltages which are opposite in phase to each other and equal in absolute value to sum of a first input voltage and a second input voltage; input ends of said second pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said first pair; in said second quadritail circuit, input ends of said third pair are respectively applied with voltages which are opposite in phase to each other and equal in absolute value to difference of said first input voltage and said second input voltage; input ends of said fourth pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said third pair; and said common-connected output ends of said first pair and said common-connected output ends of said fourth pair are connected in common to form one of differential output ends, and said common-connected output ends of said second pair and said common-connected output end of said third pair are connected in common to form the other of said differential output ends.
2. The multiplier as claimed in claim 1, wherein said first to eighth transistors are bipolar transistors; bases of said third transistor and said fourth transistor are connected in common to be connected through a first resistor to a base of said first transistor on the one hand, and to be connected through a second resistor whose resistance value is equal to that of said first resistor to a base of said second transistor, on the other hand; and bases of said seventh transistor and said eighth transistor are connected in common to be connected through a third resistor to a base of said fifth transistor on the one hand, and to be connected through a fourth resistor whose resistance value is equal to that of said third resistor to a base of said sixth transistor, on the other hand.
3. The multiplier as claimed in claim 2, wherein each of said first to fourth transistors of said first quadritail circuit has at least one diode at a corresponding emitter of each of said first to fourth transistors, and emitters of said first to fourth transistors are connected through said diode to said first constant current source, respectively; and each of said fifth to eighth transistors of said second quadritail circuit has at least one diode at a corresponding emitter of each of said fifth to eighth transistors, and emitters of said fifth to eighth transistors are connected through said diode to said second constant current source, respectively.
4. The multiplier as claimed in claim 2, wherein each of said first to fourth transistors of said first quadritail circuit has a resistor at a corresponding emitter of each of said first to fourth transistors, and emitters of said first to fourth transistors are connected through said resistor to said first constant current source, respectively; and each of said fifth to eights transistors of said second quadritail circuit has a resistor at a corresponding emitter of each of said fifth to eigth transistors, and emitters of said fifth to eighth transistors are connected through said resistors to said second constant current source, respectively.
5. The multiplier as claimed in claim 1, wherein said first to eighth transistors are MOS transistors; gates of said third transistor and said fourth transistor are respectively applied with said voltages which are opposite in phase to each other and equal in absolute value to sum of said first input voltage and said second input voltage, with common-connected gates of said first transistor and said second transistor as a reference; said common-connected gates of said first transistor and said second transistor are applied with a voltage at a middle point of said voltage applied between said gates of said third transistor and said fourth transistor; gates of said seventh transistor and said eighth transistor are respectively applied with said voltages which are opposite in phase to each other and equal in absolute value to difference of said first input voltage and said second input voltage, with common-connected gates of said fifth transistor and said sixth transistor as a reference; and said common-connected gates of said fifth transistor and said sixth transistor are applied with said voltage at a middle point of said voltage applied between said gates of said seventh transistor and said eighth transistor.
6. A multiplier comprising: a first quadritail circuit containing a first pair of first and second transistors whose capacities are the same and whose output ends are connected in common, a second pair of third and fourth transistors whose capacities are the same and whose output ends are connected in common, and a first constant current source for driving said first pair and said second pair; and a second quadritail circuit containing a third pair of fifth and sixth transistors whose capacities are the same and whose output ends are connected in common, a fourth pair of seventh and eighth transistors whose capacities are the same and whose output ends are connected in common, and a second constant current source for driving said third pair and said fourth pair; wherein in said first quadritail circuit, input ends of said first pair are respectively applied with a first input voltage and a second input voltage; input ends of said second pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said first pair; in said second quadritail circuit, one of input ends of said third pair is applied with said first voltage with the same phase as that of said first pair and the other of said input ends is applied with said second voltage with opposite phase to that of said first pair; input ends of said fourth pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said third pair; and said common-connected output ends of said first pair and said common-connected output ends of said fourth pair are connected in common to form one of differential output ends, and said common-connected output ends of said second pair and said common-connected output end of said third pair are connected in common to form the other of said differential output ends.
7. The multiplier as claimed in claim 6, wherein said first to eighth transistors are bipolar transistors; bases of said third transistor and said fourth transistor are connected in common to be connected through a first resistor to a base of said first transistor on the one hand, and to be connected through a second resistor whose resistance value is equal to that of said first resistor to a base of said second transistor, on the other hand; and bases of said seventh transistor and said eighth transistor are connected in common to be connected through a third resistor to a base of said fifth transistor on the one hand, and to be connected through a fourth resistor whose resistance value is equal to that of said third resistor to a base of said sixth transistor, on the other hand.
8. The multiplier as claimed in claim 7, wherein each of said first to fourth transistors of said first quadritail circuit has at least one diode at a corresponding emitter of each of said first to fourth transistors, and emitters of said first to fourth transistor are connected through said diode to said first constant current source, respectively; and each of said fifth to eighth transistors of said second quadritail circuit has at least one diode at a corresponding emitter of each of said fifth to eighth transistors, and emitters of said fifth to eighth transistors are connected through said diode to said second constant current source, respectively.
9. The multiplier as claimed in claim 7, wherein each of said first to fourth transistors of said first quadritail circuit has a resistor at a corresponding emitter of each of aid first to fourth transistors, and emitters of said first to fourth transistors are connected through said resistor to said first constant current source, respectively; and each of said fifth to eighth transistors of said second quadritail circuit has a resistor at a corresponding emitter of each of said fifth to eighth transistors, and emitters of said fifth to eighth transistors are connected through said resistors to said second constant current source, respectively.
10. The multiplier as claimed in claim 6, further comprises a first differential pair for generating said first input voltage and a second differential pair for generating said second input voltage; wherein said first differential pair contains a ninth transistor and tenth transistor, a third constant current source for driving said first differential pair and a first load resistor; said second differential pair contains an eleventh transistor and twelfth transistor, a fourth constant current source for driving said second differential pair and a second load resistor; and said first input voltage is applied between differential input ends of said first differential pair, and two voltages opposite in phase and equal in absolute value to said first input voltage are generated at output ends of said first differential pair, respectively; and said second input voltage is applied between differential input ends of said second differential pair, and two voltages opposite in phase and equal in absolute value to said second input voltage are generated at output ends of said second differential pair, respectively.
11. The multiplier as claimed in claim 6, wherein said first to eighth transistors are MOS transistors; gates of said third transistor and said fourth transistor are respectively applied with said voltages which are opposite in phase to each other and equal in absolute value to sum of said first input voltage and said second input voltage, with common-connected gates of said first transistor and said second transistor as a reference; said common-connected gates of said first transistor and said second transistor are applied with a voltage at a middle point of said voltage applied between said gates of said third transistor and said fourth transistor; gates of said seventh transistor and said eighth transistor are respectively applied with said voltages which are opposite in phase to each other and equal in absolute value to difference of said first input voltage and said second input voltage, with common-connected gates of said fifth transistor and said sixth transistor as a reference; and said common-connected gates of said fifth transistor and said sixth transistor are applied with said voltage at a middle point of said voltage applied between said gates of said seventh transistor and said eighth transistor.
12. The multiplier as claimed in claim 11, wherein gates of said first transistor and said second transistor are connected in common to be connected through a first resistor to a gate of said third transistor on the one hand, and to be connected through a second resistor whose resistance value is equal to that of said first resistor to a gate of said fourth transistor, on the other hand; and gates of said fifth transistor and said sixth transistor are connected in common to be connected through a third resistor to a gate of said seventh transistor on the one hand, and to be connected through a fourth resistor whose resistance value is equal to that of said third resistor to a gate of said eighth transistor, on the other hand.
13. A multiplier comprising: a first quadritail circuit containing a first pair of first and second transistors whose capacities are the same and whose output ends are connected in common, a second pair of third and fourth transistors whose capacities are the same and whose output ends are connected in common, and a first constant current source for driving said first pair and said second pair; a second quadritail circuit containing a third pair of fifth and sixth transistors whose capacities are the same and whose output ends are connected in common, a fourth pair of seventh and eighth transistors whose capacities are the same and whose output ends are connected in common, and a second constant current source for driving said third pair and said fourth pair; a third quadritail circuit containing a fifth pair of ninth and tenth transistors whose capacities are the same and whose output ends are connected in common, a sixth pair of eleventh and twelfth transistors whose capacities are the same and whose output ends are connected in common, and a third constant current source for driving said fifth pair and said sixth pair; wherein in said first quadritail circuit, input ends of said first pair are applied with a first input voltage, and input ends of said second pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said first pair; in said second quadritail circuit, input ends of said third pair are applied with a second input voltage, and input ends of said fourth pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said third pair; in said third quadritail circuit, one of input ends of said fifth pair is applied with said first voltage and the other of said input ends of said fifth pair is applied with said second voltage with opposite phase to that of said first input voltage, and input ends of said sixth pair are connected in common to be applied with a voltage at a middle point of a voltage applied between said input ends of said fifth pair; and said common-connected output ends of said first pair, said common-connected output ends of said third pair and said common-connected output ends of said sixth pair are connected in common to form one of differential output ends, and said common-connected connected output ends of said second pair, said common-connected output ends of said fourth pair and said common-connector output end of said fifth pair are connected in common to form the other of said differential output ends.
14. The multiplier as claimed in claim 13, wherein said first to twelfth transistors are bipolar transistors; bases of said third transistor and said fourth transistor are connected in common to be connected through a first resistor to a base of said first transistor on the one hand, and to be connected through a second resistor whose resistance value is equal to that of said first resistor to a base of said second transistor, on the other hand; bases of said seventh transistor and said eighth transistor are connected in common to be connected through a third resistor to a base of said fifth transistor on the one hand, and to be connected through a fourth resistor whose resistance value is equal to that of said third resistor to a base of said sixth transistor, on the other hand; and bases of said eleventh transistor and said twelfth transistor are connected in common to be connected through a fifth resistor to a base of said ninth transistor on the one hand, and to be connected through a sixth resistor whose resistance value is equal to that of said fifth resistor to a base of said tenth transistor, on the other hand.
15. The multiplier as claimed in claim 14, wherein each of said first to fourth transistors of said first quadritail circuit has at least one diode at a corresponding emitter of each of said first to fourth transistors, and emitters of said first to fourth transistors are connected through said diode to said first constant current source, respectively; each of said fifth to eighth transistors of said second quadritail circuit has at least one diode at a corresponding emitter of each of said fifth to eighth transistors, and emitters of said fifth to eighth transistor are connected through said diode to said second constant current source, respectively; and each of said ninth to twelfth transistors of said third quadritail circuit has at least one diode at a corresponding emitter of each of said ninth to twelfth transistors, and emitters of said ninth to twelfth transistors are connected thorough said diode to said third constant current source, respectively.
16. The multiplier as claimed in claim 14, wherein each of said first to fourth transistors of said first quadritail circuit has a resistor at a corresponding emitter of each of said first to fourth transistors, and emitters of said first to fourth transistors are connected through said resistor to said first constant current source, respectively; each of said fifth to eighth transistors of said second quadritail circuit has a resistor at a corresponding emitter of each of said fifth to eighth transistors, and emitters of said fifth to eighth transistors are connected through said resistors to said second constant current source, respectively; and each of said ninth to twelfth transistors of said third quadritail circuit has a resistor at a corresponding emitter of each of said ninth to twelfth transistors, and emitters of said ninth to twelfth transistor are connected through said resistors to said third constant current source, respectively.
17. The multiplier as claimed in claim 13, wherein said first to twelfth transistors are MOS transistors; gates of said third transistor and said fourth transistor are respectively applied with said first input voltage and said second input voltage, with common-connected gates of said first transistor and said second transistor as a reference; said common-connected gates of said first transistor and said second transistor are applied with a voltage at a middle point of said voltage applied between said gates of said third transistor and said fourth transistor; a gate of said seventh transistor is applied with said first input voltage with the same phase as that of said third transistor, and a gate of said eighth transistor is applied with a difference of said first input voltage and said second input voltage with opposite phase to that of said third transistor, with common-connected gates of said fifth transistor and said sixth transistor as a reference; said common-connected gates of said fifth transistor and said sixth transistor are applied with a voltage at a middle point of said voltage applied between said gates of said fifth transistor and said sixth transistor; a gate of said eleventh transistor is applied with said first input voltage with the same phase as that of said third transistor, and a gate of said twelfth transistor is applied with said second input voltage with opposite phase to that of said third transistor, with common-connected gates of said ninth transistor and said tenth transistor as a reference; and said common-connected gates of said ninth transistor and said tenth transistor are applied with a voltage at a middle point of said voltage applied between said gates of said eleventh transistor and said twelfth transistor.
18. The multiplier as claimed in claim 17, wherein gates of said first transistor and said second transistor are connected in common to be connected through a first resistor to a gate of said third transistor on the one hand, and to be connected through a second resistor whose resistance value is equal to that of said first resistor to a gate of said fourth transistor, on the other hand; gates of said fifth transistor and said sixth transistor are connected in common to be connected through a third resistor to a gate of said seventh transistor on the one hand, and to be connected through a fourth resistor whose resistance value is equal to that of said third resistor to a gate of said eighth transistor, on the other hand; and gates of said ninth transistor and said tenth transistor are connected in common to be connected through a fifth resistor to a gate of said eleventh transistor on the one hand, and to be connected through a sixth resistor whose resistance value is equal to that of said fifth resistor to a gate of said twelfth transistor, on the other hand.
Patent Citations (7)
Non-Patent Literature (1)
- Proceedings of the 1992 IEICE Fall Conference, Sep. 27-30, 1992, Tokyo, Japan.