Background of the Invention
1. Field of the Invention
The present invention relates to circuits providing a current proportional to an input voltage, and more particularly to such a circuit that can be easily fabricated in the form of an integrated circuit.
2. Discussion of the Related Art
FIG. 1 schematically shows a circuit conventionally used for voltage/current conversion. Such circuit includes two NPN-type bipolar transistors, Q1 and Q2, having their collectors connected to a high voltage VCC and their emitters connected to a low voltage VEE through current sources I. Emitters are interconnected through a resistor R1. The collector currents of these transistors are referenced IC1 and IC2. The voltage Ve to be converted into a current is applied between the bases B1 and B2 of transistors Q1 and Q2. Thus, the voltage V(R1) across R1 is:
The current .DELTA.I in resistor R1 is .DELTA.I=V(R1)/R1. The emitter current of Q1 is I+.DELTA.I, and the emitter current of Q2 is I-.DELTA.I. Assuming that the base-emitter voltage drops Vbe1 and Vbe2 of transistors Q1 and Q2 are equal, and that the difference of the emitter currents is equal to the difference of the collector currents, then IC1-IC2=2.DELTA.I=2Ve/RI.
A conventional circuit 10, for example of the current mirror type, provides the difference between currents IC1 and IC2 and provides at the output a current 2.DELTA.I that is proportional to Ve.
In the above discussion, two simplified assumptions have been considered. The first assumption is that Vbe1=Vbe2; the second assumption is that the difference in the emitter currents is equal to the difference of the collector currents. In fact, the collector currents of transistors Q1 and Q2 are IC1=.alpha.(I+.DELTA.I) and IC2=.alpha.(I-.DELTA.I), where .alpha. is the common-base current gain of transistors Q1 and Q2 (it is assumed that the two transistors have the same gain). .alpha. is expressed as a function of the common-emitter current gain, .beta., of transistors Q1 and Q2 by the relation .alpha.=1/(1+1/.beta.). Thus, current .DELTA.I, instead of being simply equal to Ve/R1 is in fact expressed by the relation:
Thus, a first error is due to the value of Vbe2-Vbe1 that is non-zero and varies with the current and temperature. The second error is due to the fact that .alpha. is not equal to 1, and the variation of .alpha. can be non-negligible when .beta. is relatively low. For example, if .beta.=35, .alpha. is equal to 0.97; so, the proportion error is approximately 3%.
A conventional manner to correct the first error is illustrated in FIG. 2. A negative feedback is imposed between the emitter and the base of each transistor Q1 and Q2 through differential amplifiers A1 and A2 whose outputs are applied to the bases of transistors Q1 and Q2, respectively, and whose inverting inputs are connected to the emitters of transistors Q1 and Q2, respectively. The input signal is applied between the non-inverting inputs E1 and E2 of amplifiers A1 and A2. Thus, the error associated with the non-zero value of Vbe2-Vbe1 is attenuated by a factor AV, where AV is the voltage gain of each amplifier A. This gain can be very high, for example higher than 100, and the slight error in the difference of the base-emitter voltages thus becomes an error of the second order, substantially lower than 1:1000.
A conventional method to correct the second error is to substitute a Darlington-type circuit for each transistor Q1 and Q2. As is shown in FIG. 3, each transistor Q1 and Q2 is associated with a respective Darlington-connected transistor Q'1 and Q'2. Considering that transistors Q1, Q2, Q'1 and Q'2 have the same common-emitter current gain, .beta., the common-base current gains .alpha. become 1[1+1/.beta.(.beta.+1)]. Again, an error of the first order is changed into an error of the second order, that becomes negligible.
Thus, the circuit of FIG. 3 that combines the correction means of the first and second type of error is satisfactory and provides currents IC1 and IC2 whose difference is proportional (the proportion ratio being associated with the value of resistor R1) to the difference in voltage between terminals E1 and E2.
However, this circuit has a drawback inherent in the presence of a Darlington-type circuit. Indeed, when considering a single transistor such as transistor Q1 or Q2, its collector/emitter voltage drop at the conducting state, Vsat, is approximately 0.2 volt. Whereas, in the case of a Darlington circuit, this voltage drop is increased by the mean value of a base-emitter voltage drop, that is, the total voltage drop approaches a value of approximately 1 volt. This phenomenon is aggravated at low temperatures where Vbe increases. This relatively high voltage drop across the transistors is a drawback especially due to the fact that, as illustrated in FIG. 1, there are additional transistor stages between the high supply voltage and the low supply voltage (between VCC and VEE). This requires that the difference VCC-VEE must be higher in the case of the circuit of FIG. 3 than in the case of the circuit of FIG. 1 and does not allow the use of the circuit of FIG. 3 when this voltage difference (supply voltage) is low.
Summary of the Invention
An object of the invention is to provide a voltage/current converter in which the voltage drop across the elements providing the current is as low as possible.
To achieve this object, the invention provides a circuit for converting a voltage into a current difference, including a first differential pair including a first and second NPN transistor whose emitters are connected to a low supply terminal through a current source and whose collectors are connected to a high supply terminal, a second differential pair including a third and fourth NPN transistor whose emitters are connected to a low supply terminal through a current source and whose collectors are connected to a high supply terminal, a first resistor disposed between the emitters of the transistors of the first pair, a second resistor disposed between the emitters of the transistors of the second pair, third and fourth resistors disposed between the bases of the first and third transistors and of the second and fourth transistors, respectively, and a voltage negative feedback means disposed across the second resistor and the bases of the transistors of the first pair in order to fix the voltage across the second resistor to a predetermined input voltage.
According to an embodiment of the invention, the negative feedback means includes operational amplifiers, each having a first input connected to a terminal of the second resistor, a second input forming an input terminal, and an output applied to the base of a transistor of the first pair.
According to an embodiment of the invention, each operational amplifier is formed by a fifth NPN transistor and a sixth PNP transistor, the base of the fifth transistor being connected to a terminal of the second resistor, the emitter of the fifth transistor being connected to the input terminal, the collector of the fifth transistor being connected to the high supply terminal through a current source, the base of the sixth transistor being connected to the collector of the fifth transistor, the emitter of the sixth transistor being connected to the high supply terminal through a current source and to the base of a transistor of the first differential pair, and the collector of the sixth transistor being connected to the low supply terminal.
According to an embodiment of the invention, an operational amplifier is formed by an NPN transistor whose collector is connected to the high supply terminal through a current source and to the base of a transistor of the first pair, having its emitter connected to a second input terminal and its base connected both to a first input terminal and a terminal of the second resistor.
According to an embodiment of the invention, the third and fourth resistors have a same value, equal to half the value of the second resistor.
The foregoing and other objects, features, aspects and advantages of the invention will become apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Brief Description of Drawings
FIGS. 1-3, above described, are useful for illustrating the state of the art;
FIG. 4 schematically shows a first embodiment of the circuit according to the invention operable for converting a voltage into a current;
FIG. 5 represents a variant of the circuit of FIG. 4; and
FIGS. 6 and 7 represent in more detail implementations of negative feedback amplifiers used in FIGS. 4 and 5, respectively.
Detailed Description
FIG. 4 schematically shows an embodiment of a circuit according to the invention. The circuit includes a first differential pair including transistors Q1 and Q2 and a second differential pair including transistors Q3 and Q4. In the represented embodiment, all the transistors are of the NPN-type. The emitters of transistors Q1-Q4 are connected to the low supply terminal VEE through current sources I. The collectors of transistors Q1-Q4 are connected to a high supply terminal VCC, directly or indirectly but in both cases through paths having the same impedance for each transistor of a differential pair. The emitters of transistors Q1 and Q2 are connected through a resistor R1 and the emitters of transistors Q3 and Q4 are connected through a resistor R2. The outputs of the operational amplifiers A1 and A2 are connected to the bases of transistors Q1 and Q2, respectively. The inverting inputs of amplifiers A1 and A2 are connected to the emitters of transistors Q3 and Q4, respectively, and the non-inverting inputs E1 and E2 of amplifiers A1 and A2 correspond to input terminals between which is applied the voltage that is to be converted into a current, the converted current being proportional to the difference between the collector currents IC1 and IC2 of transistors Q1 and Q2. The bases of transistors Q1 and Q3 and the bases of transistors Q2 and Q4 are respectively connected through connecting resistors Rb1 and Rb2 having an equal value, Rb.
For the sake of simplification of the description, references 11 and 12 designate the base terminals of transistors Q1 and Q2, 13 and 14 designate the emitter terminals of transistors Q3 and Q4, and 15 and 16 designate the collector terminals of transistors Q1 and Q2. Terminals 11-16 are the input/output terminals of a block surrounded by dashed lines and referenced 20 in FIG. 4.
In the case of FIGS. 2 and 3, because of the presence of the high gain operational amplifiers A1 and A2, voltage Ve appears across resistor R1 between inputs E1 and E2. Similarly, in the example of FIG. 4, voltage Ve appears across resistor R2. Current IR2 in resistor R2 is equal to Ve/R2 virtually without error or with a negligible error of the second order. Currents I+IR2 and I-IR2 appear again in the emitters of transistors Q3 and Q4. The differential voltage between the bases of transistors Q1 and Q2 is also differentially applied to the bases of transistors Q3 and Q4, with a resulting voltage difference across resistor R1 (neglecting the errors in differences of Vbe that are, in that case, of the second order):
or
The difference in the collector current of transistors Q1 and Q2 is equal to twice the current value in resistor R1 multiplied by the gain ratio .alpha. (.apprxeq.1-1/.beta.). Thus, by selecting Rb=R2/2, one obtains:
that is,
that is, the 1/.beta..sup.2 term being negligible, this current difference becomes substantially equal to 2Ve/R1 and, as desired, is proportional to voltage Ve. This result is obtained whereas the voltage across transistors Q1 and Q2 remains the voltage drop at the conduction state of a bipolar transistor that is, as indicated above, approximately 0.2 volt.
Like in conventional circuits, the proportion ratio between the voltage and the current depends only on the value of resistor R1. The values of resistors R2, Rb1 and Rb2 intervene only by their ratio that can be extremely accurate in an integrated circuit device.
Of course, those skilled in the art can devise various modifications to the circuit according to the invention.
FIG. 5 shows a variant in which the connection mode of the operational amplifier A1 and A2 is modified. FIG. 5 shows again the block 20 of FIG. 4 with its terminals 11-16. In FIG. 5, the inverting inputs of the operational amplifiers A1 and A2 are connected to terminals 13 and 14 through respective resistors R3 and R4, and the non-inverting inputs are interconnected. The input terminals E1 and E2 then correspond to the inverting input of amplifier A1 and to the non-inverting inputs of amplifiers A1 and A2. In this case, a voltage can be applied between inputs E1 and E2 with interposition of a series resistor on terminal E1 in a manner known by those skilled in the art.
FIG. 6 shows an exemplary embodiment of operational amplifiers used for the circuit of FIG. 4. Amplifier A1 only will be described in detail, since amplifier A2 is identical. Amplifier A1 is formed by an NPN-type transistor Q5 and a PNP-type transistor Q6. The collector of transistor Q5 is connected to the high supply terminal through a current source 15. The emitter of transistor Q6 is connected to terminal 11 and to the high supply terminal through a current source 16. The base of transistor Q6 is connected to the collector of transistor Q5. The collector of transistor Q6 is connected to the low supply terminal VEE. The base of transistor Q5 is connected to terminal 13. The emitter of transistor Q5 corresponds to the input terminal E1.
FIG. 7 shows an exemplary embodiment of the operational amplifiers A1 and A2 used in a circuit as the one shown in FIG. 5. The operational amplifiers A1 and A2 are formed by NPN-type transistors Q7 and Q8, respectively. The collectors are respectively connected to terminals 11 and 12 and to the high supply terminal through respective current sources 17 and 18. The emitters are interconnected and form the input terminal E2. The bases of transistors Q7 and Q8 are respectively connected to terminals 13 and 14 through resistors R7 and R8. As indicated above, the input terminal E1 is preferably connected to the base of transistor Q7 through a resistor R9.
Having thus described one particular embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.