Comparator With Application in Data Communication

1. Field of the Invention

This invention relates to data communications comparators and, in particular, to integrated circuit data communications receivers of the comparator type.

2. Description of Related Art

Integrated circuit receivers enjoy widespread use in data communications. For example, in an Ethernet system, data signals are differential signals transmitted over a twisted pair. The data signals are generally of a sine wave character. The data signals are shaped in a receiver, which typically is a type of comparator.

An example of a comparator for receiving Ethernet signals is shown in FIG. 1. Input signals enter the comparator 10 at nodes 11 and 12. The input signals are amplified and buffered by the network consisting of transistors 51, 52, 55, 56, 61, 62, 63, and resistors 53, 54. The amplified and buffered signals at nodes 15 and 16 are then amplified by inverting amplifiers 81, 83 and 82 84, respectively, to yield the output signals from the comparator 10 at nodes 19 and 20.

One problem encountered with the use of comparators to shape transmitted signals is that an unpredictable bias offset (which is the deviation of bias levels from their ideal values) can arise in the comparator so that the relative transitions between logic levels at the comparator output are distorted. Types of distortion typically encountered include, for example, phase distortion and duty cycle distortion. In phase distortion, the rising and falling edge of the comparator output waveform jitters or appears faster or slower than would be expected. In duty cycle distortion, the duty cycle of the comparator output differs from the duty cycle of the transmitted data signal at the comparator input. The bias offset results from, for instance, fluctuation in circuit parameters due to process and temperature changes and power supply noise.

In the comparator 10 shown in FIG. 1, bias generation circuitry consisting of differential amplifier 70, inverting amplifier 74, transistors 71, 72, 75 and resistor 73 is provided to overcome the problem of bias offset. The bias generation circuitry generates a current through the transistor 75 which, in turn, is mirrored in the transistors 61, 62 and 63. The components in the bias generation circuitry are matched With other components in the comparator 10 so that an appropriate amount of current will flow through the transistors 61, 62, 63 to keep the inverting amplifiers 81 and 82 biased in their high gain region when the inputs at nodes 11 and 12 are equal.

This circuit is inadequate for some applications because mismatch of currents in the transistors 75, 61, 62 and 63, or mismatch of device values between transistors 71, 55, 56 or resistors 73, 53, 54 will prevent the inverting amplifiers 81 and 82 from being properly biased. This circuit is also inadequate because it does not act to minimize the detrimental effects arising from the presence of noise in the power supply.

It is desirable, then, to provide a comparator in which fluctuations in the bias offset and the effects of power supply noise are minimized.

In accordance with the invention, a comparator is provided that may be used in data communications. In particular, the comparator may be advantageously used with an Ethernet Twisted-Pair line.

The comparator accepts as input a differential voltage from the transmission lines. The input differential voltage is amplified and buffered in a low gain first stage. The comparator further uses feedback circuitry to ensure that switching of the comparator output voltage between logic highs and lows accurately tracks the switching of the comparator input differential voltage between positive and negative. The feedback circuitry mitigates bias offset within the comparator that may result from, for instance, temperature driven device parameter variations.

In one embodiment, the feedback circuitry comprises an operational amplifier and a resistive-capacitive network. The resistive-capacitive network averages the output voltages of the low gain first stage to obtain a common-mode voltage. The common-mode voltage and a reference voltage equal to the logic threshold of an output amplifier constitute the two inputs to the operational amplifier. If the common-mode voltage is different from the reference voltage, then the output of the operational amplifier controls current in the low gain first stage so as to change the output DC level of the low gain first stage (i.e., input DC level of the output amplifier). The output DC levels of the low gain first stage are changed until the common-mode voltage (i.e., average of the two first stage output voltages) equals the reference voltage (i.e., logic threshold of the output amplifier).

The feedback circuitry thus ensures that as the comparator input differential voltage approaches zero (i.e., when the comparator outputs should switch from a logic high voltage to a logic low voltage or vice versa), the input of the output amplifier is situated in the middle of the high gain region of the output amplifier. In other words, the feedback circuitry ensures that the output amplifier is ready to quickly trigger switching of the comparator output when the comparator input differential voltage crosses zero volts.

Additionally, the feedback circuitry compensates for the effects of noise in the power supply. When noise appears in the comparator at the output voltages of the first stage, the feedback circuitry controls currents in the first stage so that the output voltages of the first stage are changed until the noise is eliminated.

In another embodiment, the resistive-capacitive network is implemented in silicon using a diffused region for the resistance and a polysilicon plate for the capacitance. This implementation provides an area efficient way of generating the common-mode voltage in an integrated circuit.

FIG. 1 is a circuit schematic diagram of a prior art comparator.

FIG. 2 is a circuit schematic diagram of a comparator.

FIG. 3A is a circuit schematic diagram of an inverting amplifier.

FIG. 3B is a graph of the input/output characteristic of the inverting amplifier of FIG. 3A.

FIG. 4 is a circuit schematic diagram of an operational amplifier for use with the comparator of FIG. 2.

FIG. 5A is a cross-sectional view of a stage in the formation of an integrated circuit implementation of a distributed resistive-capacitive structure used in the comparator of FIG. 2.

FIG. 5B is a cross-sectional view of a stage after the stage shown in FIG. 5A of an integrated circuit implementation of a distributed resistive-capacitive structure used in the comparator of FIG. 2.

FIG. 5C is a cross-sectional view of an integrated circuit implementation of a distributed resistive-capacitive structure used in the comparator of FIG. 2.

FIG. 5D is a cross-sectional view of an integrated circuit implementation of a distributed resistive-capacitive structure used in the comparator of FIG. 2 along a section perpendicular to the cross-sectional view shown in FIG. 5C.

FIG. 6 is a top view of an integrated circuit implementation of a distributed resistive-capacitive structure used in the comparator of FIG. 2, with some layers omitted for clarity.

FIG. 2 is a circuit schematic of comparator 100 according to an embodiment of the invention. Illustratively, the comparator 100 is electrically connected to a twisted pair data communications line (not shown). The voltage in the two lines of the twisted pair is applied to the comparator 100 at, respectively, node 101 and node 102. In a typical application, the differential voltage across node 101 and node 102 will be approximately sinusoidal with an amplitude range of from several hundred millivolts to several volts. The common-mode voltage of node 101 and node 102 may range from 2 volts to positive supply V.sub.DD.

The two input voltages at nodes 101, 102 are first conditioned by a low gain first stage amplifier. In the first part of the low gain first stage amplifier, the two input voltages at nodes 101, 102 are amplified by a differential amplifier comprising transistor 151, transistor 152, resistors 153 and 154, and current sourcing transistor 162. The amplified voltages at nodes 103, 104 are then buffered by source followers comprising, respectively, transistor 155 and current sourcing transistor 161, and transistor 156 and current sourcing transistor 163. The voltages at nodes 105 and 106 are the buffered output of the low gain first stage.

The voltage at node 105 is amplified by inverting amplifiers 181 and 183, and output at node 109. In a similar manner, the voltage at node 106 is amplified by inverting amplifiers 182 and 184, and output at node 110. The voltages at nodes 109, 110 are the digital output voltages of the comparator 100.

FIG. 3A shows the structure of a typical inverting amplifier 200, the input/output characteristic 221 of which is shown in FIG. 3B. When the input voltage at node 211 to the inverting amplifier 200 is zero, the output voltage at node 212 is approximately equal to V.sub.DD. As the input voltage at node 211 increases, the output voltage at node 212 begins to slowly decrease. This low gain region 215 exists while P-channel transistor 202 is in the triode region and N-channel transistor 201 is in the saturation region. As the input voltage at node 211 reaches voltage 213, P-channel transistor 202 also saturates, and the output voltage at node 212 begins to fall sharply with small increases in the input voltage at node 211. This high gain region 216 exists while both transistors 201 and 202 are in saturation. As the input voltage at node 211 reaches voltage 214, N-channel transistor 201 goes into the triode region while P-channel transistor 202 remains in saturation, and the inverting amplifier 200 enters the second low gain region 217. In this region, the output voltage at node 212 drops slowly to zero volts as the input voltage at node 211 increases to V.sub.DD.

Referring again to FIG. 2, the inverting amplifiers 181, 182 are identical, and, by way of the bias voltage at node 111, the average of the voltages at node 105 and node 106 is centered about the high gain regions of the inverting amplifiers 181, 182. However, a bias offset arises in the comparator 100 due to, for example, temperature effects. The presence of bias offset means that the average value of the voltages at node 105 and node 106 may be outside the high gain region of the inverting amplifiers 181 and 182. Thus, the duty cycle of the comparator output waveform may not faithfully replicate the duty cycle of the waveform at the comparator input.

The comparator 100 minimizes the problem of bias offset through the implementation of feedback control circuitry. The voltages at node 105 and node 106 are applied to a resistive-captive network, which in an integrated circuit implementation is preferably distributed resistive-capacitive structures 171 and 172. The distributed resistive-capacitive structures 171 and 172 act as a voltage averager. The voltage at node 112 represents the average or common-mode voltage of the voltages at node 105 and node 106. The voltage at node 112 should ideally be equal to the voltage at the midpoint of the high gain region (logic threshold) of inverting amplifiers 181 and 182. However, as a bias offset voltage develops, the voltage at node 112 begins to deviate from the ideal value.

The voltage at node 112 is applied to the plus input 173A of an operational amplifier 173. The minus input 173B of the operational amplifier 173 is a reference voltage at node 113. The reference voltage at node 113 is obtained from inverting amplifier 174. The input and output of inverting amplifier 174 are shorted together so that the voltage at node 113 must equal the voltage at node 114 as shown by line 220 in FIG. 3B. Since the inverting amplifier 174 must also conform to the input/output characteristic 221, the inverting amplifier 174 must operate at point 222 (i.e., the middle of the high gain region 216). Thus, because inverting amplifier 174 is identical to inverting amplifiers 181 and 182, the reference voltage at node 113 is equal to the logic threshold of inverting amplifiers 181 and 182. The operational amplifier 173 compares the voltages at node 112 and node 113. Based upon this comparison, the voltage at node 111 is output at operational amplifier output 173C. The voltage at node 111 controls the transistors 161, 162, 163 which, in turn, control the current flow in the low gain first stage.

If the voltage at node 112 begins to drop below the voltage at node 113, the voltage at node 111 also begins to fall. Transistors 161, 162 and 163 respond by driving less current through the low gain first stage. The voltages at node 105 and node 106 rise. Consequently the voltage at node 112 (the average of the voltages at node 105 and node 106) rises back to its proper value. Conversely, if the voltage at node 112 begins to rise above the voltage at node 113, then the voltage at node 111 also begins to rise. Transistors 161, 162, and 163 respond by driving more current through the low gain first stage. The voltages at node 105 and node 106 drop, and the voltage at node 112 falls back to its proper value. Thus, the operational amplifier 173 and associated feedback circuitry provide negative feedback to keep the voltage at node 112 substantially equal to the logic threshold voltages of inverting amplifiers 181 and 182.

FIG. 4 shows a circuit schematic of the operational amplifier 173. Transistor 325 establishes a bias voltage at node 344. The bias voltage at node 344 controls transistor 320 to supply a constant current 340 through transistor 320. The current 340 is split between two branches: current 341 flows through branch 331 comprising transistors 301, 303 and current 342 flows through branch 332 comprising transistors 302, 304. The voltage inputs 173A and 173B to the operational amplifier 173 control how much current flows through each of the branches 331 and 332 since the current 340 is constant. Current 351, being mirrored by transistors 303 and 317, is equal to current 341. Current 352, being mirrored by transistors 304 and 318, is equal to current 342. Currents 351 and 352 go through cascode transistors 315 and 316, respectively. Transistors 311, 312, 313 and 314 serve as a differential to single-ended converter. The amplified version of the difference between input voltages 173A and 173B is available at node 345. The output voltage 173C is the level-shifted version of the voltage at node 345, and is more suitable than the voltage at node 345 for controlling the output voltage 173C (and thus, the voltage at node 111) because the output voltage 173C can swing to a lower voltage when transistors 161, 162 and 163 need to be shut off.

FIG. 5C is a cross-sectional view of a representative portion of the distributed resistive-capacitive structure 171 and 172. FIGS. 5A or 5B are intermediate stages in the formation of the structure of FIG. 5C.

Referring to FIG. 5A, a first photolithographic operation defines the N- region 402 of length 420 in the P-type substrate 401. The N- region 402 may be doped by, for example, ion implantation followed by drive-in. After the N- region 402 is driven in, a thin layer of SiO.sub.2 (not shown) is grown over the entire wafer. On top of the layer of SiO.sub.2, a layer of Si.sub.3 N.sub.4 (not shown) is deposited. A device-well mask is next used to etch the Si.sub.3 N.sub.4 and SiO.sub.2 layers outside the device-well areas. A field oxide layer 404 is grown in regions not covered by the Si.sub.3 N.sub.4 /SiO.sub.2 mask. The use of Si.sub.3 N.sub.4 as a mask for oxidation results in a semi-recessed device well structure. The Si.sub.3 N.sub.4 is etched, exposing the thin SiO.sub.2 layer. The exposed thin SiO.sub.2 layer is removed and a new SiO.sub.2 layer 409 is grown over the N- region 402. The SiO.sub.2 layer 409 is the dielectric layer for the capacitors in this resistive-capacitive structure.

A polycrystalline silicon layer is deposited and a polysilicon mask is used to define the polysilicon plate 406 of length 429 for the resistive-capacitive structure, resulting in the structure of FIG. 5A. An illustrative concentration for the substrate 401 is 1.times.10.sup.15 atoms/cm.sup.3 and for the region 402 is 1.times.10.sup.16 atoms/cm.sup.3.

Referring to FIG. 5B, an exclusion mask is used to exclude regions (not shown) which must not receive the N+ implant. Regions which are outside the N+ exclusion area and which are not masked by thick oxide or polysilicon layers receive N+ implant. The N+ implant is driven in to form N+ regions 403A and 403B. The N+ regions 403A and 403B serve as contacts to the N- region 402 in this resistive-capacitive structure. The length of the capacitor defined by N- region 402 and polysilicon plate 406 is limited to the length 429 of the polysilicon plate 406 rather than the length 420 of the N- region 402. An illustrative concentration for the regions 403A and 403B is 9.times.10.sup.18 atoms/cm.sup.3.

A thick layer 407 of SiO.sub.2 is deposited. FIG. 5B results after a contact mask is used to etch out the contact regions 408A and 408B.

In FIG. 5C, a layer of aluminum is evaporated over the entire surface. A metal mask is then used to define the metallization patterns 405A and 405B.

FIG. 6 is a top view of an integrated circuit implementation of the distributed resistive-capacitive structures 171 and 172. Each of the resistive-capacitive structures 171 and 172 is formed in a series of three strips; however, it is to be understood that one, two, four or more strips could also be used, depending on the resistance value desired and on layout considerations. The total length L of the lightly doped region 402 of each distributed resistive-capacitive structure 171 or 172 is equal to two times the length 429 plus the length 529. The width W of the lightly doped region 402 is equal to the width 421 of each of the strips.

The strips of a given resistive-capacitive structure 171 or 172 are electrically connected between metal contacts, e.g., metal contacts 405B, 405C, by metal strips 505. The polysilicon plates 406 of each strip are connected by polysilicon connecting regions 506.

The polysilicon plates 406 and the interior ends of the resistive lightly doped regions 402 of each distributed resistive-capacitive structure 171 and 172 are electrically connected at node 112 by metal strip 507 and metal contacts 508A, 508B, 508C. Metal strip 510 electrically connects the distributed resistive-capacitive structure 172 to node 106. Metal strip 511 electrically connects the distributive-capacitive structure 171 to node 105. Metal strip 512 electrically connects node 112 to the positive input 173A of operational amplifier 173.

For each distributed resistive-capacitive structure 171 or 172, suitable values of total resistance range from 50K to 200K. Suitable values of total capacitance range from 1.5 pF to 5 pF. If the sheet resistance (in ohms/.quadrature.) is RHO and the gate oxide capacitance (in F/m.sup.2) is CAP, then the total resistance, R.sub.tot, and total capacitance, C.sub.tot, of each distributed resistive-capacitive structure 171 or 172 is given by the following equations:

Illustratively, W is 5 micrometers and L is 384.5 micrometers. These dimensions yield nominal values of R.sub.tot =100K and C.sub.tot =2.65 pF.

Each distributed resistive-capacitive structure 171 or 172 has a parasitic junction capacitance between the lightly doped N-type region 402 and the P-type substrate 401. Illustratively, the value of this capacitance is approximately 0.9 pF. This capacitance contributes to the capacitance in the distributed resistive-capacitance structure 171 and 172, as shown in FIG. 2 by the elements 175B and 176B, and should be considered in the design of the feedback circuitry.

Another pair of capacitances which should be considered in the design of the feedback circuitry are the capacitances 175A and 176A, shown in FIG. 2, which are formed between the polysilicon plate 406 and substrate 401 shown in FIG. 5D. These capacitances are minimized by using the minimum polysilicon plate 406 overlap of lightly doped region 402 allowed by the design rules. For the same reason, polysilicon connecting region 506, which is an extension of polysilicon plate 406, preferably is kept to the minimum width allowed by the design rules. The width and length (in micrometers) of the transistors in FIGS. 2 and 4 are set forth below in Table I.

Resistors 153 and 154 have a resistance of 2K and capacitor 350 has a capacitance of 5 pF.

Above, embodiments of the invention are described. The descriptions are intended to be illustrative, not limitative. Thus, modifications may be made to the invention as described without departing from the scope of the claims set out below.