Resettable Clamp-Sample-and-Hold Signal Processing Circuit for Imaging Sensors

1. Field of the Invention

The present invention relates to signal processors for imaging sensors of the type that employ clamp-sample-and-hold (C-S/H) circuits and, more particularly, a signal processor that employs a resettable C-S/H (RC-S/H) circuit that eliminates sequential pixel crosstalk while improving noise immunity.

2. Description of the Prior Art

A charge-coupled device (CCD), among other imaging sensors, may be used to generate video output signals corresponding to a particular sensed image. These video output signals must be recovered in a manner that preserves the characteristics of the image sensed by the CCD array. Heretofore, signal processing circuits have been used to recover the video signals generated by imaging sensors. Such signal processing circuits include the standard C-S/H correlated double sampling (CDS) processor, or more complex CDS processors such as the gated integrator. Problems associated with recovering video imaging signals include sequential pixel crosstalk and video output noise.

The C-S/H CDS design, which is the basis for the present invention, is a relatively simple circuit that utilizes a resistive and capacitive (RC) combination to filter video output noise from the true video signal. However, the bandwidth selected for the RC filter reflects a compromise between noise rejection and sequential pixel crosstalk. Hence, sub-optimal noise rejection performance is often the price paid for an acceptably low level of sequential pixel crosstalk.

The gated integrator and other more intricate types of CDS processors are inherently free of crosstalk between sequential video imaging pixels. However, the circuitry required to implement these designs is considerably more complex than that of the basic C-S/H processor. Therefore, these types of CDS processors are often deemed unacceptable for certain applications.

The present invention contemplates a signal processing circuit for recovering video imaging signals from a CCD or similar imaging sensor. This invention provides a unique modification to the standard C-S/H CDS processor by making the processing circuit resettable, thus a RC-S/H CDS signal processor.

The enhanced features of the RC-S/H signal processor are derived from a reset switch which has been added to the RC filter stage of the circuit. The reset switch functions to remove any residual charge from the RC filter stage that may have accumulated from the previously recovered pixel voltage level. This allows the RC filter to be optimally designed to suppress video output noise. Therefore, there is no longer a trade-off required between input noise rejection and sequential pixel crosstalk. Furthermore, this design is only slightly more complex than the basic C-S/H design.

A primary objective of the present invention is to provide a means for recovering accurate video voltage levels from a CCD sensor or other type of imaging sensor.

Another objective of the present invention is to provide a means of recovering accurate video imaging signals.

Another objective of the present invention is to provide a circuit that eliminates sequential pixel crosstalk while recovering video imaging signals.

Another objective of the present invention is to provide a circuit that provides optimal input noise rejection while recovering video imaging signals.

FIG. 1 is a circuit diagram of the RC-S/H CDS signal processing circuit.

FIG. 2 is a timing diagram illustrating an entire pixel read sequence of a RC-S/H CDS signal processing circuit.

A circuit diagram of a RC-S/H CDS signal processor for recovering video imaging signals is shown in FIG. 1. The present invention is a modification of the widely-used C-S/H CDS signal processor, with the modification being the addition of a reset switch 18 in the RC filter stage 17.

An input 10 to the RC-S/H CDS signal processor accepts a video imaging signal from a CCD or other type of imaging sensor represented by a buffer 11. The video signal is buffered and scaled by a preamplifier 12 and then provided to the RC filter stage 17. The RC filter stage 17 is comprised of a resistor 14 and a capacitor 16 that act to suppress any high-frequency noise which may propagate through the preamplifier The reset switch 18, when closed, removes from the capacitor 16 any residual charge that may be remaining from the previously recovered pixel. It is this action that limits the memory span of the RC-S/H CDS signal processor to a single pixel interval, thereby eliminating sequential pixel crosstalk.

In the absence of a reset switch, any residual charge which may have accumulated on the capacitor 16 would be slowly dissipated through the resistor 14 and the output impedance of the preamplifier 12, or through the input impedance of a filter buffer 20. As a result of this gradual charge dissipation the design of the RC filter must reflect a compromise between sequential pixel crosstalk and noise rejection. A wide filter bandwidth will yield adequate immunity to sequential pixel crosstalk but poor noise rejection, while a narrow filter bandwidth will provide good noise rejection but excessive sequential pixel crosstalk. The addition of the reset switch 18 allows the RC filter 17 to be designed solely for the purpose of optimal noise rejection rather than as a compromise between noise rejection and sequential pixel crosstalk suppression.

The remainder of the RC-S/H circuit functions as a standard C-S/H CDS signal processor. The filter buffer 20 allows the filtered video signal to propagate through to a clamp capacitor 22, which performs two functions, depending on the position of a clamp switch 24. When the clamp switch 24 is closed, the clamp capacitor 22 stores a direct current (DC) charge associated with a constant READ RESET portion of the video voltage signal that has propagated through the filter buffer 20. When the clamp switch 24 is open, the clamp capacitor 22 allows an active charge associated with a changing portion of the video voltage signal to propagate through to a clamp buffer 26. The output of the clamp buffer 26 represents this changing video signal less the stored DC voltage. A sample/hold switch 28, when closed, allows the output voltage of the clamp buffer 26 to be stored on a sample/hold capacitor 30. When the sample/hold switch 28 is open, the video voltage stored on the sample/hold capacitor 30 will be propagated through a sample/hold buffer 32 to the next signal processing stage. It should be noted that control of the reset switch 18, clamp switch 24, and sample/hold switch 28 is, in the preferred embodiment, derived directly from the time base generator of the imaging sensor.

Referring to FIG. 2, the timing of the RC-S/H CDS signal processing circuit during an entire pixel read sequence is illustrated. During the interval from time T.sub.O to T.sub.1, the imaging sensor is being reset and the video signal at the input 10 to the signal processor is unsettled. The voltage level at this time is referred to as the RESET FEED-THRU voltage.

Also during the interval from time T.sub.O to T.sub.1, the reset switch 18 is closed, thereby removing any residual charge from the capacitor 16 and prohibiting the RESET FEED-THRU voltage from propagating to the input of the filter buffer 20.

At time T.sub.1, the input 10 from the imaging sensor has settled to the READ RESET voltage level. The READ RESET voltage level is used as a reference from which the actual video imaging output voltage level is determined. However, since the READ RESET voltage is not a constant, it may be looked upon as a floating reference. Also at time T.sub.1, the reset switch 18 is opened permitting the READ RESET voltage to propagate through the filter buffer 20, and the clamp switch 24 is closed, storing the READ RESET voltage on the clamp capacitor 22.

At time T.sub.2, the clamp switch 24 is opened, and the imaging sensor enters the VIDEO interval of the pixel period. During this interval, the output of the clamp buffer 26 will represent the changing video signal less the stored READ RESET reference voltage. This implicit subtraction totally rejects the imaging sensor reset noise which is correlated in both the READ RESET and VIDEO voltage levels.

At time T.sub.3, the sample/hold switch 28 is closed, allowing the VIDEO voltage level to be stored on the sample/hold capacitor 30. At time T.sub.4, after the VIDEO voltage has settled and been stored on the sample/hold capacitor 30, the sample/hold switch 28 is opened. The sample/hold buffer 32 will then provide this video imaging voltage to the next processing stage.