Method and Apparatus for Improving the Output Response of an Electronic Imaging System

The invention relates in general to electronic imaging systems The invention relates in particular to a method and apparatus for improving the output response including the dynamic range, linearity and signal-to-noise ratio, of an electronic imaging system.

Solid state electronic imaging devices, such as charge coupled devices (CCD's) and the like, have been utilized in a wide variety of electronic imaging systems to generate electronic representations of an imaged scene. One common electronic image device structure, for example, is the full-frame CCD image sensor that typically includes a vertical CCD shift register containing a two dimensional array of photocapacitive sensing elements (pixels), which also serve as a photocharge transport mechanisms, a horizontal CCD output shift register formed on a silicon substrate, and an output amplifier coupled to the horizontal CCD shift register. An image is acquired by the image sensor when incident light, in the form of photons, falls on the array of pixels in the vertical CCD shift register and generates a proportional photocharge within the silicon substrate at each pixel site The photocharge is collected locally at each pixel site of the array in potential wells formed within the silicon substrate by the application of voltage or clock signals to clock lines of the vertical CCD shift register. Columns of collected photocharge are transported or shifted in parallel from the vertical CCD shift register row by row into the horizontal CCD shift register. Voltage signals are then applied to clock lines of the horizontal CCD shift register to transport or shift the rows of charge pixel by pixel from the horizontal CCD shift register to the output amplifier. The signal from the output amplifier is generally clamped and sampled at an appropriate pixel rate to generate an effective output signal that is subsequently supplied to signal processing circuitry.

Conventional electronic imaging systems, however, have been found to exhibit a non-linearity in their output response. It is an object of the invention to eliminate, or substantially reduce, this non-linearity to improve the overall output response of such systems.

The invention provides a method and apparatus for improving the output response of electronic imaging systems. Specifically, horizontal clocking signals used to transfer charge from a horizontal shift register to an output amplifier of an electronic imaging system are synchronized with a clamp clock signal and a sample clock signal, respectively supplied to a clamp circuit and a sampling circuit, to prevent cross talk caused by the horizontal clocking signals during the sampling operation. The horizontal clocking signals are generated so that they are in the same state when the clamp clock signal and the sample clock signal are generated.

With the above as background, reference should now be made to the following detailed description of the preferred embodiment of the invention and the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a conventional solid-state imaging system including a CCD image sensing device;

FIG. 2 is a diagram illustrating the arrangement of pixel sites and clocking electrodes in the CCD image sensing device illustrated in FIG. 1;

FIG. 3 frame timing diagram for the electronic imaging system illustrated in FIG. 1;

FIG. 4 is a line or row timing diagram for the electronic illustrated in FIG. 1;

FIG. 5 is a pixel timing diagram for the electronic imaging system illustrated in FIG. 1;

FIG. 6 is a pixel timing diagram for an electronic imaging system operating in accordance with the present invention.

FIG. 7 is a schematic block diagram of a preferred clock generator in accordance with the present invention that is used to generated the clock signals illustrated in FIG. 6.

A schematic block diagram of a conventional electronic imaging system incorporating a CCD full-frame image sensor is illustrated in FIG. 1. A KAF-1400 image sensor manufactured by the Eastman Kodak Company of Rochester, N.Y. is a typical example of a CCD full-frame image sensor that may be employed in the illustrated system. While the invention will be described with reference to a CCD full-frame image sensor, it will be understood that the invention is universally applicable to other types of electronic image sensing devices including interline devices.

The full-frame image sensor 8 includes a vertical CCD shift register 10 and a horizontal CCD shift register 12. The vertical CCD shift register 10 and the horizontal CCD shift register 12 structures are constructed using two level polysilicon and two state buried channel technology. The vertical CCD shift register 10 contains 6.8 .mu.m.times.6.8.mu.m photocapacitive sensing elements or pixels which are used to both store and transport photocharge. The pixels are arranged in a 1320 (Horizontal).times.1035 (Vertical) array in which an additional twenty columns and two rows (one each at the top and bottom) of light shielded pixels are added to provide a dark reference. The particular full-frame image sensor illustrated, unlike other types of full-frame image sensors, does not include a storage array or register between the vertical register and the horizontal register. The operation of the image sensor must therefore be synchronized with strobe illumination or a shutter operation must be utilized during readout periods. Typical applications for the such sensors include machine vision devices, film digitizers and electronic still photography devices.

The output from the horizontal CCD shift register 12 is supplied to an output amplifier 14. The output amplifier 14 in turn is coupled to a clamp circuit 16. The clamp circuit 16 is coupled to a sample and hold (S/H) circuit 18 having an output line that is coupled to video processing circuitry 20. A clock generator 22 is provided to supply the various clocking signals needed to operate the vertical and horizontal CCD shift registers 10 and 12, the clamp circuit 16, and the S/H circuit 18. A control processor 24 controls the overall operation of the electronic imaging system in response to control inputs including, for example, exposure initiation signals.

As was described above, an image is acquired when incident light falls on the array of pixels in the vertical CCD shift register 10 and creates photocharge, namely, electron-hole pairs or simply electrons, within the silicon substrate of the image sensor 8. The photocharge is collected in potential wells formed at each pixel site by the application of clock signals generated by the clock generator 22 on the vertical CCD register gate electrodes or clock lines .phi.V1 and .phi.V2 illustrated in FIG. 2. The amount of charge collected at each pixel site is linearly dependent on the incident light level and the exposure time.

The photocharge is transported from the vertical CCD shift register 10 to the output amplifier 14 in a two step process. Columns of charge are first shifted in parallel line by line into the horizontal CCD shift register 12. The .phi.V1 and .phi.V2 gate electrodes are utilized to perform the transfer operation. The horizontal CCD shift register 12 then shifts the lines or rows of charge serially pixel by pixel to the output amplifier 14 as horizontal clock signals .phi.H1 and .phi.H2 are applied to the horizontal gate electrodes .phi.H1 and .phi.H2 by the clock generator 22.

A more detailed description of the transfer operation will be provided with reference to the timing diagrams illustrated in FIGS. 3-5. As shown in the timing diagrams, capture or integration of photocharge is performed when the .phi.V1 and .phi.V2 clock signals are held to a logic low level. A transfer operation to the horizontal CCD shift register 12 begins when the .phi.V1 clock signal is brought to a logic high level which causes the charge accumulated under the .phi.V1 and .phi.V2 gate electrodes to combine under the .phi.V1 gate electrode. The polarity of the .phi.V1 and .phi.V2 clocks are then reversed causing the photocharge to "spill" forward under the .phi.V2 gate electrode of a subsequent pixel. The rising edge of the .phi.V2 clock signal also transfers the first line of photocharge into the horizontal CCD shift register 12. A second phase transition places the photocharge under the .phi.V1 gate electrode of the next pixel. The sequence is completed when the .phi.V1 clock signal is brought to a logic low level while the horizontal CCD shift register 12 shifts out the first line of photocharge using the complementary clock signals .phi.H1 and .phi.H2. The clocking of the vertical CCD shift register in the above-described manner is referred to as accumulation mode clocking. The falling edge of the .phi.H2 clock forces photocharge over an output gate (OG) of the horizontal CCD shift register 12 onto a floating diffusion node (FD) where it is sensed by the output amplifier 14 as shown in FIG. 1. The above-describe cycle repeats until all the lines of photocharge are transferred.

The potential of the floating diffusion node varies linearly with the quantity of photocharge applied thereto. The output amplifier 14 is used to buffer the change in floating gate potential to the clamp circuit 16. A reset clock signal .phi.R is used to remove the charge from the floating diffusion via a reset drain (not shown), which subsequently returns the floating diffusion potential to the reference level determined by a reset drain voltage supplied thereto. The voltage output Vout from the amplifier 14 is clamped and sampled by a clamp circuit 16 and the S/H circuit 18 in response to the CLAMP and SAMPLE clocks generated by the clock generator 22. The effective signal output is the difference in the output voltage Vout when clamped by the clamp circuit 18 and when sampled by the S/H circuit 18.

The above-described system has been found to generate non-linearities in the output signal. The source of this problem has been discovered to be related to the standard clocking sequence described above. More specifically, the problem is related to a cross-talk phenomenon occurring between the horizontal clock signals .phi.H1 and .phi.H2 and the output signal at the time of sampling. As can been seen in FIG. 5, the horizontal clock signals .phi.H1 and .phi.H2 change state between the period when the output voltage from the amplifier 14 is clamped to when the output voltage is sampled and are therefore not at the same voltage level when the clamp signal and the sample signal are generated. The change in state of the horizontal clock signals .phi.H1 and .phi.H2 at the time of clamping as opposed to the time of sampling appears to cause the cross-talk problem mentioned above.

Adjustment of the clocking sequence to insure that the horizontal clock signals .phi.H1 and .phi.H2 are at the same state when the clamp and sample signals are generated has been found to eliminate the cross-talk phenomenon. The preferred adjustment of the clocking sequence for the KAF-1400 sensor is illustrated in FIG. 6. The .phi.H1 and .phi.H2 clocks are in the same state, i.e. either a logic high or logic low level, when the clamp and sample clock signals are generated by the clock generator. This relatively simple adjustment to the image sensor timing has been found to eliminate the cross-talk problem. The elimination of the cross-talk substantially improves linearity as well as the dynamic range and signal to noise ratio of the system, thereby improving the overall response of the system. Comparison testing has shown that a system equipped with the KAF-1400 sensor and capable of reading densities from 0.3 ND to 1.8 ND prior to modification could read the distinct differences in density patches ranging from 0.3 ND to 2.4 ND after the clocking sequence was modified as shown in FIG. 6.

It should be noted that any type of timing generator can be used to produce the desired horizontal clocking signals. In a preferred embodiment of the clock generator shown in FIG. 7, programmable gate array devices are utilized to generate the desired clocking signals. A signal from a master clock 30 is supplied to a counter 32 and a pixel rate PAL 34. The pixel rate PAL 34 generates the horizontal clock signals .phi.H1 and .phi.H2, the sample clock signal SAMPLE, and the clamp clock signal CLAMP in response to a count signal supplied from the counter 32. One output (Next.sub.-- Pixel) of the pixel rate PAL 34 is also used to clock a line rate PAL 36, which in turn, produces the vertical clock signals .phi.V1 and .phi.V2. One output of the line rate PAL 36 (Horz.sub.-- Clk.sub.-- En) is fed back to the input of the pixel rate PAL 34 to enable or disable the operation of the horizontal clocks .phi.H1 and .phi.H2 during vertical transfer periods.

The invention has been described with reference to certain preferred embodiments thereof. It will be understood, however, that variations and modifications can be made within the scope of the appended claims. For example, the specifics of the clocking scheme may vary as long as the horizontal clock signals are at the same state when the clamp and sample clocks are generated.