Sense Amplifier Control Circuit of a Semiconductor Memory Device

The present invention relates to a dynamic random access memory (DRAM), and more particularly to a sense amplifier control circuit which stabilizes the device characteristic of a cell by clamping an external power voltage as an internal power voltage.

With the highly integrated semiconductor memory device, the occupying area of a transistor is reduced, to thereby miniaturize the size of the transistor. Accordingly if an external power voltage is applied to a reduced sense amplifier and a memory cell without any conversion, the device characteristic of the memory cell is distorted. For example, a peak current is increased and power noise is generated during a sensing operation. This results in a malfunctioning of the stable sense amplifier and the memory cell as a memory device. Moreover, in a sense amplifier control circuit, since the external power voltage is applied to the sense amplifier and the memory cell by an active restore signal, through a sense amplifier driver transistor without any conversion, the characteristic of the sense amplifier control circuit, as the memory device, is deteriorated.

FIG. 1 shows a circuit diagram illustrating a conventional sense amplifier control circuit; FIG. 2 shows an operating timing chart of FIG. 1 and FIG. 3 shows a characteristic graph of the voltage applied to a cell in FIG. 1; Referring to FIG. 1, when a p-type sense amplifier enable clock .phi..sub.SP is raised to a logic "high" of a power voltage level, a p-type sense amplifier driver enable clock .phi..sub.PSE is lowered to a logic "low" of a ground voltage level through an inverter 3, thereby enabling a p-type sense amplifier driver 4 is turned on.

In FIG. 2, when a row address strobe signal RAS is set to the logic "low" level, a n-type sense amplifier driver enable clock .phi..sub.NSE is set to the logic "high" level, to thereby perform the sensing operation in a n-type sense amplifier. Moreover, the p-type sense amplifier enable clock .phi..sub.SP is set to the logic "high" level, as a result, the sensing operation is performed in a p-type sense amplifier. However, as shown in FIG. 3, since the p-type sense amplifier driver 4 transmits most of the external power voltage ext.V.sub.CC to the p-type sense amplifier and the memory cell, in case that the external power voltage ext.V.sub.CC is set to a sufficiently high level, i.e., the power voltage level, a threshold voltage of the cell is varied, thereby deteriorating the device characteristic of the cell. That is, the life time of the cell becomes shorter, and the peak current is increased and the power noise is generated during the sensing operation. The characteristic of the sense amplifier control circuit, as the memory device, also becomes considerably unstable.

FIG. 4 shows a circuit diagram illustrating another sense amplifier control circuit of a prior art; and FIG. 5 shows an operating timing chart of FIG. 4. The circuit in FIG. 4 is constructed in that a voltage up to a given level, by using an internal power voltage stage, is applied to a sense amplifier and a memory cell. The construction of the internal power voltage stage and its connection in relation to FIG. 4 are described in detail in IEEE Journal of Solid-State Circuits, Vol.24, No.5, "A 45-ns 16-M bit DRAM with Triple-Well Structure", issued on October 1989. In FIG. 4, when the external power voltage ext.V.sub.CC is 5 V, an internal power voltage int.V.sub.CC of approximately 4 V is selected to clamp the voltage applied to the memory cell and the sense amplifier. If a row address strobe signal RAS is lowered to the logic "low" level, NMOS transistors 17 and 18 are turned on, and then, by an output of a comparator in the logic "low" level, a node B is set to the logic "low" level and a node C is set to the logic "high" level. According to the node C of the logic "high" level, a NMOS transistor 20 connected to a constant-current source 30 is turned on, a PMOS transistor 19 is turned off, and NMOS transistors 21, 26 and 27 connected, through respective to a ground voltage are turned on. Moreover, an output node D connected to the drain of the PMOS transistor 19 is set to the logic "low" level and a p-type sense amplifier driver 29 is turned on, thereby raising the voltage of a p-type sense amplifier enable signal SAP. When the voltage of the p-type sense amplifier enable signal SAP reaches up to 4 V, the gate voltage of a NMOS transistor 25 of the comparator is increased, and the gate voltage of each PMOS transistors 22 and 23 is decreased. As a result, the comparator produces the logic "high" level. In response to the logic "high" level of the comparator, node B is set to a logic "high" level; and node C is set to a logic "low" level. The PMOS transistor 19 is then turned on, the NMOS transistor 20 is turned off, and the NMOS transistors 21, 26 and 27 are turned off. The output node D connected to the drain of the PMOS transistor 19 is set to the logic "high" level; and the p-type sense amplifier driver 29 is turned off, thereby maintaining the voltage of the p-type sense amplifier enable signal SAP as a voltage of 4 V. At this time, under the condition that the p-type sense amplifier driver 29 is turned off, the voltage of the p-type sense amplifier enable signal SAP is lowered as much as .DELTA. V, because of the leakage current of each transistor constituting the memory cell and the sense amplifier, as shown in FIG. 5. However, since node C is set at the logic "low" level state, the NMOS transistors 21, 26 and 27 are turned off; and the comparator is thereby incapable of operating. Therefore, the p-type sense amplifier enable signal SAP can't be restored as a normal voltage of 4 V. As a result, a sufficient voltage to the cell and to the sense amplifier is not obtainable, which leads to an insufficient sensing operation of the sense amplifier.

It is therefore an object of the present invention to provide a sense amplifier control circuit capable of improving the device characteristic of a memory cell, and sufficiently performing the sensing operation of the sense amplifier by maintaining a voltage applied to a memory cell and a sense amplifier at a given level.

In accordance with the present invention, the sense amplifier, comprises a driver control circuit, a bias circuit, and a driving circuit for driving the drive control circuit and the bias circuit. The drive control circuit is connected, by its output line, to a control terminal of a first sense amplifier driver, and is for maintaining the current flowing into the first sense amplifier driver at a given level. The bias circuit connected by its output line to the driver control circuit, is for maintaining the current flowing into a driving device of the driver control circuit at a given level. The driving means receives the output of the sense amplifier of a memory cell array, and transfers the output thereof to the driver control circuit and to the bias circuit, to thereby drive the driver control circuit and the bias circuit. The driving circuit includes a comparator for comparing the voltage applied to a memory cell with a given reference voltage and for producing an output thereof in response to the control of a given clock signal; a level shift circuit for converting the voltage of a second power voltage stage into the voltage of a first power voltage stage by the control of the given clock signal, a comparator enable circuit for enabling or disabling the output of the comparator by the control of the level shift circuit, and a trigger circuit for inverting the output of the comparator.

The advantages and features of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with the reference to the attached drawings, in which:

FIG. 1 shows a circuit diagram illustrating a conventional sense amplifier control circuit;

FIG. 2 shows a timing chart illustrating an operation of the circuitry shown in FIG. 1;

FIG. 3 shows a characteristic graph illustrating the voltage applied to a cell in FIG. 1;

FIG. 4 shows a circuit diagram illustrating another sense amplifier control circuit of a prior art;

FIG. 5 shows a timing chart illustrating an operation of the circuitry shown in FIG. 4;

FIG. 6 shows a block diagram of a sense amplifier control circuit according to the present invention;

FIG. 7 shows a circuit diagram of a sense amplifier control circuit according to the present invention;

FIGS. 8A to FIG. 8C show circuit diagrams of clock signals of FIG. 7;

FIG. 8D shows a timing chart illustrating an operation of the circuitry shown in FIG. 7;

FIG. 8E shows a partial more detailed timing chart of FIG. 8D

FIG. 9 shows a characteristic graph illustrating the voltage applied to a cell in FIG. 7; and

FIG. 10 shows a characteristic graph illustrating an output voltage according to the temperature of a bias circuit as a function of an external power voltage.

Referring to FIG. 6, a sense amplifier control circuit 50 includes a comparator 50A, a trigger circuit 50D, a level shift circuit 50B, a comparator enable circuit 50C, a bias circuit 50E and a p-type sense amplifier driver control circuit 50F. The comparator 50A compares the voltage of a p-type sense amplifier 70 of a memory cell array 100 with a given reference voltage V.sub.REF in dependence upon a p-type sense amplifier enable signal .phi..sub.SP to produce an output thereof. The level shift circuit 50B converts a second power voltage of the p-type sense amplifier enable signal .phi..sub.SP into a first power voltage. In this case, the first power voltage is an external power voltage stage having a usual voltage of 5 V and the second power voltage is an internal power voltage stage having a voltage of approximately 4 V. The comparator enable circuit 50C enables or disables the output of the comparator 50A in dependence upon the output of the level shift circuit 50B. The trigger circuit 50D receives the outputs of the comparator 50A and the comparator enable circuit 50C, to produce an inverted output. The bias circuit 50E receives the output of the trigger circuit 50D and controls a constant current flowing into a driving device of the p-type sense amplifier driver control circuit 50F. The p-type sense amplifier driver control circuit 50F receives the outputs of the trigger circuit 50D and the bias circuit 50E, and transfers an output thereof to a p-type sense amplifier driver 61, thereby controlling the constant current flowing into a p-type sense amplifier driver 61.

Referring to FIG. 7, the comparator 50A is comprised of a first PMOS transistor 31 having a source connected to an external power voltage ext.V.sub.CC and diode-connected gate and drain; a second PMOS transistor 32 having a source connected to the external power voltage ext.V.sub.CC and a gate connected to the gate of the first PMOS transistor 31; a first NMOS transistor 33 having a gate connected to a p-type sense amplifier enable node 62 and a drain connected to the drain of the first PMOS transistor 31; a second NMOS transistor 34 having a gate connected to a given reference voltage V.sub.REF and a drain connected to the drain of the second PMOS transistor 32; an output node N1 connected to the common terminal of the second PMOS and NMOS transistors 32 and 34; and a third NMOS transistor 35 having a drain connected to the sources of the first and second NMOS transistors 33 and 34, a gate coupled to receive the p-type sense amplifier enable signal .phi..sub.SP and a source coupled to receive a ground voltage.

The level shift circuit 50B includes a first PMOS transistor 39 having a source connected to the external power voltage ext.V.sub.CC ; a second PMOS transistor 40 having a source connected to the external power voltage ext.V.sub.CC ; a first NMOS transistor 41 having a gate connected to receive the p-type sense amplifier enable signal .phi..sub.SP, a source connected to the ground voltage and a drain commonly connected to the drain of the first PMOS transistor 39 and to the gate of the second PMOS transistor 40; an inverter 43 having an input terminal connected to a given clock signal and controlled by an internal power voltage int.V.sub.CC ; a second NMOS transistor 42 having a source connected to the ground voltage and a gate connected to the output terminal of the inverter 43; and an output node N3 commonly connected to the gate of the first PMOS transistor 39 and to each drain of the second PMOS and NMOS transistors 40 and 42.

The comparator enable circuit 50C is comprised of a PMOS transistor 36 having a source connected to the external power voltage ext.V.sub.CC, a gate connected to the output node of the level shift circuit 50B and a drain connected to the output node of the comparator 50A.

The trigger circuit 50D includes a PMOS transistor 37 having a source connected to the external power voltage ext.V.sub.CC and a gate connected to the output node of the comparator 50A; a NMOS transistor 38 having a source connected to the ground voltage and a gate connected to the output node of the comparator 50A; and an output node N2 commonly connected to each drain of the PMOS and NMOS transistors 37 and 38.

The bias circuit 50E is comprised of a PMOS transistor 44 having a source connected to the internal power voltage int.V.sub.CC and a gate connected to the ground voltage; a first NMOS transistor 45 having a drain connected to the drain of the PMOS transistor 44 and a gate connected to the output node of the trigger circuit 50D; an output node N4 commonly connected to each drain of the PMOS and first NMOS transistors 44 and 45, for generating a bias voltage V.sub.B ; and a second NMOS transistor 46 having a drain and gate diode-connected to the source of the first NMOS transistor 45 and having a source connected to the ground voltage.

The p-type sense amplifier driver control circuit 50F includes a PMOS transistor 47 having a source connected to the external power voltage ext.V.sub.CC and a gate connected to the output node of the trigger circuit 50D; a first NMOS transistor 48 having a gate connected to the output node of the trigger circuit 50D; an output line commonly connected to the common terminal of the first PMOS and the first NMOS transistors 47 and 48 and the control terminal of the sense amplifier driver 61, for producing a p-type sense amplifier driver enable clock .phi..sub.PSE ; a second NMOS transistor 49 having a gate connected to the output node of the bias circuit 50E, and a current maintaining circuit connected between the external power voltage ext.V.sub.CC and the output line, for constantly maintaining the current flowing into the first and second NMOS transistors 48 and 49. In this case, the current maintaining circuit comprises first and second PMOS transistors 50 and 51. The source of the first PMOS transistor 50 is connected to the external power voltage ext.V.sub.CC, with the diode-connected gate and drain. The both terminals of the second PMOS transistor 51 are connected between the drain of the first PMOS transistor 50 and the output line, with the gate connected to the ground voltage.

The operation of FIG. 7 will be described with reference to FIGS. 8A to 8E. As shown in FIG. 8B, a sensing enable clock .phi..sub.S produced through a delay circuit 74 and a master clock .phi..sub.R are transmitted to a NAND gate 75 and then to an inverter 76, to produce an n-type sense amplifier driver enable clock .phi..sub.NSE. The master clock .phi..sub.R is a signal generated, through three successive inverters 71, 72 and 73 receiving a row address strobe signal RAS, as shown in FIG. 8A. In FIG. 8C, the output generated through three inverters 77, 78 and 79 receiving the n-type sense amplifier driver enable clock .phi..sub.NSE, and the output generated through an inverter 80 receiving the master clock .phi..sub.R, are input into a NOR gate 81 to produce an output signal. The output signal is then delayed through two inverters 82 and 83 to produce a p-type sense amplifier enable clock .phi..sub.SP. Turning to FIG. 7, the p-type sense amplifier enable signal SAP is initially precharged to a half level of the internal power voltage int.V.sub.CC. That is, when the row address strobe signal RAS is in a precharged state of a logic "high" level, the p-type sense amplifier enable clock .phi..sub.SP is set to a logic "low" level, the second NMOS transistor 42 of the level shift circuit 50B is turned on, and the level shift circuit 50B produces an output of the logic "low" level. Therefore, the PMOS transistor 36 of the comparator enable circuit 50C is turned on, the output of the comparator 50A becomes disabled state and the logic "high" level signal is input into the trigger circuit 50D. The trigger circuit 50D is set to the logic "low" level, and the bias circuit 50E is set to the logic "high" level since the first NMOS transistor 45 is turned off. The p-type sense amplifier driver control circuit 50F produces the output of the logic "high" level, the PMOS sense amplifier driver 61 is turned off and the p-type sense amplifier enable signal SAP is precharged to the half level of the internal power voltage int.V.sub.CC.

Now, how the bias circuit 50E is operated is described. The output line of the bias circuit 50E is connected to the driving element of the driver control circuit 50F, i.e., the gate of the second NMOS transistor 49, thus constantly setting the current i.sub.B. As shown in FIG. 10, if the external voltage ext.V.sub.CC is increased, the voltage of the node N2 is increased. Therefore, the voltage V.sub.GS of the first NMOS transistor 45 is increased and the voltage V.sub.B at the node N4 is decreased. Furthermore, since the voltage V.sub.GS of the second NMOS transistor 49 of the driver circuit 50F is decreased, the increase of the current i.sub.B caused by the increased external power voltage ext.V.sub.CC can be prevented. At this time, since the voltage V.sub.B at the node N4 is continuously applied to the gate of the second NMOS transistor 49, there is no case that the NMOS transistor 49 is turned off. In contrast, if the external power voltage ext.V.sub.CC is decreased, since the voltage of the node N2 is decreased, the voltage V.sub.GS of the first NMOS transistor 45 is decreased and the voltage V.sub.B at the node N4 is increased. Moreover, since the voltage V.sub.GS of the second NMOS transistor 49 of the driver circuit 50F is increased, the decrease of the current i.sub.B caused by the decreased external power voltage ext.V.sub.CC can be prevented. Therefore, the current i.sub.DS between the drain and source flowing into the PMOS sense amplifier driver 61 is constantly set, with the result that a constant rising slope of the p-type sense amplifier enable signal SAP is provided, regardless of the variation of the external power voltage ext.V.sub.CC.

Next, the operation of the driver control circuit 50F is described, If the node N2 is in the low level state, the p-type sense amplifier driver enable clock .phi..sub.PSE is set to the logic "high" level and the p-type sense amplifier drivers 61, 65, . . . are turned off. In contrast, the node N2 is in the logic "high" level state, the p-type sense amplifier driver enable clock .phi..sub.PSE is set to the logic "low" level and the p-type sense amplifier drivers 61, 65, . . . are turned on. Moreover, since the first NMOS transistor 48 is turned on, the constant current i.sub.B comes to flow. Even when the external power voltage ext.V.sub.CC is increased, since the current i.sub.B is constant, the voltage of the p-type sense amplifier driver enable clock .phi..sub.PSE is increased. In more detail, if the external power voltage ext.V.sub.CC is increased, the voltage between the drain and the source of the p-type sense amplifier drivers 61, 65, . . . is increased. Therefore, the gate voltage of the p-type sense amplifier drivers 61, 65, . . . i.e., the p-type sense amplifier driver enable clock .phi..sub.PSE is increased. As a result, the voltage V.sub.GS between the gate and the source is decreased, to thereby constantly maintain the current flowing into the p-type sense amplifier drivers 61, 65, . . . .Consequently, since the channel current independent of the external power voltage ext.V.sub.CC is provided, the rising slope of the p-type sense amplifier enable signal SAP is constant at a range of the external power voltage ext.V.sub.CC of the logic "high" level or "low" level, to thereby solve a problem associated with the increase of the peak current due to the rapid rising slope of the p-type sense amplifier enable signal SAP.

Next, when the row address strobe signal RAS is set to the logic "low" level and a row address is selected, the operation of FIG. 7 is described as follows. When a word line is selected and the charge sharing between a bit line and a cell is performed by the decoding of a row address. Then, a n-type sense amplifier driver enable clock .phi..sub.NSE is set to the logic "high" level and the NMOS sense amplifier drivers 63, 67, . . . are turned on, thereby sensing the bit lines. The p-type sense amplifier enable clock .phi..sub.SP is set to the logic "high" level and the output node N3 of the level shift circuit 50B reaches the external power voltage ext.V.sub.CC. As a result, the PMOS transistor 36 of the comparator enable circuit 50C is turned off and the output of the comparator 50A is enabled. Since the reference voltage V.sub.REF of 4 V is larger than the voltage of the p-type sense amplifier enable signal SAP, the comparator 50A is set to the logic "low" level at the node N1. In this case, the p-type sense amplifier enable clock .phi..sub.SP is applied to the gate of the third NMOS transistor 35 in the comparator 50A. The trigger-circuit 50D detects the logic "low" level state of the node N1 and generates the logic "high" level at the node N2. The output of the trigger circuit 50D of the logic "high" level state enables the bias circuit 50E and the driver control circuit 50F.

Consequently, the p-type sense amplifier drivers 61, 65, . . . are turned on by the p-type sense amplifier driver enable clock .PHI..sub.PSE, the voltage of the p-type sense amplifier enable signal SAP has a constant rising slope independent of the variation of the external power voltage ext.V.sub.CC. Moreover, if the voltage of the p-type sense amplifier enable signal SAP reaches 4 V, the gate voltage of the first NMOS transistor 33 of the comparator 50A is increased. Therefore, the node N1 is set to the logic "high" level, the output of the trigger circuit 50D is set to the logic "low" level, and the output of the bias circuit 50E is set to the internal power voltage int.V.sub.CC. Since the first NMOS transistor 48 of the driver control circuit 50F is turned off, the p-type sense amplifier driver enable clock .phi..sub.PSE is set to the logic "high" level and the p-type sense amplifier drivers 61, 65, . . . are turned off, which prevents the voltage of the p-type sense amplifier enable signal SAP from increasing above 4 V as shown in FIG. 9. If the voltage of the p-type sense amplifier enable signal SAP is lowered to the voltage of below 4 V at a range of A due to the leakage current of each transistor constituting the memory cell and the sense amplifier the voltage of the p-type sense amplifier enable signal SAP is again raised to a range of B in dependence upon the operation of the comparator 50A as shown in FIG. 8E. In a conventional sense amplifier control circuit shown in FIG. 4, the comparator 50A is not operable after the voltage of the p-type sense amplifier enable signal SAP rises from the precharged state to a voltage of 4 V. However, in the sense amplifier control circuit in accordance with the present invention, since the control voltage of the comparator 50A becomes the p-type sense amplifier enable clock .phi..sub.SP and is a continuously enabled state, the voltage of the SAP is maintained as a voltage of 4 V, by detecting the voltage of the p-type sense amplifier enable signal SAP whenever the SAP is lowered.

As described above, in the sense amplifier control circuit according to the present invention, since the voltage applied to the memory cell is clamped at a given level (in this case, 4 V), the distortion of the device characteristic of the cells caused by the logic "high" level of V.sub.CC can be prevented. Moreover, the peak current due to the p-type sense amplifier sensing is suppressed and the power noise is reduced, thereby improving the reliability of a semiconductor memory device.

While the invention has been particularly shown and described with reference to the preferred embodiment of the present invention thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.