Internally Regulated Power Voltage Circuit for MIS Semiconductor Integrated Circuit

The present invention relates to a MIS semi-conductor integrated circuit containing MISFETs as circuit elements and, more particularly, to a MIS semiconductor integrated circuit containing MISFETs of which the effective channel length is approximately 1 .mu.m or less.

With the substantial progress recently made in the development of semiconductor integrated circuits containing MOSFETs as one type of MISFETs, integrated circuits containing several tens or hundreds of MOSFETs with an effective channel length of about 10 .mu.m per chip were realized in the later half of 1960. The advanced micro-fabrication technique has further improved the integration density of the integrated circuits, thus allowing for the realization of VLSIs containing several hundred thousand elements, with an effective channel length of about 1.5 .mu.m per chip.

Submicron semiconductor integrated circuits having submicron MOSFETs with an effective channel length of 1 .mu.m or less may be realized in near future.

In the conventional MIS semiconductor integrated circuit, the internal circuit is directly driven by a power source voltage which is externally supplied. The value of the power source voltage decreases with the reduction of the effective channel length of the MISFETs (MOSFETs), making up the internal circuit. A 5 V power source voltage is used in driving the internal circuit of semiconductor integrated circuits containing MOSFETs with an effective channel length of, for example, 1.5 .mu.m.

Reduction of the effective channel length of the MOSFET increases the electric field thereof, if the power voltage is fixed. An increase in the electric field of the MOSFET adversely influences its elementary characteristics in the following ways.

1. Hot electrons or hot halls are generated, due to the impact of ionization.

2. The substrate current is increased.

3. The punch-through withstand capacity is reduced.

4. PN contacts containing sources and drains are broken down.

5. The threshold voltage changes over time, due to the trapping of hot carriers within the gate insulation film.

To avoid the above disadvantages, strict requirements are applied in setting the value of the externally applied power source voltage.

In the future, the submicron semiconductor integrated circuit will require a power source with a voltage level lower than that of the 5 V power source voltage, which is currently used as a standard power source, to avoid the above problems (1-5). The aging of the threshold voltage of the MOSFET, which is due to the trapping of hot carriers (See 5, above), may markedly deteriorate the speed performance of the submicron semiconductor integrated circuit, or may cause the imperfect operation of the submicron semiconductor integrated circuit.

FIG. 1 shows a cross-section illustrating the structure of a general enhancement type MOSFET. In the figure, reference numeral 1 designates a P type silicon semiconductor substrate. An n.sup.+ type source region 2 and an n.sup.+ type drain region 3 are diffused into the surface region of the substrate 1. A gate electrode 6 made of polysilicon, for example, is formed above a channel region 4 located between the source and drain regions 2, 3, while overlaying a gate insulating film 5. In FIG. 1, "Leff" indicates the effective channel length of the MOSFET.

FIG. 2 illustrates an energy band of the MOSFET shown in FIG. 1. A potential barrier .phi.e for electrons, which is formed at the boundary between the substrate 1 and the gate insulating film 5, is 3.1 eV; and a potential barrier .phi.h for holes is approximately 3.8 eV. Let us assume that the geometry of the MOSFET is further reduced and the effective channel length (Leff) is reduced to 1 .mu.m or less. Under such geometrical conditions, if the power source voltage is kept at 5 V, the probability that hot electrons and holes generated by impact ionization will exceed the above potential barriers .phi.e, .phi.h and enter the gate insulating film 5 is high. These electrons and holes entering the gate insulating film 5, are then trapped by the same film, so that the aging of the threshold voltage is great. In assembling many and various types of semiconductor integrated circuits into a system, it is desirable, for size and cost-reduction purposes, that the semiconductor integrated circuits be operable by a single and common power source. It is also preferable that the submicron semiconductor integrated circuit be operable by a standard power source voltage of 5 V, since it is frequently used in connection with the TTL circuits. In semiconductor integrated circuits of the type in which the internal circuit is directly driven by an external power source, however, use of the 5 V power source voltage is accompanied by a deterioration of the circuits characteristic, as mentioned above, possibly making the elements defective.

Further, in conventional semiconductor integrated circuits, such factors as operating speed and power dissipation depend largely on the externally applied power source voltage. This makes the circuit design complex, so that the semiconductor integrated circuits are not easy to handle in their systems applications.

Additionally, the conventional semiconductor integrated circuit must be operated by using a high precision power source. If it is driven by a poor precision power source, an overvoltage application might cause the internal MOSFETs to be deteriorated, degrading their reliability. Moreover, when a spike voltage or noise appears on the power line, the internal MOSFETs are deteriorated or erroneously operated.

Accordingly, the primary object of the present invention is to provide a MIS semiconductor integrated circuit in which the internal MISFETs are not deteriorated, ensuring high reliability, even if said circuit is operated against an external power voltage which is substantially varied.

A second object of the present invention is to provide a MIS semiconductor integrated circuit which can sustain a stable performance against an externally supplied power voltage which is substantially varied.

A third object of the present invention is to provide a MIS semiconductor integrated circuit which is stably operable, regardless of the spike voltage or noise appearing on the power line.

According to the present invention, a MIS semiconductor integrated circuit is provided, which comprises: a power source voltage terminal externally supplied with a power source voltage; an internal power source circuit including voltage dropping means having a control terminal, a voltage input terminal, a voltage output terminal, the voltage input terminal being supplied with the voltage at the power source voltage terminal; a detecting means which detects a voltage at the voltage output terminal of the voltage dropping means at a predetermined threshold and supplies the detection signal thereof to the voltage dropping means; and an internal circuit which is operable under the voltage of the internal power source circuit, said internal circuit containing MISFETs with a predetermined effective channel length.

FIG. 1 shows a cross-sectional view of the structure of a general MOSFET:

FIG. 2 illustrates an energy band of the MOSFET shown in FIG. 1;

FIG. 3 is a block diagram of a MIS semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of the circuit of FIG. 3;

FIG. 5 is a circuit diagram of a modification of the FIG. 4 circuit;

FIG. 6 is a circuit diagram of another modification of the FIG. 4 circuit;

FIG. 7 is a circuit diagram of yet another embodiment of the FIG. 4 circuit;

FIG. 8 is a block diagram of a MIS semiconductor integrated circuit according to another embodiment of the present invention;

FIG. 9 illustrates the detailed circuitry of a portion of the FIG. 8 circuit;

FIG. 10 is a block diagram of a MIS semiconductor integrated circuit according to yet another embodiment of the present invention;

FIG. 11 is a circuit diagram of an embodiment of the FIG. 10 circuit;

FIG. 12 shows a practical arrangement of a portion of the circuit of FIG. 11;

FIG. 13 is a circuit diagram of a modification of the FIG. 11 circuit;

FIG. 14 is a circuit diagram of another modification of the FIG. 11 circuit;

FIG. 15 is a circuit diagram of yet another embodiment of the FIG. 11 circuit;

FIG. 16 is a circuit diagram of a further modification of the FIG. 11 circuit; and

FIG. 17 is a block diagram of a MIS semiconductor integrated circuit according to a further embodiment of the present invention.

Various types of preferred embodiments of the present invention may be described with reference to the accompanying drawings. FIG. 3 is a block diagram of a MIS semiconductor integrated circuit according to a preferred embodiment of the present invention. In the MIS semiconductor integrated circuit (10), an internal power source circuit 20, an internal circuit 30 containing MOSFETs with an effective channel length of 1 .mu.m or less, and various terminals (e.g., a power source voltage terminal 40 externally supplied with a positive power source voltage V.sub.CC, a power source voltage terminal 50 externally supplied with another power source voltage V.sub.SS of 0 V, a plurality of input terminals 60a-60n, and a plurality of output terminals 70a-70n) are formed on a semiconductor chip. The internal circuit 30 is driven by the power source voltage V.sub.DD supplied from the internal power source circuit 20. The internal circuit 30 may be an overall memory circuit, a portion of the memory circuit, a microprocessor circuit, a digital signal processing circuit, a digital control circuit, a gate array circuit, etc.

The internal power source circuit 20 produces a fixed internal power source voltage V.sub.DD, using the power source voltage V.sub.CC supplied from the power source voltage terminal 40. The internal power source circuit 20 is comprised of a voltage dropping circuit 24 for generating an internal fixed power source voltage V.sub.DD, by using an externally supplied power voltage V.sub.CC supplied to the power source voltage terminal 40, said voltage dropping circuit 24 having a control terminal 21, a voltage output terminal 23, and a voltage input terminal 22 supplied with the voltage V.sub.CC from said power source voltage terminal 40; and a voltage detecting circuit 26 which receives at the input terminal 25 the voltage of the voltage output terminal 23 in the voltage dropping circuit 24, detects the voltage V.sub.DD at a predetermined threshold, and supplies this detected voltage to the control terminal 21 of the voltage dropping circuit 24.

In the MIS semiconductor integrated circuit thus arranged, the internal power source circuit 20 produces a fixed voltage V.sub.DD, using the voltage V.sub.CC supplied to the power source voltage terminal 40. The voltage V.sub.DD, so produced is lower than voltage V.sub.CC, and is used as a power source voltage for the internal circuit 30. To be more specific, the voltage dropping circuit 24 drops the voltage V.sub.CC according to the detected output signal from the voltage detecting circuit 26, which appears at the control terminal 21. Through this voltage dropping, voltage V.sub.DD is obtained. The voltage detecting circuit 26 detects the dropped voltage V.sub.DD by using the predetermined threshold voltage. The detected output of the voltage detecting circuit 26 is directed to the control terminal 21 of the voltage dropping circuit 24, to form a closed loop containing the voltage detecting circuit 26 and the voltage dropping circuit 24. With this re-direction, the voltage V.sub.DD at the voltage output terminal 23 of the voltage dropping circuit 24 is so controlled as to be equal to the threshold voltage V.sub.TH through the closed loop.

FIG. 4 shows a practical arrangement of the functional diagram of FIG. 3. The voltage dropping circuit 24 is comprised of an enhancement type P channel MOSFET 101 of which the gate, source and drain are connected to the control terminal 21, the input terminal 22 and the voltage output terminal 23, respectively. The drain voltage is supplied as the internal power source voltage V.sub.DD to the internal circuit 30, and to the input terminal 25 of the voltage detecting circuit 26. The voltage detecting circuit 26 is comprised of a couple of CMOS inverters 104 and 105, which are connected in a cascade fashion. The CMOS inverter 104 includes a P channel MOSFET 102 and an N channel MOSFET 103 supplied with the voltage V.sub.DD. The CMOS inverter 105 has a similar construction to that of the inverter 104. The threshold voltage V.sub.TH of the voltage detecting circuit 26 is determined depending on the threshold voltage of two MOSFETs 102 and 103 and a ratio of the conductance of each of the two MOSFETs 102 and 103 which make up the prestage CMOS inverter 104. The threshold voltage V.sub.TH of the voltage detecting circuit 26 is set at a level below the magnitude (.phi.h.delta.3.8 eV) of the potential barrier shown in FIG. 2. In FIG. 4, the internal circuit 30 illustrated contains only a CMOS inverter, for the sake of simplicity.

With such an arrangement, if the internal power source voltage V.sub.DD is lower than the threshold voltage V.sub.TH of the voltage detecting circuit 26, the output of the prestage CMOS inverter 104 in the voltage detecting circuit 26 is at a high level (V.sub.CC level). Therefore, since the output of the poststage CMOS inverter 105 is at a low level (V.sub.SS), the detected output of the voltage detecting circuit 26 is also at a low level. Under such conditions the P channel MOSFET 101 is turned on. Upon the turning on of the MOSFET 101, a parasitic capacitor which is parasitic with respect to the power line for voltage V.sub.DD is charged by voltage V.sub.CC, so that voltage V.sub.DD gradually increases. When voltage V.sub.DD exceeds the threshold voltage of the voltage detecting circuit 26, the output voltage of the CMOS inverter 104 which has been at a high level is so inverted as to be at a low level. Successively, the output of the CMOS inverter 105 is inverted from the low to the high level. As a result, the detected output of the voltage detecting circuit 26 attains a high level. Then, the P channel MOSFET 101 is cut off. Upon the cut-off of the MOSFET 101, the parasitic capacitor is discharged through the internal circuit 30, and voltage V.sub.DD gradually drops. In this way, the P channel MOSFET 101 performs a switching operation to make the internal power source voltage V.sub.DD equal to the threshold voltage V.sub.TH. In this case, if the mutual conductance, which depends upon the ratio of the channel width (W) to the channel length (L), W/L, of the P channel MOSFET 101 for voltage dropping, is set at a high level, the internal power source voltage obtained is large and stable. Moreover, the time constant, as determined by the mutual conductance and the parasitic capacitance, is small at the point of charge by the voltage V.sub.DD. Therefore, the response is quickened at the time of setting the voltage V.sub.DD. Thus, the internal power source voltage V.sub.DD is invariable even when the externally supplied power source voltage V.sub.CC changes in a wide range of 3 to 8 V. In this embodiment, the fixed voltage V.sub.DD, or the internal power source voltage, which is formed by dropping the externally supplied power source voltage V.sub.CC, is 3 V. Our experiment confirmed that the internal power source voltage V.sub.DD keeps its constancy against a variation of the externally supplied power source voltage V.sub.CC, and a spike voltage and noise, which appear on the power line. Therefore, the internal circuit 30 driven by the internal power source voltage V.sub.DD is perfectly protected from a high voltage, ensuring high reliability in operation.

In the internal power source circuit shown in FIG. 5, the voltage dropping circuit 24 is composed of an enhancement type N channel MOSFET 106. The MOSFET 106 is connected, at the drain, to the voltage input terminal 22; at the gate, to the control terminal 21, and at the source, to the voltage output terminal 23. The source voltage is supplied, as the internal power source voltage V.sub.DD, to the internal circuit 30, as well as to the input terminal 25 of the voltage detecting circuit 26. The voltage detecting circuit 26 is composed of an inverter 109 containing an N channel MOSFET 107 and a load resistor 108. The internal power source voltage V.sub.DD is supplied to the gate of the MOSFET 107. In this embodiment, the N channel voltage dropping MOSFET is used in place of the P channel MOSFET 101 which is used in the FIG. 4 embodiment. Therefore, the on/off operation of the circuit to the signal at the control terminal 21 is inverted. For this reason, the voltage detecting circuit 26 is made up of a single stage of the inverter, although that of the FIG. 4 embodiment contains double stages of inverters. Of course, the MOSFET 106 may be of the depletion type.

FIG. 6 shows another practical example of the FIG. 3 arrangement. In the internal power source circuit shown in FIG. 6, a PNP bipolar transistor 110 is used as the voltage dropping circuit 24, in place of the P channel MOSFET 101 of FIG. 4. The transistor 110 is connected, at the emitter, to the voltage input terminal 22; at the base, to the control terminal 21, and, at the collector, to the voltage output terminal 23. The collector voltage is supplied, as the internal power source voltage V.sub.DD to the internal circuit 30, and to the input terminal 25 of the voltage detecting circuit 26. In this example, the voltage detecting circuit 26 is similar to the corresponding circuit of FIG. 4, in which a fixed and stable internal power source voltage V.sub.DD appears at the collector of the transistor 110, through an operation similar to that of FIG. 4.

FIG. 7 shows yet another practical arrangement of the configuration of FIG. 3. In the internal power source circuit shown in FIG. 7, an NPN bipolar transistor 111 is used as the voltage dropping circuit 24, whereas the voltage dropping circuit 24 of FIG. 5 consists of an N channel MOSFET 106. The transistor 111 is connected, at the collector, to the voltage input terminal 22; at the base, to the control terminal 21; and, at the emitter, to the voltage output terminal 23. The emitter voltage is applied, as the internal power source voltage V.sub.DD, to the internal circuit 30 and to the input terminal 25 of the voltage detecting circuit 26. In this example, the voltage detecting circuit 26 consists of a single stage of the CMOS inverter 114 containing a P channel MOSFET 112 and an N channel MOSFET 113. The internal power source voltage V.sub.DD in question is obtained at the emitter of the transistor 111. In this example, a circuit arrangement similar to the voltage detecting circuit 26 of FIG. 5 may be employed; however, use of the CMOS inverter is preferable, to feed a larger base current to the bipolar transistor 111 and reduce the on-resistance of the transistor 111.

A block diagram of a MIS semiconductor integrated circuit according to an embodiment of the present invention is shown in FIG. 8. This embodiment is different from the FIG. 3 embodiment, in that another voltage dropping circuit 27 (for dropping the internal power source voltage V.sub.DD to a fixed voltage) is provided between the voltage output terminal 23 of the voltage dropping circuit 24 and the input terminal 25 of the voltage detecting circuit 26.

In this embodiment, the internal power source voltage V.sub.DD is so controlled as to be equal to the sum of the threshold voltage V.sub.TH of the voltage detecting circuit 26 and a voltage dropped .DELTA.V by the voltage dropping circuit 27. Since two factors are used to determine the internal power source voltage V.sub.DD in this embodiment, the accuracy of voltage V.sub.DD control is improved.

FIG. 9 illustrates a practical arrangement of the voltage dropping circuit 27 used in the FIG. 8 embodiment. As shown, the voltage dropping circuit 27 is composed of four series-connected diodes 115 to 118, and a resistor for feeding a current to those diodes. These diodes are used in dropping the voltage V.sub.DD applied to the anode of the diode group by .DELTA.V (=4 V.sub.F). Accordingly, voltage (V.sub.DD -.DELTA.V) is obtained at the cathode of the diode group. Voltage V.sub.F is the total forward voltage of the diodes 115 to 118.

FIG. 10 is a block diagram of a MIS semiconductor integrated circuit according to another embodiment of the present invention. As recalled, the FIG. 3 embodiment detects the voltage V.sub.DD at the predetermined threshold voltage V.sub.TH as set up in the voltage detecting circuit 26. The present embodiment employs a constant voltage circuit 28 and a voltage comparing circuit 29 to detect the internal power source voltage V.sub.DD. The internal power source voltage V.sub.DD obtained in the voltage dropping circuit 24 is applied to the internal circuit 30 and to the voltage comparing circuit 29. The constant voltage circuit 28 forms a constant voltage, using the voltage V.sub.CC supplied to the power source voltage terminal 40. The constant voltage so obtained is applied to the voltage comparing circuit 29. In this embodiment, the fixed voltage V.sub.DD is obtained in such a manner that the output voltage of the voltage comparing circuit 29 is supplied to the control terminal 21 of the voltage dropping circuit 24.

FIG. 11 shows a practical arrangement of the configuration of FIG. 10. As shown, the constant voltage circuit 28 consists of a load element 122 between a V.sub.CC supply node 120 and a V.sub.SS supply node 121, and a group of series-connected diodes 123. A fixed voltage V.sub.R appears at a node 124 between the load element 122 and the diode group. In this case, the number n of diodes in the constant voltage circuit 28 is so selected as to produce a fixed voltage V.sub.R, of e.g., 3 V, which is smaller than the magnitude (3.8 eV) of the potential barrier .phi.h shown in FIG. 2. The voltage comparing circuit 29 is made up of a differential amplifier 125 with inverting and noninverting input terminals, and an output terminal. The voltage dropping circuit 24, like the FIG. 4 embodiment is made up of an enhancement type P channel MOSFET 101.

The differential amplifier 125 may consist of a known MOS type circuit, as shown in FIG. 12. As illustrated in FIG. 12, an N channel MOSFET 131, serving as a constant current source, is connected at the source to a node 132 to which the voltage V.sub.SS is applied, and is supplied at the gate with a constant voltage. An N channel MOSFET 133, which is used for input, has a gate which serves as the inverting input terminal. Another N channel MOSFET 134, which is also used for input, has a gate which serves as the noninverting input terminal. The sources of MOSFETs 133 and 134 are connected to a drain of MOSFET 131. A P channel MOSFET 135 is used as the load. The drain and gate of this MOSFET 135 are interconnected. A node 136 between the drain and gate of the MOSFET 135 is connected to the drain of transistor 133. The source of the MOSFET 135 is connected to the node 137. Another load P channel MOSFET 138 is connected, at the gate, to the gate of MOSFET 135; at the drain, to the drain of MOSFET 134; and, at the source, to the node 137. A CMOS inverter 140 is connected, at the input terminal, to a node 139 on the common drain of MOSFETs 134 and 138. In the differential amplifier 125 thus arranged, when the gate input voltage V.sup.+ of MOSFET 134 is lower than the gate input voltage V.sup.- of MOSFET 133, the output terminal (i.e., the output terminal of the CMOS inverter 140) is low in level. On the other hand, when the gate input voltage V.sup.+ of MOSFET 134 is higher than the gate input voltage V.sup.- of MOSFET 133, the output terminal is high in (i.e., is at the V.sub.CC level). A fixed voltage V.sub.R is applied as the gate input voltage V.sup.- of MOSFET 133. The internal power source voltage V.sub.DD is used as the gate input voltage V.sup.+ of MOSFET 134.

In the FIG. 11 circuit, when the internal power source voltage V.sub.DD applied to the differential amplifier 125 is lower than the constant voltage V.sub.R, the output of the differential amplifier 125 is low, so that the P channel MOSFET 101 for voltage dropping is turned on. Accordingly, in this case, the internal power source voltage V.sub.DD gradually rises, as in the circuit of FIG. 4. When this voltage V.sub.DD is above voltage V.sub.R, the output of the differential amplifier 125 is high and MOSFET 101 is turned off. Thus, the voltage V.sub.DD gradually drops, as in the FIG. 4 circuit. Through this operation, the P channel MOSFET 101 is switch-controlled, so that the internal power source voltage V.sub.DD is so controlled as to be a constant voltage V.sub.R. Said constant voltage V.sub.R is invariable against a variation of the V.sub.CC. As may be seen from the results of our experiment, the internal power sources voltage V.sub.DD is not changed against a change from 3 to 8 V of the V.sub.CC, and a fixed voltage of 3 V can be obtained from voltage V.sub.CC. Further, the internal circuit 30 driven by such a stable fixed voltage V.sub.DD is fully protected from the effects of a high voltage, such as a spike voltage, and is also protected from the effects of noise.

FIG. 13 shows a modification of the FIG. 11 circuit. In this circuit, the voltage dropping circuit 24 is composed of an N channel MOSFET 106, as in the case of the FIG. 5 circuit. For this reason, the differential amplifier 125 is so wired that the constant voltage V.sub.R is applied to the noninverting input terminal, and the internal power source voltage V.sub.DD, is applied to the inverting input terminal. In this circuit, when voltage V.sub.DD is lower than the constant voltage V.sub.R, the output of the differential amplifier 125 is high, and MOSFET 106 is turned on. This results in an increase in the level of the V.sub.DD. When voltage V.sub.DD is higher than the constant voltage V.sub.R, the output of the differential amplifier 125 is low and the MOSFET 106 is cut off. In this way, a fixed and stable internal power source voltage V.sub.DD is obtained.

FIG. 14 shows another modification of the FIG. 11 circuit. The voltage dropping circuit 24 is composed of a PNP bipolar transistor 110, as in the case of the FIG. 6 circuit. The rest of the circuit arrangement is the same as the corresponding arrangement of FIG. 11. A fixed and stable voltage V.sub.DD appears at the collector of transistor 110.

FIG. 15 shows yet another modification of the FIG. 11 circuit. In this modification, the voltage dropping circuit 24 is made up of an NPN bipolar transistor 111, as in the case of FIG. 7. The rest of the circuit arrangement is the same as that of FIG. 13. A fixed and stable voltage V.sub.DD appears at the emitter of transistor 111, through an operation similar to that of the FIG. 11 circuit.

The constant voltage circuit 28 is shown in FIG. 10. The n diodes 123 are connected in series, as shown in FIG. 11, to thereby provide the fixed voltage V.sub.R. This voltage V.sub.R may be represented as n.multidot.V.sub.F, where V.sub.F is the forward voltage of each diode. The internal power source voltage V.sub.DD is so controlled as to be equal to the n.multidot.V.sub.F voltage (V.sub.R). The forward voltages V.sub.F of the diodes have potentially different values for the various fabricating processes of the diodes. If the forward voltage V.sub.F changes, the internal power source voltage V.sub.DD cannot keep its constancy. To cope with this problem; in the FIG. 16 circuit, which is another modification of the FIG. 11 circuit, the n fuses 126 are connected in parallel to their respective n diodes 123. With this arrangement, if the forward voltages V.sub.F of the diodes have a variation in their values during their manufacturing process, such a variation may be corrected by cutting the required number of fuses 126, to thereby sustain the consistancy of voltage V.sub.R. The operational voltage of the internal circuit 30 made up of MOSFETs differs, both as a result of its manufacturing process and its performance. The fuses 126 may be cut by a laser, for example, to be adapted to the operating voltage of the internal circuit 30. In the FIG. 16 circuit, the P channel MOSFET 101 is used as the voltage dropping circuit 24. This MOSFET 101 may be replaced by the N channel MOSFET 106 (FIG. 13) or the bipolar transistor (FIGS. 14 and 15). This method, wherein the fuses 126 are used and selectively cut at the programming stage, may be replaced by another method, wherein the parallel circuits (in which the fuses are located as in the former method) are set in a high impedance state at the initial stage, and are selectively set in a low impedance state at the programming stage.

FIG. 17 is a block diagram of a MIS semiconductor integrated circuit according to a further embodiment of the present invention. In this embodiment, two internal power source circuits 20A, 20B with different voltges V.sub.DD1, V.sub.DD2 are provided for use in driving the different portions of the internal circuit 30. One of the different voltages is set at a low value, to conserve on power consumption; while the other is set at a high value, to quicken the operating speed of the circuit.

As may be seen from the foregoing, according to the present invention, the voltage-dropped and fixed voltage, e.g., a voltage of 3 V, with a high current feeding potential, can be obtained in an on-chip manner against a substantial variation of, e.g., from 3 to 8 V. Under this voltage-dropped and fixed internal voltage, an internal circuit 30 containing MOSFETs with an effective channel length of 1 .mu.m or less operates. Therefore, the constraints on a power source voltage of from 1 to 5 V above, resulting from the further microfabrication of the MOSFETs, can be eliminated, to thereby provide MIS semiconductor integrated circuits free of the deterioration caused by the various circuit functions. The internal circuit 30 is thus operable under a fixed and stable internal power source voltage V.sub.DD, even if the externally supplied power source voltage V.sub.CC is varied. Therefore, performance factors of the internal circuit 30, such as operating speed and power dissipation are stable against variations of the externally supplied power source voltage V.sub.CC. Additionally, the internal circuit 30 is also stable against the effects of a spike voltage and/or noise. Accordingly, an integrated circuit containing MOSFETs with an effective channel length of 1 .mu.m or less can be operated by using the conventional the 5 V power source voltage as a standard power source. Further, the circuit according to the present invention is compatible with the TTL circuit. Moreover, low-voltage integrated circuits to be realized in the future might be driven by, e.g., a 3 V power source, while sustaining the same performance level as if driven by a 5 V power source.

While, in the above embodiments, the voltage dropping circuit 24 consists of a single MOSFET or bipolar transistor, a plurality of such transistors might also be used, in a parallel connection or a cascade connection. Moreover, the 3 V level of the internal power source voltage V.sub.DD might be reduced to 2 V or 1 V, upon a reduction of the effective channel length (0.5 .mu.m, 0.1 .mu.m) of the MOSFET used.