High Speed Analog-to-Digital Converter Having a Plurality of Comparison Cells Which in Successive Steps Determine the Four Most Significant Bits of the Conversion and Then the Four Least Significant Bits

The present invention relates to a high speed analog-to-digital converter.

Recent developments in the field of digital techniques for the processing of signals have increased interest for high speed conversion.

In particular the processing of signals in the video band creates the need of converters with a band width 10-50 Mhz and dynamic field of 8 bits.

An integrated approach for a digitization system requires the implementation, inside the conversion device itself, of several preprocessing functions.

In such sector the use is known of flash (or instantaneous) converters having one or two steps. In particular a single-step flash converter allows the use of conversion speeds of 120 Ms/sec (Megasamples per second) with bipolar technology and of 20 Ms/sec with CMOS technology. This approach does, however, have some drawbacks in terms of dissipated power, silicon area, high capacitative load at input.

Such drawbacks are overcome in part by using flash converters having two conversion steps. In this case the conversion operation provides for a first step of rough conversion of the sampled input signal, whereby there are obtained the four most significant bits of the signal at output, and a second step which receives at input a signal equal to the difference between the sampled input signal and the output signal of the first conversion step, reconverted to analog, and operates a fine conversion completing the digital output signal with the four least significant bits.

The use of such two-step conversion devices unfortunately requires conversion times which are longer with respect to the use of single-step converters. It is in fact necessary to execute two successive flash conversions, reconvert to analog the result of the first conversion operation and execute a subtraction before the second fine conversion step.

The object of the present invention is thus to accomplish an analog-to-digital converter with a very high conversion speed, around 50 Ms/sec in the CMOS technology, which has low input capacitance, low power dissipation and optimization of the silicon area used.

According to the invention such object is accomplished by means of a converter, characterized in that it comprises a plurality of comparison cells which in successive steps determine the four most significant bits of the conversion and then the four least significant bits after the more significant bits have been reconverted to analog and their subsequent subtraction from the input signal.

In particular each of said comparison cells is constituted by a comparator with the input connected to an intermediate branch point between two condensers in series, one of which is supplied in a first step with an input signal, in a second step with a first reference voltage different for each cell and in a third step with a selected reference voltage equal to that of said first reference voltages which approximates said input signal downwards with the highest accuracy, and by a second condenser which is grounded during said first and second steps, while during the third step it is connected to one respective of a plurality of second reference voltages submultiples of said first reference voltage.

In this way the result is obtained that a single group of comparators accomplishes both analog-to-digital conversion operations, the operation of intermediate digital-to-analog reconversion of the output signal from the first step of analog-to-digital conversion and that of subtraction of said signal reconverted to analog from the input signal, which in normal two-step flash converters are accomplished by two groups of comparators with a digital-to-analog converter and subtractor connected in between. There follow favourable results especially in terms of the speed of conversion, of the use of the silicon area and of power dissipation.

These and other features of the present invention shall be made evident by the following detailed description of an embodiment illustrated as an example in the enclosed drawing.

The FIGURE is a schematic diagram of the preferred embodiment of the present invention.

In detail, the converter comprises a plurality of comparison cells, in particular 15 in the case comparison is required to be executed in the 8-bit range. The generic comparison cell Cci comprises a comparator Cpi, of the type with one input only and with a digital output whose value depends on the variations of the input voltage, whose input is connected to an intermediate branch point Ni between two series condensers Ci and Ci', respectively.

The condenser Ci is in turn connected, on one side, to the branch point Ni and on the other side it communicates with a parallel of three different switches S1i, S2i, S3i, respectively, which are closed in temporal succession. In particular the switch S1i connects condenser Ci to an input voltage Vi, the switch S2i connects the condenser Ci to a reference voltage Vri forming part of a voltage divider P constituted by a series of resistances Ri, in the specific case 16, of equal value connected between a terminal supplying a voltage Vr and ground, and switch S3i connects condenser Ci to a supply line L1 which, by means of switch SWi, is connected to that among the different reference voltages Vri which is in turn selected by a coding logic LC sensitive to the outputs of comparators Cpi as that which approximates the input voltage Vi downwards with the highest accuracy.

Condenser Ci' is in turn connected, on one side, to the branch point Ni, and on the other side communicates with a parallel of two switches, S1i', S3i', respectively, of which S1i' grounds said condenser C1 and S3i' connects said condenser Ci' to a reference voltage Vri' forming part of a voltage divider P' constituted by a series of resistances Ri', in the specific case 16, of equal value connected between a terminal supplying a voltage Vr', where Vr'=Vr/16, and ground.

The input Ii of each comparator is also connected to the respective output Ui by means of a switch SS1i.

Due to the described structure the analog-to-digital converter operates as follows.

During a first step, switches S1i are closed and the value of the input voltage Vi is, memorized in condensers Ci. Switches SS1i also are closed to allow automatic cancellation of the offset at the terminals of comparator Cpi. During this step, condensers Ci' are grounded through switches S1i', closed simultaneously with switches S1i.

During a second step, switches S1i, S1i' and SS1i are open and switches S2i are closed so that the left-hand armature of the generic condenser Ci is brought to a respective reference voltage Vri. As a consequence while condenser Ci still memorizes the input voltage Vi, the voltage at the branch point Ni changes to a value (Vr - Vi) which according to the sign (+ or -) translates to a logic level 0 or 1 on the generic output Vi of comparator Cpi. There is thus operated a rough conversion of the input signal obtaining the 4 most significant bits of the digitalized signal Vi.

During a third step with switches S2i returned in open condition the coding logic LC, having detected the logic levels at the outputs of comparators Cpi, commands the closing of a selected switch SWi corresponding to the reference voltage Vri which best approximates the value of the four most significant bits of the input voltage Vi downwards thereby carrying out a reconversion of said four most significant bits into a corresponding analog signal. Switches S3i and S3i' are then closed to connect the condensers Ci to the selected reference voltage (Vrix) and condensers Ci' to respective reference voltage Vri'. As a consequence, the branch point Ni moves to a voltage Vi-Vrix, thereby subtracting a voltage corresponding to the analog conversion of the four most significant bits of the digital output signal from the input voltage Vi. According to whether Vi-Vrix is; lower or higher than the reference voltage Vri', the voltage at the branch point Ni translates to a logic level 0 or 1 on the generic output Ui, thus resulting into a" and delete "and allows the operation"; and allows the operation fine conversion giving the 4 least significant bits of the input signal Vi.