Analogue-to-Digital Converter

This invention relates to an analogue to digital converter.

An analogue to digital converter for converting an analogue input signal of narrow bandwidth to digital form based on a feedback arrangement is described in our UK patent application No., GB-A-8530669.

The present invention is concerned with an analogue to digital converter based on a feedforward arrangement which aims to achieve 16 bit resolution at a sampling frequency fs of at least 10 MHz.

According to the invention there is provided an analogue-to-digital converter comprising a first stage including means for producing a predicted signal in digital form of an analogue signal at its input, and means for determining a band limited error signal representing the difference between the predicted signal and the input signal by comparing them in analogue form; and a second stage comprising means for combining the error signal with the predicted signal to obtain a digital output signal. By "band limited" it is meant that the error signal bandwidth is less than half the sampling frequency. An analogue-to-digital converter in accordance with the invention does not require a sample and hold circuit at its input and therefore reduces the errors in sample amplitude which might occur because of jitter. It avoids instability difficulties experienced with previous arrangements and retains more of the signal in analogue form, band limited to less than half the sampling frequency fs. This optimises the linearity and noise performance. The invention may be applied to both converters having narrow bandwidth input signal and those to which wide bandwidth signals, up to approximately half the sampling frequency, are applied. In the case of a converter for narrowband signals, apparatus in accordance with the invention enables a lower cost digital- to- analogue converter to be used than with previous arrangements.

Preferably, the first stage includes a first signal path along which the analogue signal is transmitted to the said means for determining an error signal, and a second signal path which includes analogue-to-digital converter means followed by digital-to-analogue converter means, the predicted signal in digital form being passed to the second stage and the output of the digital-to-analogue converter means being applied to said means for determining a band limited error signal.

It is preferred that the second stage comprises a first signal path which includes analogue-to-digital conversion means to which the error signal is applied, and a second signal path along which the predicted signal in digital form is transmitted.

It is desirable that the error signal be made as small as possible so as to prevent overloading of components to which it is subsequently applied and in particular the analogue-to-digital converter means. The error signal will be minimised where matching between paths in the first stage is perfect. Advantageously therefore, there are included means for adding a pilot signal to the analogue signal at the input of the converter; means for monitoring the amplitude of the pilot signal present in the error signal; and means for using the result of the monitoring to improve phase and amplitude matching between signal paths in the first stage. It is also preferred that there are included means for adding a test signal to the predicted signal in digital form in the first stage, means for comparing the test signal taken from the second stage with the test signal passed along a signal path not included in the first and second stages, and means for using the result of the comparison to improve phase and amplitude matching between signal paths in the second stage. Advantageously, the characteristics of two paths followed by the test signal are substantially the same to enable suitable matching to be achieved. Matching between signal paths may be improved by applying phase and gain control to elements in the signal paths in dependence on the result obtained. Thus, preferably, means are included for controlling the clock phase and reference voltage of analogue-to-digital conversion means to improve matching between signal paths.

In one embodiment of the invention, it is preferred that delay means are included in the first stage via which the analogue input signal is transmitted to the means for determining the error signal. This is particularly applicable to wide band input signals.

For applications to signals occupying a bandwidth appreciably less than half the sampling frequency fs, it is preferred that digital filter means are included in the first stage to which the predicted signal in digital form is applied. This enables the prediction error to be minimised over a limited bandwidth without the need for a significant matching delay in the analogue signal path in the first stage. Advantageously, the output noise spectrum of the digital filter means is arranged to be shaped so as to include a null around the same limited passband. Advantageously, digital-to-analogue converter means is arranged to follow the digital filter means and has a resolution less than that of the analogue-to-digital converter means in the first stage and advantageously a resolution of only one bit.

Some ways in which the invention may be performed are now described by way of example, with reference to the accompanying drawings, in which:

FIGS. 1 and 2 are schematic block diagrams of an A-D converter in accordance with the invention; and

FIGS. 3 and 4 are schematic block diagrams of another converter in accordance with the invention.

FIG. 1 shows the basic arrangement of a converter in accordance with the invention which is suitable for use with wideband input signals. The arrangement is designed for a wideband signal which is retained in analogue form through a first stage so that no sample and hold circuit is required at the converter input. The quantised prediction of the input signal, although sampled during the quantisation process, is returned to analogue form before subtraction from the input signal. The subtractor thus only passes the band limited prediction error, which minimises the slew rate and hence aperture jitter requirements at the point of sampling in the second stage.

The prediction V.sub.p in the first stage is derived from the input signal V.sub.in via an 8 bit parallel (flash) A-D converter 1, sampled at the converter sampling rate fs and then passed to an 8-bit D-A converter 2 whose output is an analogue prediction signal V.sub.p with added quantisation noise Q.sub.p. The prediction error V.sub.pe is obtained by subtraction of the prediction V.sub.p from the input signal V.sub.in at a subtractor 3, the input signal V.sub.in being applied via a matching delay 4.

The prediction error V.sub.pe is passed through a low pass filter 5 and amplifier 6, sampled and quantised by an 8-bit parallel (flash) A-D converter 7 at the sampling frequency fs and is then added digitally at 8 to the quantised prediction V.sub.p obtained from the A-D converter 1 in the first stage via a digital filter 9 to provide the converter output V.sub.o. Matching of the two signal paths in the first stage is necessary to reduce the magnitude of the prediction error V.sub.pe to a level within the range of the second stage A-D converter 7, while matching of the second stage signal paths is necessary to suppress the quantisation distortion Q.sub.p introduced by the quantiser in the first stage. The error Q3 introduced by an imperfect D-A converter 2 however will not be suppressed by the second stage and so must be kept as small as possible and within the quantisation distortion Q2 of the second stage if the full resolution of the complete converter is to be realised.

FIG. 2 illustrates in greater detail the converter of FIG. 1 and shows the path matching control arrangement.

Small adjustments of the phase can be made by controlling the phase of the 8 bit parallel A-D converter clocks relative to the D-A clock and adjustment of the gain by adjustment of the A-D reference voltage. The control can be carried out by means of updating a register, up or down, followed by a low speed (CMOS) 8 bit D-A converter in each case. Monitoring of the error condition differs for the two stages but in each case involves monitoring the signal level appearing at the second stage A-D converter output.

Matching of the first stage is achieved by insertion at 10 of a pilot tone from a generator 11 at the input of the arrangement. The phase of the sampling clock to the first A-D converter 1 and its gain are adjusted to minimise the component of the pilot tone in the prediction error V.sub.pe. The pilot tone is at a level 20-30 dB below the maximum input capacity, and at a frequency near one edge of the system passband. The output from the second stage A-D 7 is sampled at 12 reducing the output to baseband. This is then filtered at 13 to a bandwidth of 500Hz or less to produce an indication of the amplitude of the component of the pilot tone present in the prediction error V.sub.pe. The amplitude of the detected tone produced by detector 13 is passed to a microprocessor controller 14 carrying out a `bridge balancing` control function to minimise the detected pilot level, via signals delivered to registers 15 which control the clock phase and gain of the A-D converters 1 and 7 via D-A converters 16. Should an input signal be present on the pilot tone frequency at a level in excess of the inserted pilot, the balancing mechanism can still operate and maintain cancellation at the pilot frequency.

Matching of the second stage is achieved by insertion of a digital test signal after the A-D converter 1 in the first stage and adjustment of the phase of the sampling clock to the second A-D converter 7 and its gain to minimise the component of the test signal appearing in the output signal V.sub.o. The test signal is inserted at a level no greater than the first stage A-D quantum step size. This signal will pass through the path formed by D-A converter 2, a lowpass filter 17, subtractor 3, filter 5, amplifier 6 and the second stage A-D converter 7 and the path formed by filter 9, to adder 8. These paths should be equal for matching of the second stage loop. The test signal is also passed through a separate path through filters 18 and 19 which impose an identical delay on the test signal as is included in the path through the second stage before correlation with the output from the second stage A-D converter in a correlator 20. This avoids the main input signal component present in the path through filter 9 which would make detection at adder 8 of the test signal component difficult. The correlator 20 produces baseband in-phase and quadrature components which are applied to detector 21.

The form of the test signal from generator 22 is a pseudo random modulated signal occupying the signal passband. Correlation of the two signal paths enables the detection of the test signal to be achieved without undue interference from the system input signal components, thereby avoiding the need to interrupt the input signal during calibration.

With reference to FIG. 3, another analogue-to-digital converter is illustrated which is suitable for use with input signals of narrow bandwidth. The first stage of the converter includes an A-D converter 23 followed by a filter 22 and D-A converter 25, the output of which is the prediction signal V.sub.p in analogue form. This is subtracted from the analogue input signal V.sub.in at subtractor 26. The analogue input signal is applied to subtractor 26 via a delay 27 which is used to provide matching between the two paths in the first stage. The filter 24 and D-A converter 25 may be such that only a small residual delay 27 need be included and it may be that the delay 27 could be omitted altogether.

The digital filter 24 is chosen to minimise the prediction error V.sub.pe over a sufficiently wide bandwidth and in this example uses a combination of two and four sample period delays.

The digital to analogue converter 25 requires a resolution equal to that of the prediction A-D converter 23, i.e. 8 bits, with at least sixteen bit accuracy of levels. However, the digital filter 24 can be chosen to introduce a shaping of the quantisation noise spectrum associated with an internal discarding of bits, giving a null at the quarter sampling frequency to permit a reduced resolution D-A converter 25 to be used (but still with at least 16 bit level accuracy). In the limit the D-A converter resolution can be reduced to a single bit i.e. a simple switch, which removes the requirement for 16 bit level accuracy although jitter and settling time requirements remain unchanged.

It may be advantageous to place a null at baseband in addition to or in place of the null at the quarter sampling frequency.

The error signal from the subtractor 26 is transmitted via a bandpass filter 28 and amplifier 29 to an A-D converter 30. The output of the A-D converter 30 is combined at 31 with the digital prediction signal taken from the output of filter 24 and applied to adder 31 via a filter 32.

FIG. 4 shows the converter of FIG. 3 in greater detail and illustrates the matching arrangement which is similar to that of the converter shown in FIGS. 1 and 2. A bandpass filter 33 is arranged to follow the D-A converter 25 and removes out-of-band components and quantising noise produced by the D-A converter 25, so presenting the subtractor 26 with a clean band limited prediction of the input signal containing only the in band quantising noise. A matching filter 34 in the input signal path is included to assist phase and amplitude matching prior to subtraction at 26 and also to limit the amplitude of V.sub.pe for large out of band input signals. Again, the filter 28 provides further filtering to prevent overloading of amplifier 29 and the second A-D 30.