US 5,023,543 AGrant
Temperature Compensated Voltage Regulator and Reference Circuit
Issue Date:1991-06-11
•15 Claims
•2 Drawing Sheets
Abstract
The temperature compensated reference circuit has a first common emitter BJT whose base is connected to a first JFET current source and through a JFET resistor to a voltage output. The JFET resistor is biased in the linear region and the JFET current source is biased in the saturation region in an operating condition. The voltage across the JFET resistor is selected to be approximately equal to the pinch-off voltage of the JFET current source. The temperature co-efficient of the first BJT and JFET resistor will cancel one another to produce a generally temperature invariant voltage at the output. The voltage regulator incorporates the reference circuit and has a second BJT current source driving the reference circuit. A feedback system includes a second JFET current source between the collector of the first BJT and the connection between the voltage output and the collector of the second BJT. The second JFET current source drives the base of a common emitter third BJT. The collector of the third BJT is connected through a resistor to the base of the second BJT. The feedback system regulates the amount of current necessary to drive the reference circuit and the load.
Metadata
Assignee
- Gennum Corporation
Inventor
- Lawrence T. Tse
Application Information
Application Number:US 4079930
Filing Date:1989-09-15
Priority Date:1989-09-15
Art Unit:212
Classifications
IPC:
G05F 320
Field of Search:
323307311;312;313;314;907296.1;296.6;296.7
Patent Drawings (2 sheets)
Description
Field of the Invention
This invention relates to voltage regulators and to voltage reference circuits. More particularly, it relates to temperature compensation in regulators and reference circuits.
Background of the Invention
Temperature compensation of voltage regulators has long been a problem. The reference voltage of regulators has typically been produced by adding a BJT base emitter junction voltage (VBE) to another derived voltage which is proportional to absolute temperature (PTAT). The simplest implementation of this method to achieve zero temperature co-efficient (ZTC) produces a reference voltage of 1.26 volts which is the popular bandgap voltage. With an adequate supply voltage and additional amplification circuitry this reference can be multiplied up or divided down to produce any value of regulated ZTC voltage.
These circuits however are not suitable for low supply voltage operation (1.3 volts or less) which is often required in battery operated circuits as there is not enough voltage to operate the simple band gap reference let alone the amplification circuitry required for regulation. In order to overcome this problem complicated circuitry has been used to implement essentially the same idea. This is accomplished by combining the right proportions of a VBE to produce some desired ZTC reference voltage which is less than the bandgap voltage.
Summary of the Invention
In a first aspect the invention provides a voltage reference circuit, having a voltage output, the circuit comprising: a Bipolar Junction Transistor (BJT) having a common emitter; a Junction Field Effect Transistor (JFET) current source having a given pinch-off voltage; and a JFET resistor; wherein, the current source is connected to the base of the BJT, the JFET resistor is connected between the voltage output and the base of the BJT, and the JFET resistor is selected to produce a voltage approximately equal to the pinch-off voltage of the current source when the circuit is biased in an operating condition.
In a second aspect the invention provides a voltage regulator, having a voltage output, the regulator comprising:
a first current source;
a first BJT having a common emitter;
a JFET second current source; and
a JFET resistor wherein, the second current source is connected to the base of the first BJT, the JFET resistor is connected between the voltage output and the base of the first BJT, the first current source is connected to the voltage output, the first current source drives the collector of the first BJT, and the JFET resistor is selected to produce a voltage approximately equal to the pinch-off voltage of the second current source when the circuit is biased in an operating condition.
Brief Description of the Drawings
For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example to the accompanying drawings, which show a preferred embodiment of the present invention, and in which:
FIG. 1 is a schematic diagram of a voltage regulator according to the preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of the regulator of FIG. 1 employing a feed back network;
FIG. 3 is a circuit diagram of a voltage reference circuit employed in the regulators of FIG. 1 and FIG. 2; and
FIG. 4 is a circuit diagram of a regulator according to FIG. 2.
Detailed Description of the Preferred Embodiment
Referring to FIG. 1 a voltage regulator 1 has an unregulated power supply voltage V.sub.cc connected through a current source I.sub.s1 and a reference voltage circuit V.sub.R to ground. A voltage output V.sub.o is connected between the current source I.sub.s1 and the voltage reference V.sub.R.
In operation, the voltage reference circuit V.sub.R produces a regulated voltage at the output V.sub.o. The voltage reference circuit V.sub.R and a load R.sub.L connected to the output V.sub.o are driven by the current source I.sub.s1. The load R.sub.L sees the substantially constant voltage of V.sub.R.
A fixed current source I.sub.s1 will not drive V.sub.R with a substantially constant current when the load R.sub.L varies substantially in the amount of current it draws. In FIG. 2 a feedback network 3 has been connected between V.sub.o and a current input 5 to I.sub.s1. I.sub.s1 is now a variable current source.
In operation, I.sub.s1 senses the amount of current being drawn by the load R.sub.L at V.sub.o and draws current from the feedback network 3 through the input 5 to produce the required amount of current at R.sub.L. It is not absolutely necessary that the feedback network 3 draw current from V.sub.o, however the inventor has found this to be the most convenient way of providing the additional current. Other methods would likely require a greater number of components.
Referring to FIG. 3, V.sub.R is made up of a BJT Q.sub.3, a junction field effect transistor (JFET) resistor R.sub.j and a JFET current source I.sub.s2. The resistor R.sub.j is connected between V.sub.o and the base of Q.sub.3. The current source I.sub.s2 is connected between the base of Q.sub.3 and ground. Q.sub.3 is an NPN BJT with its emitter connected to ground.
In operation, the collector of Q.sub.3 would be connected to a current source such as I.sub.s1 of FIGS. 1 and 2. The voltage across R.sub.j should be less than twice the square root of 2 times its pinch-off voltage V.sub.p. However this limitation is only dependant on the number of series JFET used to make up this resistor. The current source I.sub.s2 should be operated in the saturation region. Q.sub.3 is biased in the active region therefore most of the current I.sub.s2 goes through the resistor R.sub.j. As long as substantially all of I.sub.s2 flows through R.sub.j the resulting voltage developed will be proportional to V.sub.p. The temperature coefficient of V.sub.p for a typical silicon JFET is approximately 2 mV/.degree.C. and the temperature co-efficient of the base-emitter voltage (V.sub.be) of a typical BJT is approximately -2 mV/.degree.C.
V.sub.o, the voltage across V.sub.R, is equal to the V.sub.be of Q.sub.3 plus V.sub.rj. When R.sub.j is selected to produce a voltage approximately equal to the V.sub.p of I.sub.s2 then the temperature co-efficient of V.sub.rj will be approximately 2 mV/.degree.C. The temperature co-efficients of Q.sub.3 (-2 mV/.degree.C.) and V.sub.rj (+2 mV/.degree.C.) will cancel to produce a substantially steady voltage with respect to temperature at V.sub.o.
The -2 mV/.degree.C. temperature co-efficient of Q.sub.3 is for a typical silicon BJT. For other materials such as gallium-arsenide the temperature co-efficient will be different. This will affect the desired value of V.sub.p. As V.sub.p is inversely related to the doping of a JFET, the doping of the current source of I.sub.s2 could be altered to achieve the desired value of V.sub.p.
It is not strictly necessary that R.sub.j be a JFET resistor however these resistors are preferred as their values are predominantly dependent upon size and the relationship between I.sub.s2 and R.sub.j can be well defined when both are implemented using JFET's.
Referring to FIG. 4, the feedback network 3 of FIG. 2 has been included in detail. The feedback network 3, outlined in single dot chain line, is made up of a current source connected JFET J.sub.1, a BJT Q.sub.2 and a resistor R.sub.1. The current controlled current source I.sub.s1 has been implemented using a BJT Q.sub.1. Q.sub.1 is a PNP transistor with its emitter connected to V.sub.cc and its collector connected to V.sub.o. The base of Q.sub.1 is connected through R.sub.1 to the collector of Q.sub.2. The base of Q.sub.1 is the input 5 to I.sub.s1 of FIG. 2. Q.sub.2 is an NPN transistor. The emitter of Q.sub.2 is connected to ground while its base is connected between the drain of J.sub.1 and the collector of Q.sub.3. The gate and source of J.sub.1 are connected to the collector of Q.sub.1 and to V.sub.o. The current source I.sub.s2 has been implemented using a current source configured P-channel JFET J.sub.2.
In operation, a load R.sub.L connected to V.sub.o will increase the current following through Q.sub.1. This will increase the current in the base of Q.sub.1 flowing through R.sub.1 into the collector of Q.sub.2. Q.sub.2 acts as a variable current source drawing base current from J.sub.1. The current drawn from J.sub.1 will not substantially affect the V.sub.be of Q.sub.3 as the collector of Q.sub.3 has a very high impedance and the current drawn away is quite small.
The JFET J.sub.1 provides fairly constant current to Q.sub.3 and provides a voltage separation between the V.sub.be of Q.sub.2 and V.sub.o.
The regulator 1 and the reference circuit V.sub.R when employing silicon components are capable of operating at V.sub.o voltages down to approximately 0.9 volts. Such a voltage is obtainable using a JFET J.sub.2 having a V.sub.p of approximately 0.3 volts, and a BJT Q.sub.3 having a Vbe of approximately 0.6 volts in the active region.
Another important advantage of the regulator 1 and reference circuit V.sub.R made according to the preferred embodiment of the present invention is they may be implemented using fewer components then previously used in known circuits.
As well, the reference circuit V.sub.R can be configured to work equally well with reference voltages other than 0.9 volts. This technique can be extended to higher voltage applications as will be evident to those skilled in the art.
Resistor R1 functions to limit the base current of Q.sub.1 thus providing short circuit protection.
It will be evident to those skilled in the art that there are other embodiments of the invention falling within its spirit and scope as defined by the following claims. Such embodiments would include complementary circuits employing reversed doping layers, such as NPN for PNP, with minor consequential amendments to the circuit configurations.
Claims
I claim:
1. A voltage reference circuit, having a voltage output, the circuit comprising: a Bipolar Junction Transistor (BJT) having a common emitter; a Junction Field Effect Transistor (JFET) current source having a given pinch-off voltage; and a JFET resistor; wherein, the current source is connected to the base of the BJT, the JFET resistor is connected between the voltage output and the base of the BJT, and the JFET resistor is selected to produce a voltage approximately equal to the pinch-off voltage of the current source when the circuit is biased in an operating condition.
2. A voltage reference circuit according to claim 1, wherein the JFET resistor is biased in the linear region in the operating condition.
3. A voltage reference circuit according to claim 2, wherein the current source is biased in the saturation region in the operating condition.
4. A voltage reference circuit according to claim 3, wherein the BJT, current source and resistor are formed substantially from silicon.
5. A voltage reference circuit according to claim 3, wherein the BJT is an NPN BJT and the current source is a p-channel JFET.
6. A voltage regulator, having a voltage output, the regulator comprising: a first current source; a first BJT having a common emitter; a JFET second current source; and a JFET resistor wherein, the second current source is connected to the base of the first BJT, the JFET resistor is connected between the voltage output and the base of the first BJT, the first current source is connected to the voltage output, the first current source drives the collector of the first BJT, and the JFET resistor is selected to produce a voltage approximately equal to the pinch-off voltage of the second current source when the circuit is biased in an operating condition.
7. A voltage regulator according to claim 6, wherein the JFET resistor is biased in the linear region in the operating condition.
8. A voltage regulator according to claim 7, wherein the second current source is biased in the saturation region in the operating condition.
9. A voltage regulator according to claim 8, wherein the first current source is variable and has a current input, the regulator further comprising, a feedback network connected to the control current input.
10. A voltage regulator according to claim 9, wherein the first current source is a common emitter second BJT with its collector providing the connection to the voltage output and driving the collector of the first BJT, and its base being the control current input.
11. A voltage regulator according to claim 10, wherein the feedback network comprises, a variable third current source connected to the current input.
12. A voltage regulator according to claim 11, wherein the feedback network further comprises a voltage buffer, and wherein the third current source is a common emitter third BJT, the base of the third BJT being connected to the collector of the first BJT, the collector of the third BJT being connected to the current input, and the voltage buffer being connected between the collector of the second BJT and the collector of the first BJT.
13. A voltage regulator according to claim 12, wherein the voltage buffer comprises, a current source connected second JFET.
14. A voltage regulator according to claim 13, wherein the feedback network further comprises, a second resistor between the current input and the collector of the third BJT.
15. A voltage regulator according to claim 14, wherein the first and third BJTs are NPN, the second BJT is PNP, and the first and second JFETs are p-channel.