Process for Forming Planarized Films

FIG. 1 is a schematic illustration of a PECVD system suitable for forming planarization layers in accordance with the invention.

FIGS. 2(a) and 2(b) are schematic cross-sectional views showing a planarization layer system for forming a contact and via hole.

FIGS. 3(a) and 3(b) are is a schematic cross-sectional views showing a planarization layer removed after contact formation 3(a and left in the the circuit as a dielectric layer 3(b).

FIGS. 4(a),(b), and 4(c) are is a schematic cross-sectional views showing steps 4(a), 4(b), and 4(c) in forming a planarization layer over a conformal layer.

FIGS. 5(a), 5(b), and 5(c) are is a schematic cross-sectional views showing formation of a planarization layer for interconnection between circuits.

FIGS. 6(a) and 6(b) are is a schematic cross-sectional views of self-developed planarization process.

FIG. 1 illustrates in schematic form a PECVD system 10 for use in the planarization process of the invention. The system comprises, in general, a vertical PECVD chamber 12, R.F. power sources 14 and 15 coupled across upper and lower electrodes 16 and 18, vacuum pumps 20 and a source 22 of reactant gases coupled to the chamber 12. The source 22 also includes a means for mixing gases and controlling the flow rate.

Substrate samples 24, having a corrugated profile 26, are disposed on one electrode, for example, the lower electrode 18. The electrode 18, upon which the sample 24 is disposed for planarization, is brought to a suitable temperature by heating/cooling unit 26 located in close proximity to electrode 18 and electrically controlled by temperature control unit 28. Unit 28 may comprise a resistance heater and/or a fluid cooler. Gasses are introduced from source 22 via port 30 in communication with shower head 29 on electrode 16.

A bellows 36 is provided to mechanically adjust the spacing between electrodes and, hence, controlling confinement of the plasma 40. Throttle valve 34 controls the pressure in the chamber 12 and an optical thickness monitor is provided to observe the thickness of the deposited planarization film 25.

The parameters that control the film characteristics include gas composition, gas flow rate, R.F. power, pressure and temperature.

A typical condition used for deposition is the following: Benzene (C6H6) is used as the source gas flowing at a rate of 50 sccm. The pressure is maintained at 750 mTorr by valve 34; with 50 W R.F. power applied to the top electrode 16 from R.F. source 14. Note: R.F. source 15 is not energized in this example and electrode 18 is grounded. The addition source 15 is provided for flexibility in the event it is desired to power the bottom or both electrodes simultaneously. The sample 24 is placed on the bottom electrode 18 with sample temperature maintained at 30.degree. C. The resultant deposition rate is 230 nm/min and the film 26 is liquid-like and planar over 1 to 1 micron deep steps 26. Other gases used that provide planarized films include toluene (CH3-CH6H5); butadiene (C4H6); hexamethyldisilazane (HMDS--(CH3)6 Si-HN-Si); and L HMDS/Xylene [ (CH3)2--C6H4]mixture. To obtain soft films that flow over steps, it is desirable to use low R.F. power (less than 150W), high pressure (more than 500 mTorr), high gas flow rate (more than 10 sccm), and low temperature (less than 100.degree. C.).

In addition, the process works best when the source gases are in liquid phase at room temperature, but have high vapor pressure to maintain high flow and high pressure during deposition. Alternatively, the gas line could be heated to maintain high vapor pressure. (For comparison, a vapor pressure of 40 Torr is achieved for the following gases at the temperature indicated, C4H6---61.degree. C.; C6H6--8.degree. C.; C6H5-CH3-32.degree. C.; C6H4-(CH3)2--60.degree. C.; C8H8--60.degree. C.; HMDS--20 Torr at room temperature).

The deposition rate depends on the gas composition, is directly proportional to gas flow rate, power and pressure, and inversely proportional to temperature.

The hardness of the deposited film can also be modified by the addition of other gases, such as N2, N20, H2, NH3, SiH4, and Ar. The film remains soft and planar over steps when N2 or N20 are added. However, as H2, NH3 or Ar is mixed with the hydrocarbon source gas, the film becomes hard and conformal. It appears that inert gases or hydrogen radicals tend to harden the films by either causing more dissociation in the gas phase or reacting on the film surface.

Depending on the deposition conditions, the films can be soft and liquid-like, or hard and conformal. The soft films form a planar surface over corrugated features. For example, better than 95% planarization can be obtained using 1-micron-thick film for 20-micron-wide, can be dissolved in organic solvents, such as trichloroethane and chlorobenzene. The hard, conformal films are less reactive to the organic solvents and some are not soluble. Both the hard and soft amorphous carbon films can be easily patterned using oxygen reactive ion etching (RIE) at an etch rate of about 50 nm/min with better than 200 to 1 selectivity for inorganic masks (Ni, Al, Si).

The films deposited using gases, such as HMDS, or HMDS/Xylene mixture which contain Si the resultant films, contain 5 to 95% Si, depending on the deposition conditions. Because of the Si contents in these films, the etch rate in O2 RIE varies. There is insignificant etching (less than 1 nm/min) for films with more than 10% Si. These films can be used as an imaging layer and act as a good RIE mask. For films with low Si contents, they can still be easily patterned by RIE in O2 with F/Cl gas mixture. For example, HMDS films with 10% Si can be etched in 02/CF4 (1:3) RIE with an etch rate of 50 nm/min and better than 200 to 1 selectivity for metallic RIE masks (Ni, Al).

The soft and liquid-like films can be hardened by in-situ, thermal, or plasma treatment. The in-situ treatment can be applied during the deposition process where layers of soft films are deposited with hardening steps in between each layer. The deposited films will be planar and hard and no further hardening step is necessary. Without in-situ hardening, the films can still be hardened in the same deposition chamber or in a different chamber after deposition. Typical thermal treatment involve annealing the samples in N2 for 15 minutes at 120.degree. C. The annealing ambient (N2, H2, Ar) does not make a substantial difference in the hardness of the films. Annealing in O2 at temperature greater than 200.degree. C. tends to react with the film and reduce the film thickness. The higher the temperature and the longer the annealing time, the harder the film will be. Hardening can also be accomplished by exposing the soft films to plasma with low ion energy. N2 plasma gives the best result in surface morphology, although other plasma, such as H2 and O2, also works. Typically, the soft films are placed in an N2 plasma with 10 V dc bias voltage at 500 mTorr, 100.degree. C. for 5 minutes. The plasma seems to allow hardening to be achieved at lower temperature and shorter time.

Because soft films can be self-developed by exposure to deep UV light (250 nm), at a rate of 10 nm/min, the conventional image layer and pattern transfer steps required in the other planarization processes may be eliminated as shown in FIG. 6. After forming a planarization layer 56 over a dielectric patterned substrate 50 (FIG. 6a), openings 92 may be formed directly through the soft layer by exposing the layer to light through a conventional mask set 90. The self-development rate decreases to half after the soft films were annealed at 100.degree. C. for 15 minutes.

Experimental tests were conducted, in accordance with the invention, and the conditions and results are tabulated in Tables I and II below:

Referring now to FIG. 2, a typical application for the planarization film will now be described. In VLSI processing, it is often necessary to isolate regions of a Si wafer with a dielectric and to form contact openings and via holes through the dielectric for metallization. A dielectric insulator layer of SiO.sub.2 or Si.sub.3 N.sub.4 is first formed by known processes on the Si wafer 50 and patterned to expose the Si wafer surface 52 where the contact is to be made; leaving a corrugated or step-like dielectric structure 54. This structure may be planarized by a layer 56 formed, as described above, in a PECVD chamber at low temperature. The composition of layer 56 varies, depending upon whether the layer 56 is to be a removable sacrificial layer, or will stay as an insulator. In the former case, an amorphous carbon layer is formed, while in the latter case, a silicon containing carbon layer is required.

A conventional image layer 58 of of Si/Ni/Al is then deposited, preferably in the same chamber, by PECVD, on the smooth planar surface of layer 56, and lithographic techniques used to etch contact openings 60 or vias to the substrate surface.

FIG. 3 illustrates another application for the invention in which the planarization layer 56 may be either removed, as in FIG. 3a, or left, as in FIG. 3b. Thus, in FIG. 3a, the layer 56 is removed by a solvent after the metal contacts 62 were formed in the contact openings. Whereas, in FIG. 3b, the planarization layer 56 is left to form an insulator upon which a second metal layer (64) may be formed.

FIG. 4 shows the steps in forming a planarization layer 56' over a conformal layer 70. In this process, typically a metallized pattern 74 is formed on a silicon wafer and conformally coated, either conventionally, or using the hard coating PECVD process, to produce a dielectric layer 70 with a non-planar surface 72. Planarization layer 56' is formed over the layer 70, as described above. An image layer 58' is then deposited on layer 56' and patterned. The patterned openings are etched, as shown in FIG. 4b, to expose the underlying metal conductors 74. The image layer and planarization layer 56' are then dissolved and a second metal layer 76 formed over and through the conformal dielectric layer 70.

FIG. 5 shows yet another application for the invention wherein hybrid circuits 80 may be interconnected with the aid of a planarization layer 56. Hybrid circuits 80 are affixed to a common substrate, such as Si wafer 50, and a layer 56 formed over the non-planar structure, as described above, along with an image layer 58, preferably formed in the PECVD chamber (FIG. 5a). Note: It is also possible to form the layer 58 by other processes, such as E-beam evaporation, CVD, MBE, etc. The image layer may be patterned by any of the well-known processes, such as laser patterning, UV lithography, E-beam lithography, ion beam or X-ray lithography.

Vias 90 are formed by RIE using the image layer as a mask; and metal lines 92 are formed by using the CVD process at low temperature with gases, such as WF6 or Al(CH3)3.

In summary, we have achieved better than 95% planarization using films deposited by PECVD. This process has advantages over other conventional planarization techniques. The process is carried out at low temperature (20.degree. C.) without bombardment by high energy ions. Since it does not require etching (back sputtering) of the deposited films (as needed in sputter deposit film), deposition rate is as high as 250 nm/min.

In addition, a high degree of planarization is obtained using a thin layer with thickness equal to the step height of the underlying profile. The fast deposition rate and thin layer needed can provide high wafer throughput. In comparison to spun-on layers using wet chemical, since no spinning is required, better uniformity and better planarization over large features are obtained.

While the process has been described in connection with VLSI circuits using Si wafers, it should be understood that other materials, such as III-V semiconductors, may be adapted for use in the process.

The R.F. power used for the deposition process can be converted to R.F. power density by simply dividing the power by the area of the electrode. In the experiments referenced, the area of the electrodes was about 500 cm.sup.2 and the R.F. power typically used is less than 150 W, which is equivalent to 0.3 w/cm.sup.2.

Some of the as-deposited planarization films do not have the desired electrical properties required as dielectric layers. Films containing relatively small C content and Si, N or 0, can be converted to good dielectric layers by further treatment after deposition. For example, the C in the film can be removed by thermal or plasma treatment in an 02 of N2 ambient.

Accordingly, the invention is not to be limited, except as defined in the following claims: