Method for Making a BiCMOS Semiconductor Device

This invention relates to a method for making a semiconductor device, and more particularly to an improved method for making on a single semiconductor chip a semiconductor device having bipolar transistors, CMOS transistors, MOS capacitors and resistors formed on a single-crystal silicon semiconductor substrate.

A semiconductor device having bipolar transistors and CMOS transistors on a single semiconductor substrate, is generally called a BiCMOS device. VLSI-class BiCMOS technology of a prior art is mainly suitable for use in high-integration and high-speed logic or memory devices because it has been primarily developed for such objects. The BiCMOS technology of prior art for high-performance memory and logic devices has been disclosed in ISSCC Digest of Technical Papers, page 212, February 1986 and in CICC Technical Digest, page 68, May 1986, respectively. In achieving high-performance digital and analog VLSI devices on a single chip with the prior art, there are often limits in the performance and application because there are not optimized and prepared therein for MOS elements, bipolar elements, resistors and capacitors to simultaneously perform precise analog functions and high-speed, high-integration digital functions. In the meanwhile, the influence that the interface between single-crystal emitter region and polycrystalline silicon in a polycrystalline silicon emitter bipolar transistor element has upon the characteristic of elements and circuits, has been disclosed in IEEE, ED-34 NO. 6, PP 1346-1353, June 1987 and in Symposium VLSI Technical Digest papers, PP 47-48, May 1986.

It is therefore an object of this invention to provide with less processing steps a method for making a BiCMOS semiconductor device which can be used both in high-integration, high-speed digital devices and in precise analog devices by forming within a single substrate a CMOS transistor, a metal contact emitter bipolar transistor having the high load driving power and highly effective matching characteristics, and a polycrystalline silicon emitter bipolar transistor having a high-speed characteristic at a low current level.

It is another object of the invention to provide a method for making a BiCMOS semiconductor device capable of obtaining the most effective elements with the least processing steps by means of forming MOS capacitors and resistors on a single semiconductor chip including the MOS and bipolar transistors, and therein making their inter-connections effective.

The above objects, advantages and features of the present invention will become more readily apparent from a review of the following specification when taken in conjunction with the drawings:

FIGS. 1(A)-(T) and 1(A')-(T') are cross-sectional views sequentially illustrating the processing steps of a preferred embodiment according to this invention;

FIG. 2 is a final cross-sectional view of a device completely fabricated according to this invention;

FIG. 3 is a final cross-sectional view of an active element portion in another preferred embodiment according to this invention; and

FIGS. 4(N) through 4(T) are cross-sectional views illustrating the process steps of another preferred embodiment according to this invention.

Hereinafter, a preferred embodiment of this invention will be described in detail with reference to the drawings. FIGS. 1(A) to 1(T) and FIGS. 1(A') to 1(T') are cross-sectional views sequentially illustrating the process steps for manufacturing a BiCMOS device according to this invention. It should be noted that each processing step through said FIGS. 1(A) to 1(T) and 1(A') to 1(T') illustrates a single successive process carried out on a single substrate, respectively in pairs.

Referring to FIGS. 1(A) and 1(A'), after coating a silicon oxide layer 2 for masking on the whole substrate surface of P-type single crystal silicon substrate 1 with <100> orientation and resistivity of 2-20 .OMEGA..Cm by means of a conventional oxidation process, a first photoresist layer 3 is deposited on the oxide layer 2, and windows 4, 5 and 6 are made by a conventional photolithographic technique in order to form the substrate region (or well) of PMOS transistor and the collector regions of polycrystalline silicon emitter NPN transistor and of metal contact emitter NPN transistor. Then there are formed N-type ion-implanted regions 7, 8 and 9 by means of ion implantation of group V impurity such as phosphorus (P) with an energy of about 160 KeV and a dose of 10.sup.12 -10.sup.14 ions/cm.sup.2. After that, as shown in FIGS. 1(B) and 1(B'), the photoresist 3 used as a mask in performing the ion implantation of group V impurity such as phosphorus is removed, and there are formed a N-type first substrate region 10, a N-type third substrate region 11 and a N-type fourth substrate region 12 having a depth of about 2.5 .mu.m by means of activating and diffusing said N-type ion-implanted regions 7, 8 and 9 under the atmosphere of oxygen and nitrogen at a temperature between 1000.degree. C. and 1200.degree. C. The substrate region 1 between said first substrate region 10 and said third substrate region 11 may be a second substrate region so that a NMOS transistor will be formed in the subsequent process. Thereafter, upon removing all the oxide layer 2 on said substrate 1, an oxide layer 13 having the thickness of 500 .ANG. is deposited on the surface of substrate 1, and a nitride layer 14 of Si.sub.3 N.sub.4 having a thickness of 1500 .ANG. is deposited on the oxide layer 13 by a conventional Low Pressure CVD (Chemical Vapor Deposition). The masking layer consisting of said oxide layer 13 and said nitride layer 14 is used to prevent the oxidation of silicon on the substrate surface 1 below said masking layer during the following oxidation process. A second photoresist 15 is coated on the masking layers 13, 14 by a conventional method. Photoresist 15 covers a connecting region 100 and a region 101 on the first substrate region 10 to be formed into a PMOS FET, a connecting region 103 and a region 102 on the second substrate region to be formed into a NMOS FET, regions 104 and 105 to be formed into NPN transistors, a MOS capacitor region 106, a resistor region 107 and a connecting region 108.

After etching the exposed nitride layer not covered with the mask in the nitride layer 14 shown in FIGS. 1(C) and 1(C') by means of employing the second photoresist 15 as an etching mask, said second photoresist is removed. In order to electrically isolate each of the elements, a third photoresist 16 is then deposited as shown in FIGS. 1(D) and 1(D'). After forming a P-type ion-implanted region 17 by performing ion implantation of a group III impurity such as boron with a low energy of about 30 KeV and a dose of 10.sup.12 -10.sup.14 ions/cm.sup.2, the third photoresist 16 is removed, and then there is formed a second oxide layer 18 as shown in FIGS. 1(E) and 1(E'). In this oxidation process, an oxide layer is not grown on a silicon substrate below the masking layers 13, 14 but grown on a region of silicon substrate not protected by said masking layers 13, 14. In addition said ion-implanted region 17 is activated, as shown in FIGS. 1(E) and 1(E'), so that there is formed a high concentration P+ channel stopper 19 for preventing the channel between elements for forming thereon. After growing the second oxide layer 18 with the previous process, the nitride layer 14 is removed by a conventional etching method without a mask, and a sacrificial oxide layer 20 is formed through a process of thermal sacrificial oxidation to purify the substrate surface. Thereafter, a fourth photoresist 21 is deposited to form a MOS capacitor as a passive element as shown in FIGS. 1(G) and 1(G'). After forming a N-type ion implanted region 22 by means of performing ion implantation of a group V impurity such as Arsenic (As) in a dose of 10.sup.15 -10.sup.16 ions/cm.sup.2 in the MOS capacitor region 109, the photoresist 21 is removed. Then, by etching the thin oxide layer 20 over the substrate without use of a mask by means of HF solution, the second oxide layer 18 becomes a new oxide layer which is etched in the thickness of said thin oxide layer 20, and the remaining part of the substrate thereon coated with said second oxide layer is exposed. Thereafter there is deposited an oxide layer 23 with a thickness of 200-500 .ANG. on the exposed substrate for the formation of a gate oxide layer of the MOS element and the dielectric of a capacitor, as shown in FIGS. 1(H) and 1(H'), by a conventional thermal oxidation process. At this time, in the process shown in FIGS. 1(G) and 1(G'), the ion-implanted region 22 is activated to form an electrode region 24 for a MOS capacitor as shown in FIG. 1(H'). After that, in order to control the threshold voltages of NMOS and PMOS FET's, there is performed ion implantation of a group III impurity such as boron (B) with an energy of about 30 KeV and a dose of 10.sup.11 -10.sup.13 ions/cm.sup.2 into the whole silicon substrate. After there is formed a first polycrystalline silicon layer 25, which is employed as gate electrode material and connecting element material of MOS transistors, and electrode plate material with a constant area over the dielectric of the capacitor, on the whole silicon substrate by a conventional method, the group V impurities such as Phosphorus(P) are injected to lower the resistance of said first polycrystalline silicon layer 25. For example, the sheet resistance of the first polycrystalline silicon is about 20 .OMEGA./.quadrature. by way of POC13 at a temperature 900.degree. C. Thereafter, as shown in FIGS. 1(I) and 1(I'), a fifth photoresist 26 is coated to leave a polycrystalline silicon layer region 110 over a gate of a PMOS FET, a polycrystalline silicon layer region 111 over a gate of a NMOS FET, a polycrystalline silicon layer 112 of an upper electrode plate region of the capacitor dielectric layer, and a polycrystalline silicon layer region of connecting elements, that is, a first polycrystalline silicon region 113 to be connected with a second polycrystalline silicon in the following process. After the removal of the polycrystalline silicon layer 25 by a conventional method, the fifth photoresist 26 is also removed. Then a sixth photoresist 27 is deposited to form a base region of a bipolar transistor as shown in FIGS. 1(J) and 1(J'), and there is formed a P-type active base region 28 to form a non-compensated emitter region by means of a ion implantation of group III impurity such as boron (B) with an energy of about 70 KeV and a dose of 1.times.10.sup.12 -5.times.10.sup.13 ions/cm.sup.2. After removing the sixth photoresist 27 used as a masking layer, a thermal process is carried out in a conventional method in order to activate a group III impurity such as boron implanted into the base region. Then a seventh photoresist 29 for the Lightly Doped Drain (LDD) is coated on the silicon surface, as shown in FIGS. 1(K) and 1(K'). By way of ion implantation of a group V impurity such as phosphorus (P) into only source/drain region of NMOS FET, with a dose of 10.sup.12 -10.sup.14 ions/cm.sup.2 and an energy of about 30 KeV, there is formed source and drain regions 30 of the LDD-type NMOS transistor. After forming said source/drain region of low concentration and removing the seventh photoresist 29, an oxide layer 31 with the thickness of 500 .ANG. is deposited on the first polycrystalline silicon layer 25 by carrying out a conventional thermal oxidation process at a temperature 900 .degree. C. and an oxide layer 32 is deposited on the whole silicon surface by a conventional CVD method as shown in FIGS. 1(L) and (L'). Thereafter, by processing the oxide layer 31 deposited by said thermal oxidation process and the oxide layer 32 deposited by the CVD method through a conventional dry etching method, as shown in FIG. 1(M), oxide layer spacers 33,34 of side walls of gate electrodes of NMOS and PMOS transistors are formed and a connecting region 114 for a lower electrode of a MOS capacitor is also formed. Said oxide layer spacer 33 becomes a mask for an ion implantation process to form high-concentration drain and source regions of a NMOS transistor with the LDD structure in the following process, thereby achieving a NMOS transistor having a LDD structure.

An eighth photoresist 35 is then coated on the silicon surface as shown in FIGS. 1(N) and 1(N'). Consequently, there are formed a connecting region 36 of the first substrate region 10 of PMOS FET, a source/drain region 37 of a NMOS FET, an emitter region 38 of metal contact emitter NPN transistor, a collector connecting region 39 of the third substrate region 11 of polycrystalline silicon emitter NPN transistor, a collector connecting region 40 of the fourth substrate region 12 of metal contact emitter NPN transistor, and a lower region 41 of a resistor, by performing ion implantation of group V impurity such as Arsenic with an energy of 40-80 KeV and a dose of 10.sup.14 -10.sup.16 ions/cm.sup.2. The eighth photoresist 35 is then removed.

In the preferred embodiment of this invention, the NPN transistor is formed after selectively performing the LDD ion implantation with the seventh photoresist 29, but in case that the base concentration of the NPN transistor is high enough not to be largely affected by the LDD ion implantation, the NPN transistor with LDD structure can be formed by performing the LDD ion implantation without depositing the seventh photoresist 29.

Referring to FIGS. 1(O) and 1(O'), a ninth photoresist 42 is deposited on the substrate surface, and the group III impurity such as Boron (B) with a dose of 10.sup.15 -10.sup.16 ions/cm.sup.2 is implanted with a low energy of about 30 KeV. Then there are formed a source/drain region 43 of PMOS FET, a connecting region 44 of the substrate 1 of NMOS FET, a connecting region 45 of the base 28 of the polycrystalline silicon emitter bipolar NPN transistor and a connecting region 46 of the base 28 of the metal contact emitter NPN transistor, and ninth photoresist 42 is removed. After this processing, an oxide layer 47 is deposited on the whole substrate surface by a conventional CVD method, and the quality of said oxide layer is densificated by a conventional method. Thereafter, a tenth photoresist 48 is coated on said silicon oxide layer 47, windows are formed on an emitter region 49 of the polycrystalline silicon emitter NPN transistor, a butting contact 50 of a resistor region and a contacting region 51 of a first and second polycrystalline silicon are formed by a general photolithographic technique, and then the group V impurity such as Arsenic (As) with a dose of 10.sup.15 -10.sup.16 ions/cm.sup.2 is ion-implanted with an energy of 40 KeV. Consequently, as shown in FIG. 1(P), there are formed an emitter region 52 of the polycrystalline silicon emitter NPN bipolar transistor, a butting contact region 50 of the high-concentration resistor portion (shown in FIG. 1(P') adequate for ohmic contact, and a contacting portion 51 (shown in FIG. 1(P') of a first and second polycrystalline silicon. After removing the tenth photoresist 48, there is formed a second polycrystalline silicon layer 53 on all silicon substrate surfaces by a conventional method, so that it can be used for electrode material of the polycrystalline silicon emitter, passive resistor elements made of the polycrystalline silicon and connecting material.

As shown in FIGS. 1(Q) and 1(Q'), an eleventh photoresist 54 is deposited so as to leave a polycrystalline silicon region 117, a butting contact region, a second polycrystalline silicon region 118 of the resistor element having the sheet resistance of Giga ohms per square (G.OMEGA./.quadrature.) unit, a resistor element region 119 of several hundreds .OMEGA./.quadrature. utilizing the second polycrystalline silicon layer and a polycrystalline silicon layer of only the second polycrystalline silicon portion 120 to be connected with the first polycrystalline silicon. After removing the polycrystalline silicon layer by general photolithographic techniques, the eleventh photoresist 54 is removed by a conventional method.

Thereafter, a twelfth photoresist 55 is deposited, as shown in FIG. 1(R'), in order to selectively control the electric characteristics of a passive element which is made of polycrystalline silicon. Resistor region 118a having the G.OMEGA./.quadrature. resistance is masked for protection, and the group V impurity such as Arsenic (As) with a appropriate dose concentration is ion implanted into the butting contact portion, the connecting portion of first and second polycrystalline silicon and a polycrystalline silicon emitter region so as to obtain sheet resistance of several hundreds of .OMEGA./.quadrature.. Then the twelfth photoresist 55 is removed by a conventional method. A conventional CVD oxide layer 56 is deposited on the whole silicon surface, and the activation of impurities implanted into said regions 43, 44, 45, 46, 36, 37, 38 and 52 and the cohesion of said oxide layer 56 are performed by thermal annealing process. As shown in FIGS. 1(S) and 1(S'), a thirteenth photoresist 57 is coated on the whole substrate. Then there are etched the connecting region window 121 of the first substrate region and the source/drain region window 122 in PMOS FET, the source/drain region window 123 and the connecting region window 124 of the second substrate 1 region in NMOS FET, the base connecting region window 125, the emitter connecting region window 126 and the collector connecting region window 127 in the polycrystalline emitter bipolar NPN transistor, the emitter connecting region window 128, the base connecting region window 129 and the collector connecting region window 130 in the metal contact emitter NPN transistor, and finally the first and second polycrystalline silicon contacts 131 to 134.

After removing said thirteenth photoresist 57, there is deposited a metal layer 58 by a conventional vacuum evaporation method, as shown in FIGS. 1(T) and 1(T'). Next, a fourteenth photoresist 59 is deposited and a metal layer 58 is etched. Consequently, there are formed a connecting electrode 135 of the first substrate region 10 and source/drain electrode 136 of PMOS FET, the source/drain electrode 137 and the second substrate connecting electrode 138 of NMOS FET, the emitter electrode 139 and the base electrode 140 and the third substrate collector electrode 141 of the polycrystalline silicon emitter bipolar NPN transistor, the emitter electrode 142, the base electrode 143 and the fourth substrate collector electrode 144 of the metal contact emitter bipolar transistor, electrodes 145,146 of the MOS capacitor, electrodes 147 to 149 of the resistor region having the order of some G.OMEGA./.quadrature. or several hundreds of .OMEGA./.quadrature., and an electrode 150 of the contacting region of the first and second polycrystalline silicon. Then the fourteenth photoresist 59 is removed by the conventional method. After removing the fourteenth phtoresist 59, there is coated a protecting layer 60 (shown in FIG. 2) to protect the semiconductor device. In the preferred embodiment for forming the emitter region of said polycrystalline silicon emitter NPN transistor, as shown in FIG. 1(P), there are formed the emitter region by means of ion-implantation, deposited the second polycrystalline silicon layer above the emitter region, performed the N-type ion implantation on the second polycrystalline silicon layer, formed the oxide layer over all the substrate, and then activated said ion-implanted impurties by the thermal process.

However, the emitter region of polycrystalline silicon emitter NPN transistor may be also formed as the following method. After the processing of FIG. 1(O), there are removed the mask layer on the substrate and formed the CVD oxide layer on the whole substrate. Then the impurities implanted by said process are activated and a window for forming the emitter region of the first NPN transistor is made. There is formed a connecting part for the second polycrystalline silicon layer on the emitter region with said window and thereon ion-implanted with the high concentration. Then, a CVD oxide layer is deposited on the whole substrate and the thermal process is performed, by which the impurities implanted into the second polycrystalline silicon layer are activated so that the emitter region of the N-type first bipolar transistor having high concentration can be formed toward the base region.

FIG. 2 shows a final cross-sectional view of a complete BiCMOS device manufactured through said fabrication process according to the invention, wherein region `a` is that of the PMOS transistor, region `b` is of the NMOS transistor with LDD structure, region `c` is of the polycrystalline silicon emitter NPN transistor, region `d` is of the metal emitter NPN transistor, region `e` is of the MOS capacitor, region `f` is of the polycrystalline silicon resistor region having the resistance with the order of G.OMEGA./.quadrature., region `g` is of the butting contact, region `h` is of the polycrystalline silicon resistor with several hundreds of .OMEGA./.quadrature., and region `i` is a contacting region connecting the first polycrystalline silicon layer with the second polycrystalline silicon layer.

FIG. 3 is a final cross-sectional view showing a portion of active elements in another preferred embodiment according to this invention. In the previous embodiment of FIGS. 1(A) to (T), the description of this invention is mainly made with respect to the triple diffusion structures thereof. However, it should be noted that this invention will be suitable for the formation of a BiCMOS structure having a standard bipolar transistor with the buried layer and the epitaxial layer as illustrated in FIG. 3. Referring to said BiCMOS structure, after forming a second conductivity type of buried layers 62, 63, 64 on a first conductivity type of single crystal silicon substrate 61 having low concentration, there is grown a first conductivity type of epitaxial layer 65 with high concentration on the whole substrate surface. Thereafter a first substrate region 66 forming a first MOS transistor with a first conductivity type of channel, and third and fourth substrate regions 67,68 making first and second bipolar transistors are respectively formed on the second conductivity type of buried layers 62, 63, 64. An epitaxial layer 65 between the first and third substrate regions 66,67 will be a second substrate region for forming a second MOS transistor. By sequentially performing the processes as shown in FIGS. 1(C) to 1(T), there can be manufactured a BiCMOS semiconductor device of FIG. 3 comprising a P-channel FET, a N-channel FET, a polycrystalline silicon emitter bipolar transistor and a metal contact emitter bipolar transistor. In practice, after a N+ buried layer above a P-type single crystal silicon substrate with the <100> orientation and the resistivity of 0.006-0.1 .OMEGA..cndot.Cm is formed, a P-type epitaxial layer with the resistivity of 5 .OMEGA..cndot.Cm is grown, and N-type first, third and fourth substrates are formed. Consequently, by sequentially carrying out the processes according to FIGS. 1(C) to 1(T), said BiCMOS device can be manufactured.

Referring to FIG. 4, showing each fabrication step in an another preferred embodiment according to this invention, the processes identical to those of FIGS. 1(A) to 1(J) are performed on the substrate in which the P-type epitaxial layer of high concentration is deposited on the P-type single crystal silicon substrate as shown in FIG. 1 or on the P-type single crystal silicon layer of low concentration as shown in FIG. 3. Thereafter the remaining photoresist 27 above said substrate and the oxide layer 23 above regions for forming elements are removed. As shown in FIG. 4(N), the eighth photoresist 35 is deposited on the silicon substrate surface and the group V impurity such as Arsenic (As) with the dose of 10.sup.14 -10.sup.16 ions/cm.sup.2 is implanted with an energy of 40-80 KeV. Then there are formed a connecting region 36 of the first substrate region 10 of PMOS transistor, a source/drain region 37 of the second substrate region of a NMOS transistor, an emitter region 38 of the metal contact emitter NPN transistor, a collector connecting region 39 of the third substrate region 11 of the polycrystalline silicon emitter NPN transistor, a collector connecting region 40 of the fourth substrate region 12 of the metal contact emitter NPN transistor and a lower region 41 of the resistor which is not illustrated in FIG. 4. Thus the eighth photoresist 35 is removed. The subsequent processes from the process of FIG. 4(O) are identical to the corresponding ones of FIGS. 1(O) to 1(T), respectively. In FIGS. 4(N) to 4(T) and FIGS. 1(N) to 1(T), the same reference numerals are used to represent the same elements and regions in the same fabrication process. Said FIGS. 4(N) to 4(T) show a portion of active elements of the BiCMOS transistor of this invention, and a portion of the passive elements thereof, which is not illustrated therein, can be formed as shown in FIGS. 1(A') to 1(T') by the aforementioned processes. The BiCMOS device manufactured through said processes becomes a BICMOS device consisting of a conventional NMOS transistor instead of the NMOS transistor with LDD structure, being different from the preferred embodiment illustrated in FIG. 3.

As described hereinbefore, the invention achieves high-integration, high-performance MOS transistors in a BiCMOS semiconductor device, and further achieves high-performance, high-precision bipolar transistors having a good matching characteristic together with the formation of said NMOS transistor, thereby enabling use in a precision analog circuit. Also it will be noted that the invention is well arranged for the polycrystalline silicon emitter NPN transistor having a small area of emitter which is particularly suitable for high-speed digital devices and the metal contact emitter NPN transistor which is specially fit for precise analog circuit and high-load driving power. Furthermore, the invention optimally integrates the high quality MOS capacitor particularly necessary for an analog MOS circuit and the polycrystalline silicon resistor for the bias and load in various circuits, and achieves more convenient inter-connections between the elements. Accordingly, there will be optimally achieved a high-performance digital VLSI circuit such as a logic circuit, a memory, etc. or an analog VLSI circuit such as a data converter, a switched capacitor circuit, etc. or the composite circuit of the two, which has been relatively difficult to achieve by means of the prior art.

While the invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference this description, without departing from the spirit of the invention.