Integrated Mos High-Voltage Level-Translation Circuit, Structure and Method

1. Field of the Invention

This invention generally relates to a high-voltage level-translation circuit structure and method, and more particularly, to a high-voltage level-translation circuit structure and method suitable for use in high-voltage MOS integrated circuit type applications.

2. Brief Description of the Prior Art

Complementary N and P channel MOS devices have been commonly used for active pull-up and pull-down operation in power driven circuitry. For supply voltages greater than about 50 volts, the P and N channel gates of the complementary driver devices are usually driven separately in order to avoid excessive gate voltages. This separate operation or excitation requires high-voltage level-shifting or level-translation circuitry to translate a ground-reference logic signal to a high-voltage reference logic signal to drive one of these push-pull devices. Discrete type level translation devices usually involve the additional use of an optoelectronic isolation, a resistor and zener voltage divider, or capacitive coupling circuitry. These approaches are either incompatible with silicon integrated circuitry, inefficient in using silicon real estate, or involve substantial performance trade-offs.

Thus, a need has existed to provide improved high-voltage level translation circuitry for drawing serially-connected high-voltage MOS transistors. In particular, a need has existed to provide high-voltage level-translation circuitry suitable for monolithic integration without substantial loss of performance.

In accordance with the preferred embodiments of this invention described hereinafter, it is an object of this invention to provide a high-voltage level-translation circuit, method and structure compatible for use with MOS semiconductor devices.

It is still another object of this invention is to provide a level-translation unit comprising MOS transistors for driving one of a pair of complementary MOS transistors serially connected across a high voltage supply.

It is yet another object of this invention to provide a high-voltage level-translation circuit capable of economical integration in a monolithic integrated circuit format.

In accordance with a preferred embodiment of this invention, there is provided a level-translation circuit and method comprising or providing first and second serially-connected current source devices. The second current source device may be switched on or off, while the first current source device is coupled to shunt means for limiting its voltage excursion when the second current source device is switched on. The second current source device has a greater current-carrying capability than the first current source device.

In accordance with another embodiment of this invention, an integrated high-voltage level-translation circuit comprising CMOS transistors is provided requiring a high-voltage device of only one conductivity type, resulting in or permitting relatively simple and inexpensive integration.

The foregoing and other objects, features, and advantages of this invention will be apparent from the following, more particular description of the preferred embodiments of this invention as illustrated in the accompanying drawings.

FIGS. 1a and 1b are, respectively, electrical schematic and block diagram illustrations of prior art power driver circuitry.

FIG. 2 is a skeleton block diagram and schematic embodiment of a power driver circuit including a level translator according to the present invention.

FIG. 3 is a detailed schematic of a preferred embodiment of the level translator portion of the circuitry of FIG. 2.

FIG. 4 is a cross-sectional view of the integrated circuit architecture or structure suitable for the integration of the level translation circuit of FIG. 3.

Referring now to FIG. 1a, there is shown a prior art CMOS circuit comprising an output driver inverter 10 comprising P-type (P.sub.2) MOS transistor 12 and N type (N.sub.2) MOS transistor 14 whose gates are connected together, whose drains are connected together and whose sources are connected, respectively, to V.sub.pp and V.sub.nn. The output driven inverter 10 is driven by a pre-driver inverter 16 comprising a P type (P.sub.1) MOS transistor 18 and an N type (N.sub.1) MOS transistor 20. The source of the MOS transistors 18 and 20 are respectively connected to V.sub.pp and V.sub.nn, their gates are connected together and to an input terminal, and their drains are connected together and are also connected to the gates of the MOS transistors 12 and 14. Substantially all the supply voltage V.sub.pp or V.sub.nn is impressed across the gate to source terminals of one or the other of the CMOS transistors in the output driver 10 (output driver inverter) depending on the state of the predriver inverter 16. This arrangement is thus only suitable for supply levels up to about the gate rupture voltage of the output driver CMOS transistors 12 and 14, or about 50 volts for typical devices.

For higher voltages, the prior art has usually employed the block diagram and schematic circuitry of FIG. 1b. Here the output driver CMOS transistors 12 and 14 of the output driver 10 are connected between a first supply voltage V.sub.pp and a second supply voltage V.sub.nn. The low voltage pre-driver circuit 16 comprising the complementary pair of MOS devices 18 and 20 which is referenced to V.sub.nn drives the N-channel MOS transistor 14 directly to provide a gate signal somewhat in excess of its threshold voltage. The gate of the P-channel transistor 12 is driven through a level translator 22 to provide a gate voltage drive referenced to V.sub.pp but which cannot swing sufficiently below V.sub.pp to rupture the gate of the P-channel transistor 12. In the past, level translation has been accomplished with an opto-isolator, a resistor and zener voltage divider, or a capacitive coupling circuit. These approaches are either incompatible with silicon integrated circuit technology or inefficient in using silicon area so that the cost of the translation function is excessive.

The basic operation of the improved active level translation circuitry of this invention may be understood with reference to the schematic diagram of FIG. 2. The level translator portion of the circuitry surrounded by the dotted rectangle is functionally equivalent to a low voltage (e.g. 20 volts) constant current source I.sub.1 in series with a high-voltage (e.g. 400 volts) gated constant current source I.sub.2. A voltage limiting device such as zener diode Z.sub.1 having a breakdown voltage (e.g. 14 volts) less than the breakdown voltage of the low-voltage constant current source I.sub.1 may be used to limit the voltage excursion between the gate and the source of the P-channel MOS transistor 12 comprising the pull-up device of the output driver 10.

The magnitude of the lower positioned constant current source I.sub.2 is greater than the magnitude of the upper positioned constant current source I.sub.1. When I.sub.2 is gated off, the charge on the load capacitance (gate and Miller capacitances of the P-channel output driver transistor 12) will be discharged by the upper positioned constant current source I.sub.1 and thus will return the voltage on output node 24 of the level translator to V.sub.pp. When the bottom positioned constant current source I.sub.2 is gated on, the condition I.sub.2 >I.sub.1 will result in a pulldown of the voltage on the translator output node 24 until the zener voltage is reached. The output thus pulls down about 14 V below V.sub.pp. Thus a logic level signal from Logic Circuitry 26 to the lower gated constant current source I.sub.2 can generate a high-voltage reference signal of about 14 V amplitude providing a differential output signal having a magnitude much less than the differences between the supply voltages V.sub.pp and V.sub.nn.

FIG. 3 shows CMOS circuitry for the implementation of the schematic level translator of FIG. 2. The constant current sources I.sub.1 and I.sub.2 comprise P-channel depletion mode transistors PD.sub.1 and PD.sub.2 respectively. Transistors PD.sub.1 and PD.sub.2 have source feedback resistors R.sub.1 and R.sub.2, respectively. The current ratio I.sub.1 /I.sub.2 of the top to bottom current sources is controlled by the transistor geometry and the source feedback resistors R.sub.1 and R.sub.2. For proper operation, this ratio must be less than one. In practice, a nominal value of I.sub.1 /I.sub.2 of about 0.6 has been found suitable to ensure that the ratio never reaches one. Both depletion transistors of the top and bottom constant current sources are preferably designed with identical operating points to maintain a tight distribution of the current I.sub.1 /I.sub.2. Such tracking constant current source design eliminates possible circuit malfunction caused by unity or greater current ratio. The source feedback resistors R.sub.1 and R.sub.2 reduce the effect of process parameter variation on the current ratio.

High voltage N-channel enhancement mode MOS transistor NH.sub.2 in FIG. 3 is driven by the logic level circuitry (not shown in FIG. 3) connected to the terminal that is connected to the gate of the transistor NH.sub.2. When the NH.sub.2 transistor is off, the current through the upper positioned current source I.sub.1 comprising PD.sub.1 returns the output voltage to V.sub.pp. When the NH.sub.2 transistor is turned on, its current rises to the current I.sub.2 of the lower positioned current source I.sub.2 provided by transistor PD.sub.2. Since this is more current than can be provided by the current source I.sub.1 comprising PD.sub.1, current will flow through the serially-connected enhancement mode P-channel transistors P.sub.10, P.sub.20 and P.sub.30 which together operate or function like the zener diode Z.sub.1 of FIG. 2. Since these three P-channel MOS transistors 10, 20 and 30 each have a drain shorted to the gate, a voltage equal to about three times the threshold voltage is generated at the output terminal OUT. This voltage may be, for example, about 14 V below V.sub.pp and is sufficient to drive the top MOS transistor 12 in the output driver 10 of FIG. 1 or FIG. 2. The foregoing assumes that the breakdown voltage of PD.sub.1 is greater than the serial combination of P.sub.10, P.sub.20 and P.sub.30. Alternatively, the breakdown voltage of PD.sub.1 could be controlled at the desired differential output voltage level.

Referring now to FIG. 4, the architecture or structure of a monolithic silicon CMOS integrated circuit suitable for appropriate interconnection and for the implementation of the high voltage level translator of FIG. 3 is shown. The integrated circuit comprises a low-voltage (e.g. 36 volt) CMOS (logic circuitry) section located on the left side of this figure including a low voltage MOS N-channel (LV N-CH) and a low voltage MOS P-channel (LV P-CH) pair of MOS transistors in the logic circuitry section. The technology uses preferably conventional PN junction isolated N-well CMOS integration.

The level translator circuitry itself located on the right side of this 400 volt pseudo push-pull junction-isolated high voltage CMOS technology includes a high voltage MOS N-channel transistor (HV N-CH) and low voltage P-channel transistors (P-CH and P-CH DEPL). The 400 volt high voltage N-channel transistor H V N-CH is a lateral DMOS type of device well known to those skilled in the art. The logic and level translator circuit devices of FIG. 4 are all incorporated in a single high-sensitivity P-type substrate. Because of the design of the high voltage level translator circuit described in detail hereinbefore, a high voltage P-channel transistor is not required, substantially simplifying the monolithic integrated embodiment depicted in FIG. 4. Relating FIG. 4 to FIG. 3, PD.sub.1 and PD.sub.2 each comprised P-CH DEPL transistors (only one of the two are shown in FIG. 4). Transistor, NH.sub.2 is the HV N-CH transistor, and P.sub.10, P.sub.20 and P.sub.30 each comprise a P-CH transistor (only one of the three is shown in FIG. 4) in the level translation circuitry of FIG. 4.

There are, however, two factors which could substantially limit the maximum operating voltage of the high voltage CMOS circuitry of the level translator section of the integrated circuit of FIG. 4. These are vertical punch-through of the N-type well containing both P-CH and P-CH DEPL devices, and high-voltage CMOS latch-up. In the architecture of FIG. 4, vertical N-well punch-through is precluded by using a double N-well concept. A 10 micron deep relatively lightly doped N-well is used for the (logic circuitry) low-voltage p-channel transistor (LV P-CH) device, while a 15 micron relatively heavily-doped N-well is used for the level-translator portion to achieve the requisite punch-through voltage of the 400 volt pseudo CMOS level-translator section. By using a single high resistivity P-type substrate (e.g. 50 ohm-cm) both breakdown voltage and the punch-through voltage of the N-well containing both P-CH and P-CH DEPL are above 500 volts.

High voltage latch-up is prevented in two ways. First, the vertical parasitic PNP bi-polar gain is minimized by the relatively heavy doping of the 15 micron N-well in the high-voltage level translator section. The 15 micron well results in a large PNP base width. The high well doping also reduces the emitter injection efficiency. Both of these result in a low PNP bipolar gain. Second, the lateral NPN bipolar gain is degraded or reduced by the provision of a relatively deep, relatively heavily-doped P+ region that is located between the high-voltage N-channel (H V N-CH) transistor and the low voltage P-channel transistors P-CH and P-CH DEPL in the level translation portion of the integrated circuit. This P+ deep diffusion, which may have a depth of about 20 microns, greatly reduces the NPN gain. By using both the heavily-doped N-well and the deep P+ diffusion, the product of the NPN and the PNP current gains has been reduced to significantly less than one.

While the high-voltage level translator of the present invention has been particularly described and shown with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail and omissions may be made therein without departing from the spirit and scope of the invention.