Refresh Arrangement in a Block Divided Memory Including a Plurality of Shift Registers

1. Field of the Invention

The present invention relates to a block access memory and, more specifically, it relates to an improved accessing for enhancing an operating efficiency of a block access memory.

2. Description of the Prior Art

Recently, a semiconductor memory device has come to be implemented with larger capacity and it has been desired to enhance the data transfer rate in order to provide high speed operation. In order to improve the data transfer rate, a block access memory as shown in FIG. 1 has come to be used in which data input/output is carried out serially between the shift register and a data input/output portion, and data transfer is simultaneously carried out between the shift register and an entire row of memory cells (memory cells connected to one word line).

Referring to FIG. 1, a conventional block access memory comprises an address buffer 7 which receives externally applied external address signals A0 to A7 and generates complementary address signals A0, A0 to A7, A7; a refresh address counter 8 which successively generates refresh row addresses for designating the row to be refreshed; a REF buffer 9 which receives an externally applied external refresh signal Ext. REF for designating the refresh cycle and generates signals REF and REF for transmitting either the complementary address A0 to A7, A0 to A7 or the refresh row address from the refresh address counter 8; a switch SW1 which turns on in response to the signal REF from the REF buffer 9 for transmitting an output of the address buffer 7 to the row decoder 1; a switch SW2 which turns on in response to the signal REF from the REF buffer 9 for transmitting the refresh row address from the refresh address counter 8 to the row decoder 1; a row decoder 1 which receives and decodes a row address applied from the address buffer 7 or from the refresh address counter 8 and selects accordingly one word line; a plurality of memory cells 4 arranged in rows and columns, each storing information; a plurality of word lines 2 for selecting one row of the plurality of memory cells 4; a plurality of bit lines 3 to each of which is transmitted the information of a memory cell connected to the word line which is in turn selected by the output of the row decoder 1; a sense amplifier group 5 provided corresponding to each of the bit lines 3 for detecting/amplifying the information on the bit lines; a shift register 6 which simultaneously receives the signals from the sense amplifier group 5 in response to the clock signal .PHI.20 and transmits the received data successively to the data output buffer 10 in response to clock signals .PHI.1 and .PHI.2; and an output buffer 10 which outputs the information from the shift register 6 serially as the output data D.sub.OUT. In FIG. 1, the memory cell array MA is structured with 256 rows.times.256 columns as an example. The shift register 6 has its output portion and the input portion connected together to form a loop. The sense amplifier group 5 is activated in response to the sense amplifier activating signal SE.

FIG. 2 shows the structure of the sense amplifier group 5 and the shift register 6 shown in FIG. 1 in more detail. Referring to FIG. 2, the sense amplifier group 5 is constituted by 256 sense amplifiers 5-1 to 5-256 provided corresponding to each of the bit line pairs. Each of the sense amplifiers 5-1 to 5-256 is constituted by two switch transistors Tr1 and Tr2 having their gates and drains cross connected and is activated in response to the sense amplifier activating signal SE to differentially amplify the potential on the bit lines using the level of a bit line to which the non-selected memory cell is connected as a reference potential, and outputs a potential on the bit line BL. As for the bit lines, a bit line to which a selected memory cell is connected and a reference bit line which applies the comparison reference potential with respect to the potential on that bit line are arranged in pairs. The shift register 6 is constituted by 256 stages of unit shift registers 6-1 to 6-256. Each of the unit shift registers 6-1 to 6-256 is constituted by two stage inverters I1 and I2 and a switch transistor T1 connected between these inverters and which turns on in response to the clock signal .PHI.1. A switching transistor T2 which turns on in response to the clock signal .PHI.2 is provided between adjacent unit shift registers. The outputs of the sense amplifiers 5-1 to 5-256 are transmitted to the input portions of respective unit shift registers 6-1 to 6-256 through the switching transistors 11-1 to 11-256 which turn on in response to the clock signal .PHI.20.

FIG. 3 is a waveform diagram showing the data reading operation in a conventional block access memory shown in FIG. 1. The operation of a conventional block access memory will be hereinafter described with reference to FIGS. 1 to 3.

First, for example, an external RAS signal (not shown) which is a basic operation timing signal becomes activated and external address signals A0 to A7 are taken into the memory chip and applied to the address buffer 7. In the normal data reading cycle, the external refresh signal Ext. REF is at a low level. Therefore, the signal REF is at a high level, the signal REF is at the low level, and the switch SW1 is turned on while the switch SW2 is turned off. The complementary addresses A0, A0 to A7, A7 generated in the address buffer 7 are transmitted to the row decoder 1 through the switch SW1. Thereafter, one word line is selected by the row decoder 1 which is designated by the address signals A0, A0 to A7, A7, the potential of the selected word line WL rises and one row of memory cells is selected. Consequently, the potential change corresponding to the information contained in the memory cell connected to the selected word line WL appears on each of the bit lines 3. Thereafter, the sense amplifier activating signal SE falls and the sense amplifier group 5 (5-1 to 5-256 of FIG. 2) is activated and differentially amplifies the potential on each bit line pair BL and BL using the level bit line to which the non-selected memory cell is connected as a reference potential. Then, the clock signal .PHI.20 rises and the switch transistors 11-1 to 11-256 turn on and the information from each of the sense amplifiers 5-1 to 5-256 is simultaneously transmitted to the input portion of each of the unit shift registers 6-1 to 6-256 of the shift register 6. The information transmitted to the shift register 6 is successively transmitted to the data output buffer 10 serially bit by bit in response to the clock signals .PHI.1 and .PHI.2, and the serial 256 bit data is read through the data output buffer 10 as the output data D.sub.OUT. When one cycle (serial read cycle) is completed, the potential of the selected word line WL falls and the sense amplifier activating signal SE rises, and the external refresh signal Ext. REF becomes high level so that the signal REF becomes high level and the signal REF becomes low level. Consequently, the refresh row address from the refresh address counter 8 is transmitted to the row decoder 1 through the switch SW2, thereby starting the refresh cycle. One word line is selected corresponding to the refresh row address which is decoded by the row decoder 1, the selected word line level rises and the information contained in the memory cells connected to the selected word line is transmitted to respective bit lines. Thereafter, the sense amplifier activating signal SE becomes low level and the sense amplifier group 5 is activated to differentially amplify the potential difference on each bit line pair, establishing the potential level on the bit lines 3. Thereafter, by lowering the potential of the selected word line, the potential level on each bit line is re-written in each memory cell, and the refresh of the memory cell information is completed. On this occasion, the refresh address counter 8 outputs a refresh row address and applies the same to the row decoder 1 and thereafter increments or decrements the address.

The operation timing of the refresh address counter 8 is given by, for example, the signal REF and the increment or decrement of the refresh row address is automatically carried out in the counter 8.

The data writing cycle is carried out with the same timing as in the data reading and data is serially inputted to the shift register 6 from a data input buffer, which is not shown. As for the operation in data writing, the operation timing is similar to that in reading, except that the flow of the stream of data is reversed to that in the reading. Namely, the description of the operation of data reading is directly applied when the reading buffer 10 of FIG. 1 is replaced with a writing (or data input) buffer and the data is assumed to flow from the writing buffer to the shift register and to the memory cells of one row.

Since a conventional block access memory is structured as described above, a refresh cycle must be interposed between the normal data reading cycle or the data writing cycle in order to refresh the memory cells, so that the operating efficiency of the block access memory is lowered.

A memory device in which the data transfer is carried out between memory cells of one row and the shift register is disclosed in U.S. Pat. No. 4,541,075 to Dill et al., entitled "RANDOM ACCESS MEMORY HAVING A SECOND INPUT/OUTPUT PORT", U.S. Pat. No. 4,044,339 to Berg, entitled "BLOCK ORIENTED RANDOM ACCESS MEMORY" and in an article "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications" by R. PINKHAM et al., IEEE Journal of Solid-State Circuits Vol. SC-19, No. 6, December 1984, pp. 999-1007.

These prior arts disclose a structure in which serial data transfer is carried out between the shift register and the exterior and the simultaneous data transfer of all of the data bits is carried out between the shift register and the memory cells of one row in the DRAM. However, there is no consideration for the existence of a refresh cycle which is an essential operation cycle in the DRAM in these references.

An object of the present invention is to prevent the above described lowering of efficiency in utilizing the memory due to the refresh cycle in a conventional block access memory.

The specific object of the present invention is to provide a block access memory which is capable of refreshing each memory cell without interposing a special cycle as a refresh cycle between the normal access (writing and reading) cycles.

Another specific object of the present invention is to provide a method for driving the block access memory which enables refreshing of each memory cell without providing a special operation cycle as a refresh cycle.

In the block access memory of the present invention, the memory cell array is divided into a plurality of blocks, the data reading or writing is carried out by selecting and accessing a word line in each block in response to the external address and the word lines of the not-accessed blocks are selected by the output of the refresh address counter to carry out refreshing in parallel to the access of the selected blocks.

In the block access memory of the present invention, the reading or writing of data is carried out in a block by block access manner, and the refreshing is carried out by selecting a word line in the non-selected blocks by the output of the refresh address counter in parallel to the access of the selected block, so that the refresh cycle simultaneously occurs with the read cycle or the write cycle for normal data reading or writing. Therefore, there is no need for providing a special cycle for refreshing in the block access memory, whereby the operating efficiency of the block access memory can be enhanced.

These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 schematically shows one example of the whole structure of a conventional block access memory;

FIG. 2 shows one example of the specific structure of the sense amplifier portion and the shift register portion of the block access memory shown in FIG. 1;

FIG. 3 is a diagram of waveforms showing the operation in reading and refreshing a conventional block access memory;

FIG. 4 schematically shows the whole structure of the block access memory in accordance with one embodiment of the present invention; and

FIG. 5 is a diagram of waveforms showing the operation in reading of the block access memory in accordance with one embodiment of the present invention.

FIG. 4 shows a structure of the block access memory of one embodiment of the present invention, showing the structure associated with the data reading path.

Referring to FIG. 4, in the block access memory of the present invention, the memory cell array is divided into two blocks, that is, block #1 and block #2. Each of the blocks #1 and #2 comprises a plurality of memory cells 4 arranged in rows and columns each of which stores information, a plurality of word lines 2-1 to 2-n for selecting one row of the plurality of memory cells, a plurality of bit lines 3 to which the information contained in the memory cell connected to a selected word line is transmitted and sense amplifier groups 5 and 5' which detect and amplify the information appearing on the bit lines 3 when activated in response to the sense amplifier activating signal SE. The output of the sense amplifier group 5 in the block #1 is simultaneously transmitted to the shift register 6 provided corresponding to the block #1 through a switch which turns on in response to the clock .PHI.10. A switch 26 which turns on in response to the clock .PHI.10 is provided between the shift register 6 and the sense amplifier group 5. The shift register 6 has its input portion and output portion connected to each other to form a loop. The shift register 6 transfers the received signal bit by bit in response to the clocks .PHI.1 and .PHI.2 generated in response to the clock .PHI.10. The output of the shift register 6 is transmitted to the data output buffer 10 through a switch transistor 16 which turns on in response to the block selection signal B1. The output of the sense amplifier group 5' provided corresponding to the block #2 is simultaneously transmitted to the shift register 6' which is provided corresponding to the block #2 through the switch 26' which turns on in response to the clock .PHI.20, The shift register 6' has its output portion and input portion connected to each other to form a loop. The shift register 6' shifts the contents bit by bit in response to the clocks .PHI.3 and .PHI.4. The clocks .PHI.3 and .PHI.4 are generated by detecting the completion of the shifting operation in the shift register 6 (which can be easily implemented by counting the number of the clocks .PHI.1 and .PHI.2) or, if the timing of generation of the clock .PHI.20 for data transfer corresponds to the timing of a shift in the shift register 6 (preferably the timing corresponding to the clock for transferring the bit immediately before the final bit in the shift register 6, for example, the clock for shifting the 127-th bit in the 128 bit structure shift register 6 and 6'), then the clocks .PHI.3 and .PHI.4 are generated in response to the clock .PHI.20. The output of the shift register 6' is transferred to the data output buffer 10 through the switch transistor 16' which turns on in response to the block selection signal B2.

Each of the word lines 2-1 to 2-n contained in block #1 comprises a corresponding one of a plurality of AND gates 12-1 to 12-n each of which receives the output of the row decoder 1 and the signal .PHI..sub.x1 for activating a word line at a first timing, and a corresponding one of AND gates 13-1 to 13-n each of which receives the output of the refresh address shift register 17 and a signal .PHI..sub.x2 for activating a word line at a second timing. Each of the word lines 2-1 to 2-n in block #2 comprises a corresponding one of AND gates 12'-1 to 12'-n each of which receives the output of the row decoder 1 and the signal .PHI..sub.x2 which activates a word line at the second timing and a corresponding one of AND gates 13'-1 to 13'-n each of which receives the output of the refresh address shift register 17 and the signal .PHI..sub.x1 which activates the word line at a first timing. The refresh address shift register 17 generates a refresh row address which designates a word line to be refreshed and after the refreshing of the blocks #1 and #2, it automatically increments or decrements the refresh row address.

Various structures may be employed as the refresh address shift register. The shift register of the most preferred structure may be provided with output portions corresponding to each word line, one of which output portions is previously set to a high level with the high level output portion shifted sequentially downward or upward at a predetermined timing.

The operation of the block access memory of one embodiment of the present invention will be hereinafter described with reference to FIG. 5, which is a diagram of waveforms of the block access memory of FIG. 4 in reading data. Now, the waveforms of FIG. 5 are for the case in which the memory block #1 is first accessed based on the external address and then the memory block #2 is selected and accessed based on the same external address. Therefore, the block selection signals B1 and B2 and the clock signals .PHI..sub.x1 and .PHI..sub.x2 are activated at respective predetermined sequence. Each of the timing signals .PHI.1, .PHI.2, .PHI..sub.x1, .PHI..sub.x2, .PHI.3, .PHI.4, B1 and B2 is generated by the clock generator 100.

First, external address signals A0 to A7 are taken in the memory chip in response to the activated state of the external RAS signal which is the basic timing signal for the memory operation, and complementary address signals A0, A0 to A7, A7 are applied to the row decoder 1 through the address buffer which receives the external address signals. One word line is selected by the row decoder 1 based on the address signals A0, A0 to A7, A7 and the output of the row decoder corresponding to the selected word line becomes a high level. Meanwhile, based on the refresh row address retained in the refresh address shift register 17, the output of the corresponding refresh address shift register 17 becomes high level. When the output of the row decoder 1 and the output of the refresh address shift register 17 are established, the first word line driving signal .PHI..sub.x1 becomes high level and is applied to the AND gates 12-1 to 12-n. One of the outputs of the AND gates 12-1 to 12-n becomes high level in response, and one word line WL.sub.S1 is selected and becomes high level in the block #1. Since the word line driving signal .PHI..sub.x2 remains low level on this occasion, the outputs of the AND gates 12'-1 to 12'-n and 13-1 to 13-n are at low level. On the other hand, in the block #2, one output of the AND gates 13'-1 to 13'-n becomes high level in response to the output of the refresh address shift register 17 and the first word line driving signal .PHI..sub.x1, one word line WL.sub.R2 is selected and the level thereof becomes high. Consequently, the information contained in the memory cells connected to the selected word lines WL.sub.S1 and WL.sub.R2 is read onto the bit lines 3. Thereafter, the sense amplifier activating signal SE becomes low level and the sense amplifiers 5 and 5' are both activated, and the potential on each of the bit lines 3 becomes high level or low level dependent on the information contained in the selected memory cell. In FIG. 5, the bit lines constitute complementary bit line pairs as in the conventional device and the sense amplifiers are shown with the structure for differentially amplifying the potential difference between a corresponding complementary bit line pair. In addition, the bit lines are shown being precharged at the Vcc (supply potential) level. When the state of the bit lines BL and BL is established to be high level or low level, the clock signal .PHI.10 becomes high level and the information detected and amplified by the sense amplifier group 5 in the block #1 is transferred to the shift register 6 through the switch 26. The structure of the sense amplifier group 5 and the shift register 6 are assumed to have the same structure as the conventional sense amplifier and the shift register. However, the step number (stage number) thereof is made one half, that is, 128 (in case the serial data is 256 bit). Then, the block selection signal B1 becomes high level, the switch transistor 16 turns on, the information from the shift register 6 is successively applied to the data output buffer 10 in response to the two phase clocks .PHI.1 and .PHI.2 generated in response to the clock .PHI.10, and the 128 bit data of the block #1 is successively outputted serially through the buffer 10. Meanwhile, in the block #2, since the clock .PHI.20 remains at low level, the refreshing operation is carried out in which the information detected and amplified by the sense amplifier 5' is again written in the memory cells, with the memory cells of one row in block #2 being refreshed.

While the 128 bit data from the shift register 6 is serially outputted successively in response to the clock signals .PHI.1 and .PHI.2, the first word line driving signal .PHI..sub.x1 falls and the sense amplifier activating signal SE rises so as to reset (precharge) the bit lines and the sense amplifiers of each of the blocks #1 and #2. On this occasion, the output of the row decoder 1 is not reset. Alternatively, the output of the row decoder 1 may be similarly reset while latching the address in the address buffer and the latched address A0 to A7 and A0 to A7 may be once again applied to the row decoder 1. Then, the second word line driving signal .PHI..sub.x2 rises. Consequently, the word line selection signal for the same row which is selected in the block #1 is applied to the AND gates 12'-1 to 12'-n through the respective output signal lines 14 of the row decoder 1. Simultaneously with the rise of the second word line clock signal .PHI..sub.x2 to the high level, one word line WL.sub.S2 is selected in the block #2 and the level thereof rises to the high level. At the same time, the refresh row address from the refresh address shift register 17 is applied to the AND gates 13-1 to 13-n, one word line is selected in accordance with the refresh row address designated by the refresh address shift register 17 in response to the second word line driving signal .PHI..sub.x2 at high level, and the selected word line WL.sub.R1 becomes high level in the block #1. Then, the information contained in the memory cells connected to the selected word lines WL.sub.S2 and WL.sub.R1 is transmitted to the respective bit lines 3, and the level of each of the bit lines BL and BL is established at high level or low level dependent on the logic "1" or "0" of the information contained in the memory cells connected to the selected word lines. When the level on the bit lines BL and BL is established by the sensing operation of the sense amplifiers 5 and 5', the clock .PHI.20 becomes high level and the level on each bit line BL in the block #2 is transferred to the input portion of each stage of the shift register 6' through the switch 26, waiting for outputting. Thereafter, when the serial output from the block #1 is detected to be 128-th bit (or 128 bits), the clocks .PHI.3 and .PHI.4 for shifting data from the block #2 are activated, the block selection signal is switched from B1 to B2 simultaneously, and the switch transistor 16' turns on, then the 128 bit data from the block #2 is successively transmitted to the data output buffer 10 serially, following the serial 128 bit from the block #1 without break, so that the 256 bit block data as whole is serially outputted without break in the same manner as in the conventional case. During the reading of the data from the block #2, the memory cells of one row of the selected word line WL.sub.R1 are refreshed and after the completion of the refreshing, the refresh row address of the refresh address shift register 17 is shifted by 1 bit (incremented or decremented) to be ready for the next cycle. The timing for generating the refresh row address of the refresh address shift register 17 and the timing for shifting the refresh row address may be controlled using the first and second word line driving signals .PHI..sub.x1 and .PHI..sub.x2 as shown in FIG. 4 or, alternatively, it may be controlled by the internal RAS signal which is generated in synchronization with the external RAS signal which provides the timing for taking the external address into the chip. The refresh row address may be continuously outputted and the shifting only may be effected before the start or after the end of the refreshing.

Although in the above described embodiment the memory cell array (256 rows.times.256 columns) is divided into two blocks, it is not limited to this and the memory cell array may be divided into any number of blocks to obtain the same effect as in the above described embodiment.

In addition, although in the above described embodiment the description was made of a case in which the data is serially read, it is not limited and the same effect as in the above described embodiment can be obtained in the write cycle in which the data is serially inputted to the shift register and the information is written in the memory cells of one row at one time. The operation timing signal in the write cycle is almost the same as the operation timing signal in the read cycle and the data stream is considered to flow in the reverse direction with the data output buffer replaced with the data input buffer, as shown by the dotted line in FIG. 4.

As described above, according to the present invention, the memory cell array is divided into a plurality of blocks, the access is carried out for each block as a unit based on the external address, and the accessing is carried out for reading or writing the data in the selected block while the refreshing is carried out based on the output of the refresh address shift register in the non-selected block, with each of the blocks connected to the input/output circuits by switching the accessing to the plurality of the blocks at appropriate timings. Therefore, the reading or writing of one bulk of a serial data is seemingly carried out, while the refreshing can be successively carried out actually inside behind the access cycle, so that the operating efficiency in utilizing the block access memory can be enhanced without providing a specific refresh cycle between the read cycles or the write cycles.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.