Architecture for a Fast Frame Store Using Dynamic RAMS

1. Field of the Invention

This invention relates to digital storage systems and more particularly to fast frame stores for storing digital images.

2. Description Relative to the Prior Art

A digital image processor can be used to improve the quality of a photographic image and typically includes a digitizer, a frame store, a processing section and an output device such as a printer. The digital image to be processed can be provided in a number of ways such as by scanning a beam of light through a photographic negative onto a photodetector. The output signal from the photodetector is digitized and stored in the frame store. The processing section performs the necessary image enhancement processing on the digitized image and the enhanced digital image is read out from the frame store and provided to a high speed "scan" printer.

Systems have been devised for scanning all of the pixels of the film negative quite rapidly, leading to the requirement for a frame store capable of handling data rates on the order of 15 MHz (70 ns/pixel) and having a memory capacity of a number of megabytes. A frame store capable of handling data at such rates can be constructed of random access memory (RAM) devices which are available to operate in static or dynamic modes. Each storage cell in a RAM (referred to as a memory cell) is fabricated with either a static storage cell or a dynamic storage cell. Static storage cells are fabricated with either bipolar or MOS components whereas dynamic storage cells are fabricated with MOS technology. A static RAM stores data in memory so long as the power is on whereas a dynamic RAM (DRAM) requires a refresh cycle.

Static RAMs are relatively expensive devices with limited storage capacity when compared with dynamic RAMs. MOS dynamic random access memory (DRAM) devices that are commercially available have many times the memory capacity of static RAMs and are less expensive. A memory cell in such a device usually includes a single MOS transistor and a charge storage capacitor (which can be provided by the substrate capacitance). Using DRAMs in the above-described frame store, instead of static RAMs, would significantly reduce the cost of the frame store while reducing the number of memory devices needed.

Problems are encountered when trying to implement the use of DRAM's in a frame store having high data rates. For example, the access time of a 64K DRAM is about to 300-500 ns while a frame store operating at 15 MHz requires a 50 to 70 ns memory access time. Access time is that duration needed to read a bit into or out of a memory cell. In addition to the problem of the slow DRAM access time, every memory cell in the DRAM must be refreshed within every four milliseconds due to the charge leakage in the storage capacitor in order to retain the data stored in the memory cells.

The object of the present invention is to use relatively slow DRAM's in a fast frame store.

This object is achieved by a frame store comprising a memory array having a plurality of selectable banks, each bank having a plurality of DRAMs; input and output data buffer means for respectively transferring data in parallel to and from bit cells of DRAMs of selected banks of the memory array; and controller means for selecting first and second banks and for controlling the transfer of data from said input buffer to said first selected bank while at the same time controlling the transfer of data from said second selected bank to said output buffer.

The frame store also includes means for causing the refresh of bit cells of DRAMs in at least one unselected bank simultaneous with the transfer of data to or from the selected memory bank.

FIG. 1 is a block diagram of a conventional prior art 64K bit DRAM;

FIG. 2 is a block diagram of a frame store architecture in accordance with the invention; and

FIG. 3 is a schematic diagram of one section of a memory bank of the frame store in FIG. 2.

Referring now to FIG. 1, a block diagram of a conventional 64K.times.1 bit DRAM 10 is shown. The DRAM 10 is composed of a 256 by 256 bit memory array 12 that is addressed by column decoder 16 and row decoder 18. The desired row and column addresses (A.sub.0 -A.sub.7) are latched by column latch 20 and row latch 22 from the eight bit address bus 24 in response to two TTL strobe pulses, column address select (CAS) and row address select (RAS), both of which are active as low voltage level signals. In response to signals from timing and control 19, the column decoder 16 and the row decoder 18 select a particular column and row in each DRAM in the array 12. At the junction of the selected column and selected row is a selected bit cell which is to be read or written into depending upon the state of WE. Data are read into or out of the memory array 12 through the sense and refresh amplifiers 14 in response to the write enable (WE) strobe pulse. When the WE line is in a high logic level (high voltage), the DRAM 10 is in the read mode; when the WE line is in a low logic level, the DRAM 10 is in the write mode. In addition to latching the row address data, the RAS strobe causes all the non-addressed memory cells in the decoded row in array 12 whose row address is latched into the decoder 18 to be refreshed. The CAS signal when low, in addition to latching the column address data, is used as a chip select for the input and output data buffer 26. When the CAS signal is high, activating the RAS strobe (low level) refreshes all the memory cells of the addressed or decoded row of the bit array 12 without any data being exchanged because the output buffer 26 is in a high-impedance state. When the CAS signal is low, a bit cell is selected and data will be read into or out of that cell to and from buffer 26 depending on the level of the WE signal. All other bit cells of an addressed row will be refreshed. Strobing each of the 256 row addresses with a RAS strobe pulse, therefore causes all the bit cells of the memory array 12 to be refreshed.

Referring now to FIG. 2, a block diagram of a preferred frame store architecture is shown. A memory array 28 is laid out operationally into six memory banks 30-35 with sixty-four 64K.times.1 bit DRAM's 10 in each memory bank. The six memory banks 30-35 are each connected to a separate column address select (CAS) line provided by the column address select circuitry 38. The even memory banks 30, 32 and 34 are connected to an RAS0 select line and the odd memory banks 31, 33 and 35 are connected to an RAS1 select line. The RAS0 and RAS1 voltage signals are generated by the row address select circuitry 40. The memory controller 42 provides the WE signals to each DRAM in memory. All the DRAMs in any given memory bank receive the identical RAS, CAS and WE signals. In order to reduce delay times, the CAS and RAS signals are generated by utilizing fast TTL logic in the controllers 38 and 40.

Since each memory bank has a single column address select (CAS) line to which all the DRAMs in the bank are connected, when the CAS line is low, the DRAMs of a selected bank can be either read from or written into depending upon the state of the WE signal. Alternate memory banks are connected to a common row address select (RAS) line. A refresh cycle for an addressed row of a DRAM can be accomplished by activating (low level) the RAS line of a bank without activating the CAS line of such bank.

For example, if bank 31 is selected to be written into (read mode), CAS2 is low and WE for bank 31 is high. The RAS1 signal corresponding to bank 31 is low and strobes all of the other odd number memory banks (33, 35). At this time CAS4 and CAS6 are high and a "hidden" refresh of the addressed row of the DRAMs of the odd number memory banks 33 and 35 is therefore provided simultaneously with data transfer to bank 31. Let us assume that at the same time, bank 34 is also selected for data transfer (write mode) to buffer 52. In this instance CAS5 is low and WE for bank 34 is low. Refresh of the addressed row of the DRAMs of the even number memory banks 30 and 32 is also accomplished if CAS1 and CAS3 are high.

Double buffering is accomplished by using an input buffer 44 and an output buffer 52. The input buffer 44 contains two sets of data latches, outer latches 46 and inner latches 48. Each set of latches has sixty-four gates. Since the basic memory cycle time (i.e. time required to store one data bit in one memory cell of a DRAM) is about 300 ns, it is impossible to directly store the data into memory at the desired data rates of approximately 70 ns/pixel. Incoming data words (D.sub.0 -D.sub.7) are stored sequentially, one byte or word (eight bits) at a time in a logic circuit 49 in response to a data available signal provided by a microprocessor 43. Each byte of data is then latched into eight latches of the outer set of latches 46. In other words a group of eight outer latches 46 is selected by one of the signals L.sub.0 -L.sub.7 to receive a byte of data. A binary counter 50 responds to a data available signal provided by microprocessor 43 sequentially provides the signals L.sub.0 -L.sub.7. When all of the outer latches are full, eight bytes of data are loaded. These eight bytes of data are then parallel shifted to the inner latches 48 under the control of the signal L.sub.8. Eight bytes of data are then shifted in parallel from the inner latches 48 to a selected memory bank of the memory array 28. It will take approximately 560 ns to refill the outer latches 46 with data providing sufficient time to transfer the eight data words or bytes from the inner latches 48 to the selected bank of the memory array 28. The output buffer 52 operates in a similar manner. The output buffer 52 has two sets of flip-flop latches 54 and 56, respectively. Eight bytes of data are read in parallel into the inner latches 56 in response to signals L.sub.9. Eight bytes of data then are sequentially transferred to the outer latches 54 in response to signals L.sub.10 -L.sub.17. Signals L.sub.10 -L.sub.17 are sequentially produced by counter circuit 59 which responds to a data available signal provided by the microprocessor 43. Eight separate words or bytes of data (D.sub.0 -D.sub.7) are read sequentially (one byte at a time) from the outer latches 54 into a storage device 60 while the inner latches 56 are being filled in parallel with eight new bytes of data from the memory array 28. Storage device 60 can be read out at the system rate. The use of the two sets of latches in both the input and output buffers permits slow DRAMS to be used in a fast frame store.

Reference will now be made to FIG. 3. As previously stated, each memory bank contains sixty-four 64K.times.1 bit DRAM's 36. Each memory bank has eight sections 58. Each section 58 contains eight DRAM's. Each of these eight DRAMs receive one bit of data at a time. In other words, a section 58 is loaded with a byte of data. When eight bytes of data are shifted in parallel from the inner latches 48 to a selected memory bank (for example bank 30), each section 58 of the memory bank 30 receives one byte of data. As shown, each DRAM 10 of section 58 receives a single bit which is delivered to a bit cell having the same address in each DRAM. All the bit cells in the addressed row of every DRAM in the banks 32 and 34 of array 28 are at this time refreshed. Each memory section 58 holds 64K words or bytes and each memory bank holds 512K words or bytes. Because each memory request loads eight bytes or words in parallel, only 64K memory request are needed to completely load or unload a bank.

Each memory cell of every DRAM must be refreshed within four milliseconds or the stored bit of data will be lost due to leakage of the storage cell capacitor. Each memory transfer involves eight words; one word for each memory section 58. A separate memory request to each of the 256 different rows will cause a refresh of an entire memory bank. Furthermore, a memory data transfer operation to one selected bank will result in the refresh of all unselected memory banks commonly connected to the same RAS line. Because alternate banks are tied to the same RAS line, if 256 memory transfers are done in one odd bank, while at the same time 256 memory transfers are done in one even bank, the entire frame store will be refreshed.

The invention has been described in detail with reference to a preferred embodiment thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, 256K DRAMs or one megabit DRAMs could be used in accordance with the invention instead of the 64K bit DRAMs described above .